2 Kbit serial presence detect (SPD) EEPROM
TSSOP8 (DW)
4.4 × 3 mm
UFDFPN8 (MB or MC)
2 x 3 mm
for double data rate (DDR1 and DDR2) DRAM modules
Features
■ 2 Kbit EEPROM for DDR1 and DDR2 serial
presence detect
■ Backward compatible with the M34C02
■ Permanent and reversible software data
protection for lower 128 bytes
■ 100 kHz and 400 kHz I
■ Single supply voltage:
– 1.7 V to 5.5 V
■ Byte and Page Write (up to 16 bytes)
■ Self-timed write cycle
■ Noise filtering
– Schmitt trigger on bus inputs
– Noise filter on bus inputs
■ Enhanced ESD/latch-up protection
■ More than 1 million erase/write cycles
■ More than 40 years’ data retention
■ ECOPACK
■ Packages:
– ECOPACK2
®
(RoHS compliant) packages
®
Halogen-free)
2
C bus serial interface
(RoHS-compliant and
M34E02
M34E02-F
May 2011 Doc ID 10367 Rev 11 1/34
www.st.com
1
Contents M34E02, M34E02-F
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC
2.5 Supply voltage (V
2.5.1 Operating supply voltage V
2.5.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Setting the write-protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.1 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.2 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.3 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16
3.8 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8.4 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Contents
5 Use within a DDR1/DDR2 DRAM module . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Programming the M34E02 and M34E02-F . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Isolated DRAM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 DRAM module inserted in the application motherboard . . . . . . . . . . . . 19
6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 10367 Rev 11 3/34
List of tables M34E02, M34E02-F
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Acknowledge when writing data or defining the write-protection
(instructions with R/W bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Acknowledge when reading the write protection (instructions with R/W bit = 1). . . . . . . . . 20
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating conditions (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Operating conditions (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. DC characteristics (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. DC characteristics (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30
Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/34 Doc ID 10367 Rev 11
M34E02, M34E02-F List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. TSSOP and MLP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Maximum R
Figure 5. I
Figure 6. Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Setting the write protection (WC
Figure 8. Write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Serial presence detect block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30
2
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . . 9
P
= 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Doc ID 10367 Rev 11 5/34
Description M34E02, M34E02-F
1 Description
The M34E02 and M34E02-F are 2 Kbit serial EEPROM memories able to lock permanently
the data in its first half (from location 00h to 7Fh). This facility has been designed specifically
for use in DRAM DIMMs (dual interline memory modules) with serial presence detect (SPD).
All the information concerning the DDR1 or DDR2 configuration of the DRAM module (such
as its access speed, size and organization) can be kept write-protected in the first half of the
memory.
The first half of the memory area can be write-protected using two different software write
protection mechanisms. By sending the device a specific sequence, the first 128 bytes of
the memory become write protected: permanently or resettable. In addition, the devices
allow the entire memory area to be write protected, using the WC
tieing this input to V
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are
CC
).
organized as 256 × 8 bits.
2
I
C uses a two wire serial interface, comprising a bi-directional data line and a clock line.
The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the
2
I
C bus definition to access the memory area and a second device type identifier code
(0110) to define the protection. These codes are used together with the voltage level applied
on the three chip enable inputs (E2, E1, E0).
The devices behave as a slave device in the I
2
C protocol, with all memory operations
synchronized by the serial clock. Read and Write operations are initiated by a Start
condition, generated by the bus master. The Start condition is followed by a device select
code and RW
bit (as described in the Device select code table), terminated by an
acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for WRITE, and after a NoAck for READ.
input (for example by
th
bit
Figure 1. Logic diagram
6
##
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-%
3#,
7#
6/34 Doc ID 10367 Rev 11
-%&
6
33
!)B
M34E02, M34E02-F Description
Figure 2. TSSOP and MLP connections (top view)
-%-%&
% 6
%
33
1. See the Package mechanical data section for package dimensions, and how to identify pin-1.
Table 1. Signal names
Signal names Description
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC Write Control
V
CC
V
SS
Supply voltage
Ground
##
7#%
3#,
3$!6
!)B
Doc ID 10367 Rev 11 7/34
Signal description M34E02, M34E02-F
!IB
6
##
6
33
%
I
6
##
-%
-%&
6
33
%
I
-%
-%&
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor can be connected from Serial Clock
(SCL) to V
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V
the value of the pull-up resistor can be calculated).
. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In
CC
. (Figure 4 indicates how
CC
2.3 Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. In the end application, E0, E1 and
E2 must be directly (not through a pull-up or pull-down resistor) connected to V
establish the device select code. When these inputs are not connected, an internal pulldown circuitry makes (E0,E1,E2) = (0,0,0).
The E0 input is used to detect the V
Figure 3. Device select code
2.4 Write Control (WC)
This input signal is provided for protecting the contents of the whole memory from
inadvertent write operations. Write Control (WC
disable (when driven high) write instructions to the entire memory area or to the Protection
Register.
or VSS to
CC
voltage, when decoding an SWP or CWP instruction.
HV
) is used to enable (when driven low) or
When Write Control (WC
) is tied low or left unconnected, the write protection of the first half
of the memory is determined by the status of the Protection Register.
8/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Signal description
1
10
100
10 100 1000
Bus line capacitor (pF)
Bus line pull-up resistor
(k
)
When t
LOW
= 1.3 µs (min value for
f
C
= 400 kHz), the R
bus
× C
bus
time constant m ust be below the
400 ns time constant line
represented on the left.
2.5 Supply voltage (VCC)
2.5.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Tab l e 8 ). In order to
CC
secure a stable DC supply voltage, it is recommended to decouple the V
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t
2.5.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Ta bl e 8 and the rise time must not vary faster than 1 V/µs.
2.5.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches the internal reset threshold voltage (this threshold is lower than the minimum V
operating voltage defined in Ta bl e 8 ).
When V
Power mode. However, the device must not be accessed until V
stable V
In a similar way, during power-down (continuous decrease in V
below the power-on reset threshold voltage, the device stops responding to any instruction
sent to it.
passes over the POR threshold, the device is reset and enters the Standby
CC
voltage within the specified [VCC(min), VCC(max)] range.
CC
CC
line with a
CC
CC/VSS
reaches a valid and
CC
), as soon as VCC drops
CC
).
W
package
CC
CC
2.5.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
Figure 4. Maximum R
Here R
× C
bus
4 kΩ
bus
30 pF
value versus bus parasitic capacitance (C) for an I2C bus
P
R
bus
× C
bus
= 120 ns
V
CC
R
SCL
SDA
bus
M24xxx
C
bus
ai14796b
= 400 ns
I²C bus
master
Doc ID 10367 Rev 11 9/34
Signal description M34E02, M34E02-F
Figure 5. I2C bus protocol
SCL
SDA
Start
condition
SCL
SDA
Start
condition
SCL
SDA
Table 2. Device select code
1 23 7 89
MSB
1 23 7 89
MSB ACK
Chip Enable
signals
SDA
Input
SDA
Change
Stop
condition
ACK
Stop
condition
AI00792c
Device type identifier Chip Enable bits RW
(1)
b7
b6 b5 b4 b3 b2 b1 b0
Memory area select
code (two arrays)
(2)
Set write protection
(SWP)
Clear write protection
(CWP)
Permanently set write
protection (PSWP)
(2)
Read SWP V
Read CWP V
Read PSWP
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. VHV is defined in Table 13.
(2)
E2 E1 E0 1 0 1 0 E2 E1 E0 RW
V
SSVSSVHV
V
SSVCCVHV
E2 E1 E0 E2 E1 E0 0
SSVSSVHV
SSVCCVHV
(3)
(3)
0110
(3)
(3)
E2 E1 E0 E2 E1 E0 1
10/34 Doc ID 10367 Rev 11
0010
0110
0011
0111
M34E02, M34E02-F Device operation
3 Device operation
The device supports the I2C protocol. This is summarized in Figure 5 Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The memory device is always a slave in all
communication.
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal EEPROM Write cycle.
3.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.
th
clock pulse period, the receiver pulls Serial Data (SDA) low to
3.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Doc ID 10367 Rev 11 11/34
Device operation M34E02, M34E02-F
Default EEPROM memory area
state before write access
to the Protect Register
AI01936C
Standard
Array
FFh
Standard
Array
80h
7Fh
00h
Standard
Array
FFh
Write
Protected
Array
80h
7Fh
00h
State of the EEPROM memory
area after write access
to the Protect Register
Memory
Area
3.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta bl e 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is
1010b; to access the write-protection settings, it is 0110b.
Up to eight memory devices can be connected on a single I
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
th
The 8
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
2
C bus. Each one is given a
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 3. Operating modes
Mode RW bit WC
Current Address Read 1 X 1 Start, Device Select, RW
0X
Random Address Read
1 X reStart, Device Select, RW
Sequential Read 1 X ≥ 1
Byte Write 0 V
Page Write 0 V
1. X = V
IH
or V
.
IL
(1)
Bytes Initial Sequence
= 1
Start, Device Select, RW
= 0, Address
1
= 1
Similar to Current or Random Address
Read
IL
IL
1 Start, Device Select, RW = 0
≤ 16 Start, Device Select, RW = 0
Figure 6. Result of setting the write protection
12/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Device operation
START
SDA LINE
AI01935B
ACK
WORD
ADDRESS
VALUE
(DON'T CARE)
ACK
DATA
VALUE
(DON'T CARE)
STOP
ACK
CONTROL
BYTE
BUS ACTIVITY
MASTER
BUS ACTIVITY
3.6 Setting the write-protection
The M34E02 and M34E02-F have a hardware write-protection feature, using the Write
Control (WC
whole instruction sequence. When Write Control (WC
(addresses 00h to FFh) is write protected. When Write Control (WC
protection of the memory array is dependent on whether software write-protection has been
set.
Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh)
to be write protected irrespective of subsequent states of the Write Control (WC
Software write-protection is handled by three instructions:
● SWP: Set Write Protection
● CWP: Clear Write Protection
● PSWP: Permanently Set Write Protection
The level of write-protection (set or cleared) that has been defined using these instructions,
remains defined even after a power cycle.
3.6.1 SWP and CWP
If the software write-protection has been set with the SWP instruction, it can be cleared
again with a CWP instruction.
) signal. This signal can be driven high or low, and must be held constant for the
) is held high, the whole memory array
) is held low, the write
) signal.
The two instructions (SWP and CWP) have the same format as a Byte Write instruction, but
with a different device type identifier (as shown in Tab le 2 ). Like the Byte Write instruction, it
is followed by an address byte and a data byte, but in this case the contents are all “Don’t
Care” (Figure 7). Another difference is that the voltage, V
and specific logical levels must be applied on the other two (E1 and E2, as shown in
Ta bl e 2 ).
3.6.2 PSWP
If the software write-protection has been set with the PSWP instruction, the first 128 bytes of
the memory are permanently write-protected. This write-protection cannot be cleared by
any instruction, or by power-cycling the device, and regardless the state of Write Control
(WC
). Also, once the PSWP instruction has been successfully executed, the M34E02 and
M34E02-F no longer acknowledge any instruction (with a device type identifier of 0110) to
access the write-protection settings.
Figure 7. Setting the write protection (WC
= 0)
, must be applied on the E0 pin,
HV
Doc ID 10367 Rev 11 13/34
Device operation M34E02, M34E02-F
3.7 Write operations
Following a Start condition the bus master sends a device select code with the RW bit reset
to 0. The device acknowledges this, as shown in Figure 8, and waits for an address byte.
The device responds to the address byte with an acknowledge bit, and then waits for the
data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the
internal Write cycle.
During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and
the device does not respond to any requests.
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal
3.7.1 Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is hardware write-protected, the device replies to the data byte with
NoAck, and the location is not modified. If, instead, the addressed location is not Writeprotected, the device replies with Ack. The bus master terminates the transfer by generating
a Stop condition, as shown in Figure 8
3.7.2 Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC
the device replies to the data byte with NoAck, and the locations are not modified. After each
byte is transferred, the internal byte address counter (the 4 least significant address bits
only) is incremented. The transfer is terminated by the bus master generating a Stop
condition.
) is low. If the addressed location is hardware write-protected,
14/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Device operation
Figure 8. Write mode sequences in a non write-protected area
ACK ACK ACK
Byte Write Device select Byte address
Start
Page Write Device select Byte address Data in 1 Data in 2
Start
ACK ACK
R/W
ACK ACK ACK
R/W
Data in N
Stop
Figure 9. Write cycle polling flowchart using ACK
WRITE cycle
in progress
Start condition
Device select
with RW = 0
Data in
Stop
AI01941b
First byte of instruction
with RW = 0 already
decoded by the device
ReStart
Stop
NO
returned
operation is
addressing the
memory
ACK
YES
Next
WRITE operation
Continue the
WRITE operation
YESNO
Data for the
Send address
and receive ACK
Start
condition
YESNO
Device select
with RW = 1
Continue the
Random READ operation
AI01847d
Doc ID 10367 Rev 11 15/34
Device operation M34E02, M34E02-F
3.7.3 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in Ta bl e 1 4 , but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 9, is:
● Initial condition: a Write cycle is in progress.
● Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
● Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
w
) is
3.8 Read operations
Read operations are performed independently of whether hardware or software protection
has been set.
The device has an internal address counter which is incremented each time a byte is read.
3.8.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
3.8.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the RW
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
3.8.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
bit set to 1. The device
bit set to 1. The device acknowledges this, and
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
16/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Device operation
Start
Dev select * Byte address
Start
Dev select Data out 1
AI01942b
Data out N
Stop
Start
Current
Address
Read
Dev select Data out
Random
Address
Read
Stop
Start
Dev select * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev select * Byte address
Sequential
Random
Read
Start
Dev select * Data out 1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
3.8.4 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9
th
bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
Figure 10. Read mode sequences
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 3rd bytes) must
be identical.
Doc ID 10367 Rev 11 17/34
Initial delivery state M34E02, M34E02-F
4 Initial delivery state
The device is delivered with all bits in the memory array set to ‘1’ (each Byte contains FFh).
5 Use within a DDR1/DDR2 DRAM module
In the application, the M34E02/M34E02-F is soldered directly in the printed circuit module.
The three Chip Enable inputs (E0, E1, E2) must be connected to V
without using a pull-up or pull-down resistor) through the DIMM socket (see Tab l e 4 ). The
pull-up resistors needed for normal behavior of the I
2
C bus are connected on the I2C bus of
the mother-board (as shown in Figure 11).
or VCC directly (that is
SS
The Write Control (WC
connecting it to V
Table 4. DRAM DIMM connections
) of the M34E02/M34E02-F can be left unconnected. However,
is recommended, to maintain full read and write access.
SS
DIMM position E2 E1 E0
0 V
1 V
2 V
3 V
4 V
5 V
6 V
7 V
SS
SS
SS
SS
CC
CC
CC
CC
V
V
V
V
5.1 Programming the M34E02 and M34E02-F
The situations in which the M34E02 and M34E02-F are programmed can be considered
under two headings:
● when the DDR2 DRAM is isolated (not inserted on the PCB motherboard)
● when the DDR2 DRAM is inserted on the PCB motherboard
V
SS
V
SS
CC
CC
V
SS
V
SS
CC
CC
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
5.1.1 Isolated DRAM module
With specific programming equipment, it is possible to define the M34E02/M34E02-F
content, using Byte and Page Write instructions, and its write-protection using the SWP and
CWP instructions. To issue the SWP and CWP instructions, the DRAM module must be
inserted in a specific slot where the E0 signal can be driven to V
instruction. This programming step is mainly intended for use by DRAM module makers,
whose end application manufacturers will want to clear this write-protection with the CWP
on their own specific programming equipment, to modify the lower 128 Bytes, and finally to
set permanently the write-protection with the PSWP instruction.
18/34 Doc ID 10367 Rev 11
during the whole
HV
M34E02, M34E02-F Use within a DDR1/DDR2 DRAM module
5.1.2 DRAM module inserted in the application motherboard
As the final application cannot drive the E0 pin to VHV, the only possible action is to freeze
the write-protection with the PSWP instruction.
Ta bl e 5 and Ta bl e 6 show how the Ack bits can be used to identify the write-protection
status.
Table 5. Acknowledge when writing data or defining the write-protection
(instructions with R/W bit = 0)
Status
Permanently
protected
Protected
with SWP
WC
input
level
X
0 PSWP Ack
1 CWP Ack
Instruction Ack Address Ack Data byte Ack
PSWP, SWP or
CWP
Page or Byte Write
in lower 128 bytes
SWP NoAck
CWP Ack
Page or Byte Write
in lower 128 bytes
SWP NoAck
PSWP Ack
Page or Byte Write Ack Address Ack Data NoAck No
NoAck
Ack Address Ack Data NoAck No
Ack Address Ack Data NoAck No
Not
significant
Not
significant
Not
significant
Not
significant
Not
significant
Not
significant
Not
significant
NoAck
NoAck
Ack
Ack
NoAck
Ack
Ack
Not
significant
Not
significant
Not
significant
Not
significant
Not
significant
Not
significant
Not
significant
NoAck No
NoAck No
Ack Ye s
Ack Ye s
NoAck No
NoAck No
NoAck No
Write
cycle
(tW)
Not
Protected
0
1
PSWP, SWP or
CWP
Page or Byte Write Ack Address Ack Data Ack Ye s
PSWP, SWP or
CWP
Page or Byte Write Ack Address Ack Data NoAck No
Doc ID 10367 Rev 11 19/34
Ack
Ack
Not
significant
Not
significant
Ack
Ack
Not
significant
Not
significant
Ack Ye s
NoAck No
Use within a DDR1/DDR2 DRAM module M34E02, M34E02-F
Table 6. Acknowledge when reading the write protection (instructions with R/W
bit = 1)
Status Instruction Ack Address Ack Data byte Ack
Permanently
protected
PSWP, SWP or CWP NoAck Not significant NoAck Not significant NoAck
SWP NoAck Not significant NoAck Not significant NoAck
Protected with
SWP
CWP Ack Not significant NoAck Not significant NoAck
PSWP Ack Not significant NoAck Not significant NoAck
Not protected PSWP, SWP or CWP Ack Not significant NoAck Not significant NoAck
20/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Use within a DDR1/DDR2 DRAM module
R = 4.7 kΩ
AI01937b
DRAM module slot number 7
SDASCLE0E1E2
V
CC
DRAM module slot number 6
SDASCLE0E1E2
DRAM module slot number 5
SDASCLE0E1E2
DRAM module slot number 4
SDASCLE0E1E2
DRAM module slot number 3
SDASCLE0E1E2
DRAM module slot number 2
SDASCLE0E1E2
V
CC
DRAM module slot number 1
SDASCLE0E1E2
DRAM module slot number 0
SDASCLE0E1E2
V
SS
V
SS
V
SS
V
CC
V
SS
VSSV
CC
V
CC
V
SS
V
CC
VCCV
SS
V
SS
V
CC
SCL line SDA line
From the motherboard
I
2
C master controller
Figure 11. Serial presence detect block diagram
1. E0, E1 and E2 are wired at each DRAM module slot in a binary sequence for a maximum of 8 devices.
2. Common clock and common data are shared across all the devices.
Doc ID 10367 Rev 11 21/34
Maximum rating M34E02, M34E02-F
6 Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 7. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient temperature with power applied –55 130 °C
T
STG
V
Storage temperature –65 150 °C
Input or output range
IO
E0
Others
–0.50
–0.50
10.0
6.5
V
I
OL
V
V
ESD
1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
DC output current (SDA = 0) - 5 mA
Supply voltage –0.5 6.5 V
CC
Electrostatic discharge voltage (human body model)
(1)
–4000 4000 V
22/34 Doc ID 10367 Rev 11
M34E02, M34E02-F DC and AC parameters
AI00825B
0.8V
CC
0.2V
CC
0.7V
CC
0.3V
CC
Input and Output
Timing Reference Levels
Input Levels
7 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8. Operating conditions (for temperature range 1 devices)
Symbol Parameter Min. Max. Unit
V
CC
T
Table 9. Operating conditions (for temperature range 6 devices)
Supply voltage 1.7 3.6 V
Ambient operating temperature 0 70 °C
A
Symbol Parameter Min. Max. Unit
V
CC
T
Table 10. AC measurement conditions
Supply voltage 1.7 5.5 V
Ambient operating temperature –40 +85 °C
A
Symbol Parameter Min. Max. Unit
C
Load capacitance 100 pF
L
SCL input rise and fall time,
SDA input fall time
Input levels 0.2V
Input and output timing reference levels 0.3V
to 0.8V
CC
to 0.7V
CC
50 ns
CC
CC
Figure 12. AC measurement I/O waveform
V
V
Doc ID 10367 Rev 11 23/34
DC and AC parameters M34E02, M34E02-F
Table 11. Input parameters
Symbol Parameter
(1)
Test condition Min. Max. Unit
C
C
Z
Z
Z
WCL
Z
WCH
t
1. Characterized, not tested in production.
Table 12. DC characteristics (for temperature range 1 devices)
Symbol Parameter
I
Input capacitance (SDA) 8 pF
IN
Input capacitance (other pins) 6 pF
IN
Ei (E0, E1, E2) input impedance VIN < 0.3V
EiL
Ei (E0, E1, E2) input impedance VIN > 0.7V
EiH
WC input impedance VIN < 0.3V
WC input impedance VIN > 0.7V
Pulse width ignored (input filter on
NS
SCL and SDA)
CC
CC
CC
CC
30 kΩ
800 kΩ
5kΩ
500 kΩ
Test condition (in addition to
those in Tabl e 8 )
Input leakage current
I
LI
(SCL, SDA)
Output leakage current
LO
SDA in Hi-Z, external voltage
applied on SDA: V
= VSS or V
V
IN
SS
CC
or V
CC
VCC = 1.7 V, fc = 100 kHz 1 mA
I
I
CC1
V
V
Supply current (read)
CC
Standby supply current
Input low voltage
IL
(SCL, SDA, WC
Input high voltage
IH
(SCL, SDA, WC)
= 3.6 V, fc = 100 kHz 2 mA
V
CC
(1)
CC
CC
,
= 3.6 V
(1)
,
= 1.7 V
Device not selected
= VSS or VCC, V
V
IN
Device not selected
= VSS or VCC, V
V
IN
2.5 ≤ V
CC
)
1.7 V ≤ V
< 2.5 V –0.45 0.25V
CC
100 ns
Min Max Unit
± 2 µA
± 2 µA
2µA
1µA
–0.45 0.3 V
0.7V
CCVCC
CC
CC
+1 V
V
V
V
V
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the
completion of the internal write cycle t
E0 high voltage VHV – VCC ≥ 4.8 V 7 10 V
HV
I
= 2.1 mA, 2.2 V ≤ VCC ≤ 3.6 V 0.4 V
Output low voltage
OL
OL
I
= 0.7 mA, VCC = 1.7 V 0.2 V
OL
(tW is triggered by the correct decoding of a write command).
W
24/34 Doc ID 10367 Rev 11
M34E02, M34E02-F DC and AC parameters
Table 13. DC characteristics (for temperature range 6 devices)
Symbol Parameter
Input leakage current
I
LI
(SCL, SDA)
I
I
I
CC1
V
V
V
V
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the
completion of the internal write cycle t
Output leakage current
LO
Supply current (read)
CC
Standby supply current
Input low voltage
IL
(SCL, SDA, WC
Input high voltage
IH
(SCL, SDA, WC
E0 high voltage VHV – VCC ≥ 4.8 V 7 10 V
HV
Output low voltage
OL
)
)
Test condition (in addition to
those in Tabl e 9 )
V
= VSS or V
IN
CC
SDA in Hi-Z, external voltage
applied on SDA: V
V
< 2.5 V, fc = 400 kHz 1 mA
CC
V
≥ 2.5 V, fc = 400 kHz 3 mA
CC
Device not selected
V
= VSS or VCC, V
IN
Device not selected
V
= VSS or VCC, V
IN
2.5 ≤ V
1.8 V ≤ V
= 3.0 mA, V
I
OL
I
= 2.1 mA, VCC = 2.5 V 0.4 V
OL
= 0.7 mA, VCC = 1.7 V 0.2 V
I
OL
(tW is triggered by the correct decoding of a write command).
W
or V
SS
CC
(1)
,
≥ 2.5 V
CC
(1)
,
< 2.5 V
CC
CC
< 2.5 V –0.45 0.25V
CC
= 5.5 V 0.4 V
CC
Min Max Unit
± 2 µA
± 2 µA
–0.45 0.3 V
0.7V
CCVCC
2µA
1µA
CC
CC
+1 V
V
V
Doc ID 10367 Rev 11 25/34
DC and AC parameters M34E02, M34E02-F
Table 14. AC characteristics
Test conditions specified in Tab l e 10 , Ta b l e 8 and Ta ble 9
Symbol Alt. Parameter Min. Max. Unit
f
C
t
CHCL
t
CLCH
t
DL1DL2
t
XH1XH2
t
XL1XL2
t
DXCX
t
CLDX
t
CLQX
(3)(4)
t
CLQV
t
CHDL
t
DLCL
t
CHDH
t
DHDL
t
W
1. Sampled only, not 100% tested.
2. Values recommended by I²C-bus/Fast-Mode specification.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. t
CLQV
0.7V
5. For a re-Start condition, or following a Write cycle.
f
t
HIGH
t
LOW
(1)
(2)
(2)
t
SU:DAT
t
HD:DAT
t
t
(5)
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
, assuming that the R
CC
Clock frequency 400 kHz
SCL
Clock pulse width high 600 ns
Clock pulse width low 1300 ns
t
SDA (out) fall time 20 100 ns
F
t
Input signal rise time 20 300 ns
R
t
Input signal fall time 20 300 ns
F
Data in set up time 100 ns
Data in hold time 0 ns
Data out hold time 200 ns
DH
Clock low to next data valid (access time) 200 900 ns
AA
Start condition setup time 600 ns
Start condition hold time 600 ns
Stop condition setup time 600 ns
Time between Stop condition and next Start
condition
Write time 5 ms
WR
× C
bus
time constant is within the values specified in Figure 4).
bus
1300 ns
26/34 Doc ID 10367 Rev 11
M34E02, M34E02-F DC and AC parameters
SCL
SDA In
SCL
SDA Out
SCL
SDA In
tCHCL
tDLCL
tCHDL
Start
condition
tCLCH
tDXCXtCLDX
SDA
Input
SDA
Change
tCHDH tDHDL
Stop
condition
Data valid
tCLQV tCLQX
tCHDH
Stop
condition
tCHDL
Start
condition
Write cycle
tW
AI00795f
Start
condition
tCHCL
tXH1XH2
tXH1XH2
tXL1XL2
tXL1XL2
Data valid
tDL1DL2
Figure 13. AC waveforms
Doc ID 10367 Rev 11 27/34
Package mechanical data M34E02, M34E02-F
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
28/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Package mechanical data
$
%
:7?-%E
!
!
EEE
,
E
B
$
,
%
,
,
E B
$
,
%
,
0IN
+
+
-" -#
Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline
1. Drawing is not to scale.
2. The central pad (area E2 by D2 in the above illustration) is pulled, internally, to V
to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
. It must not be allowed
SS
3. The circle in the top view of the package indicates the position of pin 1.
Table 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MB) 0.800 0.0315
K (rev MC) 0.300 0.0118
L (rev MB) 0.450 0.400 0.500 0.0177 0.0157 0.0197
L (rev MC) 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
(2)
eee
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
Doc ID 10367 Rev 11 29/34
Package mechanical data M34E02, M34E02-F
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
2. The circle around the number 1 in the top view of the package indicates the position of pin 1. The numbers
4, 5 and 8 indicate the positions of pins 4, 5 and 8, respectively.
Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
(1)
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
N8 8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
30/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Part numbering
9 Part numbering
Table 17. Ordering information scheme
Example: M34E02 – F DW 1 T P
Device type
M34 = ASSP I
Device function
E02 = 2 Kbit (256 × 8) SPD (serial presence detect) for DDR1 and DDR2
Operating voltage
F = V
CC
F = VCC = 1.7 to 5.5 V over –40 °C to 85 °C
2
C serial access EEPROM
= 1.7 to 3.6 V over 0°C to 70 °C
(1)
or
(2)
Package
MB or MC= UDFDFPN8 (MLP8)
DW = TSSOP8 (4.4 × 3 mm body size)
Temperature range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
blank = Standard packing
T = Tape & reel packing
Plating technology
P or G = ECOPACK (RoHS compliant)
1. The 1.7 to 3.6 V operating voltage range is available only on temperature range 1 devices.
2. The 1.7 to 5.5 V operating voltage range is available only on temperature range 6 devices.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 10367 Rev 11 31/34
Revision history M34E02, M34E02-F
10 Revision history
Table 18. Document revision history
Date Revision Changes
13-Nov-2003 1.0 First release
TSSOP8 4.4x3 package replaces TSSOP8 3x3 (MSOP8) package.
01-Dec-2003 1.1
29-Mar-2004 1.2
14-Apr-2004 2.0 First public release
24-Nov-2004 3.0
11-Mar-2005 4.0
28 -Apr-2005 5.0
10-Apr-2006 6
Correction to sentence in “Setting the Write Protection”. Correction to
specification of tNS values.
Always NoACK after Address and Data bytes in Tab l e 6. Improvement in
and VCC (min) in Absolute Maximum Ratings table. IOL changed for
V
IO
test condition of VOL. MLP package mechanical data respecified.
Soldering temperature information clarified for RoHS compliant devices.
Direct connection of E0, E1, E2 to V
E1, E2) and Use within a DDR1/DDR2 DRAM module paragraphs). Z
and Z
parameters added to Table 11: Input parameters. E0, E1, E2
EiH
removed from the Parameter descriptions of V
and VCC (see Chip Enable (E0,
SS
and VIH in Table 13: DC
IL
EiL
characteristics (for temperature range 6 devices).
Document status promoted from Product Preview to full Datasheet.
Datasheet title changed. Features revised.
Plating Technology options updated in Table 17: Ordering information
scheme.
Resistance and capacitance renamed in Figure 4: Maximum RP value
versus bus parasitic capacitance (C) for an I2C bus.
Text in Power On Reset changed. Noise filter value in Table 11: Input
parameters modified. ICC value 2mA, when Vcc=3/6V, added to Table 13:
DC characteristics (for temperature range 6 devices).
In Table 14: AC characteristics: Frequency f
400kHz, related AC timings (t
t
, t
CHDH
) also modified.
DHDL
CHCL
, t
CLCH
changed from 100kHz to
C
, t
, t
CLQV
max, t
DXCX
CHDX
, t
DLCL
Power On Reset paragraph removed replaced by Internal device reset.
Figure 3: Device select code inserted. I
modified in Table 13: DC
CC1
characteristics (for temperature range 6 devices).
Note 3 added to Figure 14 and Note 2 added to Figure 15
All packages are ECOPACK® (see text added under Description and Part
numbering, T
removed from Table 7: Absolute maximum ratings).
LEAD
,
32/34 Doc ID 10367 Rev 11
M34E02, M34E02-F Revision history
Table 18. Document revision history (continued)
Date Revision Changes
Datasheet title and Features on page 1 modified: the device can be used
with DDR1 and DDR2 DRAM configurations.
Temperature range 6 added, operating voltage range V
device temperature range 6. IOL added to and TA modified in Ta bl e 7 :
Absolute maximum ratings.
, ICC and VIL modified in Table 13: DC characteristics (for temperature
I
LO
range 6 devices). Table 14: AC characteristics added. Table 13: DC
characteristics (for temperature range 6 devices) modified. Figure 13: AC
18-Mar-2009 7
waveforms modified.
Figure 4: Maximum RP value versus bus parasitic capacitance (C) for an
I2C bus updated. Note removed below Figure 11: Serial presence detect
block diagram.
UFDFPN8 package specifications updated (see Table 15: UFDFPN8
(MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm,
data).
Blank option removed under plating technology in Table 17: Ordering
information scheme. Small text changes.
Section 2.5.2: Power-up conditions and Section 2.5.3: Device reset
updated. Figure 4: Maximum RP value versus bus parasitic capacitance
25-Sep-2009 8
(C) for an I2C bus modified.
modified in Table 11: Input parameters.
t
NS
ICC and VIL test conditions extended in Table 12: DC characteristics (for
temperature range 1 devices).
Test condition updated in Table 12: DC characteristics (for temperature
range 1 devices) and Table 13: DC characteristics (for temperature range
01-Apr-2010 9
6 devices)
Updated Figure 14: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat
package no lead 2 x 3 mm, outline and Table 15: UFDFPN8 (MLP8) 8lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data
Added M34E02-F part number.
Added ambient temperature with power applied in Table 7: Absolute
maximum ratings.
conditions in Table 12: DC characteristics (for temperature
CC1
in Table 14: AC characteristics. Updated
CLQV
23-Jul-2010 10
Updated I
range 1 devices).
Added Note 4 for t
Figure 13: AC waveforms.
t
CHDX
replaced by t
in Figure 13: AC waveforms.
CHDL
Modified MC package outline in Figure 14: UFDFPN8 (MLP8) 8-lead ultra
thin fine pitch dual flat package no lead 2 x 3 mm, outline.
27-May-2011 11 Updated MLP8 package data.
extended in
CC
Doc ID 10367 Rev 11 33/34
M34E02, M34E02-F
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34/34 Doc ID 10367 Rev 11
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