ST M34C02 User Manual

M34C02

2 Kbit Serial I²C Bus EEPROM

For DIMM Serial Presence Detect

■Two Wire I2C Serial Interface Supports 400 kHz Protocol

■Single Supply Voltage:

–2.5V to 5.5V for M34C02-W

–2.2V to 5.5V for M34C02-L

■Software Data Protection for lower 128 bytes

■BYTE and PAGE WRITE (up to 16 bytes)

■RANDOM and SEQUENTIAL READ Modes

■Self-Timed Programming Cycle

■Automatic Address Incrementing

■Enhanced ESD/Latch-Up Protection

■1 Million Erase/Write Cycles (minimum)

■40 Year Data Retention (minimum)

DESCRIPTION

The M34C02 is a 2 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory.

This bottom half of the memory area can be writeprotected using a specially designed software write protection mechanism. By sending the device a specific sequence, the first 128 bytes of

Table 1. Signal Names

	E0, E1, E2		Chip Enable Inputs

	SDA		Serial Data/Address Input/
			Output

	SCL		Serial Clock

			Write Control
	WC		Write Control

	VCC		Supply Voltage
	VSS		Ground

	8
	1
	PSDIP8 (BN)
	0.25 mm frame
8	8
1	1
SO8 (MN)	TSSOP8 (DW)
150 mil width	169 mil width

Figure 1. Logic Diagram

VCC

E0-E2

SDA

SCL M34C02

VSS

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Figure 2A. DIP Connections

Figure 2B. SO and TSSOP Connections

	M34C02				M34C02
		8
E0	1	8	VCC	E0	1	8	VCC
E1	2	7	WC	E1	2	7	WC
E2	3	6	SCL	E2	3	6	SCL
VSS	4	5	SDA	VSS	4	5	SDA
		AI01932				AI01933

the memory become permanently write protected. Care must be taken when using this sequence as its effect cannot be reversed. In addition, the device allows the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC).

The M34C02 is a 2 Kbit electrically erasable programmable memory (EEPROM), organized as 256x8 bits, fabricated with STMicroelectronics’ High Endurance, Advanced, CMOS technology. This guarantees an endurance typically well above one million Erase/Write cycles, with a data retention of 40 years. These memory devices operate with a power supply down to 2.2 V for the M34C02-L.

The M34C02 is available in Plastic Dual In-line, Plastic Small Outline and Thin Shrink Small Outline packages.

These memory devices are compatible with the I2C memory standard. This is a two wire serial

interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second Device Type Identifier Code (0110) to access the Protection Register. These codes are used together with three chip enable inputs (E2, E1, E0) so that up to eight 2 Kbit devices may be attached to the I²C bus and selected individually.

The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission.

Table 2. Absolute Maximum Ratings 1

Symbol	Parameter		Value	Unit

TA	Ambient Operating Temperature		-40 to 85	°C

TSTG	Storage Temperature		-65 to 150	°C

		PSDIP8: 10 sec	260
TLEAD	Lead Temperature during Soldering	SO8: 40 sec	215	°C
		TSSOP8: 40 sec	215

VIO	Input or Output range		-0.6 to 6.5	V

VCC	Supply Voltage		-0.3 to 6.5	V

VESD	Electrostatic Discharge Voltage (Human Body model) 2		4000	V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

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When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the VCC voltage has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal.

SIGNAL DESCRIPTION Serial Clock (SCL)

The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the master has a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open

drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code.

Write Control (WC)

A hardware Write Control (WC, pin 7) is provided for protecting the contents of the whole memory from erroneous erase/write cycles. The Write Control signal is used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memory area or to the Protection Register.

When WC is tied to VSS or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register.

DEVICE OPERATION

The memory device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communication.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

Maximum RP value (kΩ)

VCC

SDA

MASTER

CBUS

SCL

fc = 100kHz

fc = 400kHz

CBUS

100

1000

CBUS (pF)

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Figure 4. I2C Bus Protocol

SCL
SDA
START	SDA	SDA	STOP
CONDITION	INPUT	CHANGE	CONDITION

SCL	1	2	3	7	8	9
SDA	MSB					ACK
	START
	CONDITION
SCL	1	2	3	7	8	9
SDA	MSB					ACK

STOP

CONDITION

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Start Condition

Stop Condition

START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.

Table 3. Device Select Code 1

STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, provided that it is followed by a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write

		Device Type Identifier				Chip Enable		RW
	b7	b6	b5	b4	b3	b2	b1	b0
Memory Area Select Code (two arrays)	1	0	1	0	E2	E1	E0	RW
Protection Register Select Code	0	1	1	0	E2	E1	E0	RW

Note: 1. The most significant bit (b7) is sent first.

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Table 4. Operating Modes

Mode

bit

Bytes

Initial Sequence

Current Address Read

= ‘1’

START, Device Select, RW

= ‘0’, Address

Random Address Read

START, Device Select, RW

= ‘1’

reSTART, Device Select, RW

Sequential Read

³ 1

Similar to Current or Random Address Read

Byte Write

VIL

= ‘0’

START, Device Select, RW

Page Write

VIL

£ 16

= ‘0’

START, Device Select, RW

Note: 1. X = VIH or VIL.

command triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low.

Memory Addressing

To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0).

To address the memory array, the 4-bit Device Type Identifier is 1010b. To address the Protection Register, it is 0110b.

If all three chip enable inputs are connected, up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on its Chip Enable inputs. When the Device Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the same as the pattern applied to its Chip Enable pins.

The 8th bit is the read or write bit (RW). This bit is set to ‘1’ for read and ‘0’ for write operations. If a

match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match the Device Select code, it will deselect itself from the bus, and go into standby mode.

Write Operations

Following a START condition the master sends a Device Select Code with the RW bit set to ’0’, as shown in Table 4. The memory acknowledges this, and waits for an address byte. The memory responds to the address byte with an acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC input pin is taken high.

Byte Write

In the Byte Write mode, after the Device Select Code and the address byte, the master sends one data byte. If the addressed location is in a write protected area, the memory replies with a NoAck, and the location is not modified. If, instead, the addressed location is not in a write protected area, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition.

Page Write

The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the most significant memory address bits (b7-b4) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data sheet).

The master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not modified. After each byte is transferred, the internal byte address counter (the 4 least

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Figure 5. How to Set the Write Protection

			FFh			FFh
		Standard			Standard
Memory		Array			Array
Memory			80h			80h
Area			80h			80h
Area		Standard	7Fh		Write	7Fh
					Write
					Protected
		Array			Protected
		Array			Array
			00h		Array	00h
			00h			00h
	Default EEPROM memory area			State of the EEPROM memory
	state before write access			area after write access
	to the Protect Register			to the Protect Register

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Figure 6. Write Mode Sequences in the Non Write-Protected Area

BYTE WRITE

START

PAGE WRITE

START

	ACK	ACK
DEV SEL	BYTE ADDR
	R/W
	ACK	ACK
DEV SEL	BYTE ADDR

R/W

ACK ACK

DATA IN N

STOP

	ACK
DATA IN
	STOP
	ACK
DATA IN 1	DATA IN 2

AI01941

significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition.

When the master generates a STOP condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. A STOP condition at any other time does not trigger the internal write cycle.

During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests.

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum write time (tw) is shown in Table 9, but the typical time is shorter. To make use of this, an Ack polling sequence can be used by the master.

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