ST M34C02 User Manual

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M34C02

2 Kbit Serial I²C Bus EEPROM

For DIM M Serial P resence Detect

■ Two Wire I

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 2.5V to 5.5V for M34C02-W
– 2.2V to 5.5V for M34C02-L

■ Software Data Protection for lower 128 bytes

■ BYTE and PAGE WRITE (up to 16 bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim ed P ro gr a m ming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Protection

■ 1 Million Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.

This bottom half of the memory area can be write­protected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of

8

PSDIP8 (BN)

0.25 mm frame

8

1

SO8 (MN)

150 mil width

Figure 1. Logic Diagram

V

CC

1

8

1

TSSOP8 (DW)

169 mil width

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs
SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC
V

CC

V

SS

Write Control

Supply Voltage

Ground

3

E0-E2 SDA

SCL

WC

M34C02

V

SS

AI01931

1/19December 1999

M34C02

Figure 2A. DIP Connections

M34C02

1

E0 V

2
3

E2

4

SS

8
7
6
5

AI01932

CC

WCE1
SCL
SDAV

the memory become permanently write protected.
Care must be taken w hen us i ng this s equence as
its effect cannot be reversed. In addition, the
device allows the entire m emory area to be write
protected, using the WC
tieing this input to V

input (for example by

).

CC

The M34C02 is a 2 Kbit electrically erasable pro­grammable memory (EEPROM), organized as

256x8 bits, fabricated with STMicroelectronics’
High Endurance, Advanced, CMOS technology.
This guarantees an endurance typically well
above one millio n Erase/Wri te cycles, with a data
retention of 40 years. These memory devices
operate with a power supply down to 2.2 V for the
M34C02-L.

The M34C02 is available in Plastic Dual In-line,
Plastic Small Outline and Thin Shrink Small
Outline packages.

These memory devices are compatible with the

2

C memory standard. This is a two wire serial

I

Figure 2B. SO and TSSOP Connections

M34C02

1

E0 V

2
3

E2

SS

4

8
7
6
5

AI01933

CC

WCE1
SCL
SDAV

interface that uses a bi-directional data bus and
serial clock. The memory carries a built-in 4-bit
Device Type Identifier code (1010) in accordance
with the I

2

C bus definition to access the memory
area and a second Device Type Identifier Code
(0110) to access the Protection Regist er. These
codes are used together with three chip enable
inputs (E2, E1, E0) so that up to eight 2 Kbit
devices may be attached to the I²C bus and
selected individually.

The memory behaves as a slave device in the I

2

protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, genera ted by the
bus master. The START condition is followed by a
Device Select Code and RW

bit (as described in

Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory

inserts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.

C

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

T

LEAD

V

IO

V

CC

V

ESD Electrostatic Discharge Voltage (Human Body model)

Note: 1. Exc ept for the rat i ng “Operating Temperatu re Range”, s tr esses above those listed in the Table “Absolute Maximum Ratings” may

2/19

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating se ct i ons of this specification is not im plied. Expo sure to Absolute Maximum Rating condi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (100 pF, 1500 Ω)

Ambient Operating Temperature -40 to 85 °C
Storage Temperature -65 to 150 °C

Lead Temperature during Soldering

Input or Output range -0.6 to 6.5 V
Supply Voltage -0.3 to 6.5 V

1

PSDIP8: 10 sec
SO8: 40 sec
TSSOP8: 40 sec

2

260
215
215

4000 V

°C

M34C02

When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.

Power On Reset: V

Lock-Out Write Protect

CC

In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the V

voltage has reached

CC

the POR threshold value, and all operations are

disabled – the device will not respond to any
command. In the same way, when V

drops from

CC

the operating voltage, below the POR threshold
value, all operations are disabled an d the device
will not respond to any command. A stable and
valid V

must be applied before applying any

CC

logic signal.

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be c onnected
from the SCL line to V

. (Figure 3 indicates how

CC

the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull­up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open

drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected f rom the SDA
bus to V

. (Figure 3 indicates how t he value of

CC

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to

or VSS to establish the device select code.

V

CC

Write Control (WC

A hardware Write Control (WC

)

, pin 7) is provided
for protecting the contents of the whole memory
from erroneous erase/write cycles. The Write
Control signal is used to enable (WC
disable (WC

=VIH) write instructions to the entire

=VIL) or

memory area or to the Protection Register.
When WC

is tied to VSS or left unc onnected, the
write protection of the first half of the memory is
determined by the status of the Protection
Register.

DEVICE OPERATION

The memory device supports the I

2

C protocol.
This is summarized in Figure 4. Any device that
sends data on to the bus is defined to be a
transmitter, and any device that reads the data to
be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can o nly be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.

Figure 3. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

Value versus Bus Capacitance (C

L

fc = 100kHz

fc = 400kHz

100

C

(pF)

BUS

) for an I2C Bus

BUS

MASTER

V

CC

R

SDA

SCL

R

C

BUS

L

C

BUS

AI01665

3/19

L

M34C02

Figure 4. I

2

C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

AI00792

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is stable in t he
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.

Table 3. Device Select Code

1

Stop Condition

STOP is identified by a low to high transition of the
SDA line wh ile th e clock S CL is sta ble in the h igh
state. A STOP condition terminates
communication between the m emory device and
the bus master. A STOP condition at the end of a
Read command, provided th at it is followed by a
NoAck, forces the memory device into its st andby
state. A STOP condition at the end of a Write

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0
Memory Area Select Code (two arrays) 1 0 1 0 E2 E1 E0 RW
Protection Register Select Code 0 1 1 0 E2 E1 E0 RW

Note: 1. The most significant bit (b7) is sent first.

4/19

M34C02

Table 4. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

0X

Random Address Read

1 X reSTART, Device Select, RW

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

WC

1

Bytes Initial Sequence

= ‘1’

1

START, Device Select, RW

= ‘0’, Address

= ‘1’

Byte Write 0
Page Write 0

Note: 1. X = V

IH

or V

.

IL

V

IL

V

IL

command triggers the internal EEPROM write
cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9
clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high

only

transition, and the data must change

when

the SCL line is low .

Memory Addressing

To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type

Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0 ) .

To address the memory array, the 4-bit Device
Type Identifier is 1010b. To address the Protection
Register, it is 0110b.

If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I

2

C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When t he Device
Select Code is received on the SDA bus, the
memory only responds if t he Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.

th

The 8

bit is the read or write bit (RW). This bit is

set to ‘1’ for read and ‘0’ for write operations. If a

1 START, Device Select, RW = ‘0’

≤ 16 START, Device Select, RW = ‘0’

match occurs on the Device Select Code, the
corresponding memory gives an acknowledgment
on the SDA bus during the 9

th

bit time. If the
memory does not match the Device Select code, it
will deselect itself from the bus, and go into stand­by mode.

th

Write Operations

Following a START con dition the ma ster sends a
Device Select Code with the RW

bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC
input pin is taken high.

Byte Write

In the Byte Write mode, after the Device Select
Code and the address byte, the master sends one
data byte. If the addressed location is in a write
protected area, the memory replies with a NoA ck,
and the location is not modified. If, instead, the
addressed location is not in a write protected area,
the memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.

Page Write

The Page Write mode allows u p to 16 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
(b7-b4) are the same. I f m ore byt es are sent than
will fit up to t he en d of t he row, a condition known
as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).

The master sends from one up to 16 bytes of data,
each of which is acknow ledged by the memory if
the WC

pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified. After each byte is transferred, the
internal byte address counter (the 4 least

5/19

M34C02

Figure 5. How to Set the Write Protection

FFh

80h
7Fh

00h

Standard

Array

Write

Protected

Array

State of the EEPROM memory
area after write access
to the Protect Register

Memory

Area

Standard

Array

Standard

Array

Default EEPROM memory area
state before write access
to the Protect Register

Figure 6. Write Mode Sequences in the Non Write-Protected Area

ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

R/W

START

ACK

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

ACK ACK

FFh

80h
7Fh

00h

AI01936C

STOP

START

ACK ACK

DATA IN N

significant bits only) is incremented. The transfer is
terminated by the master generating a STOP
condition.

When the master generates a STOP condition

immediately after the Ack bi t (in t he “10

th

bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not
trigger the internal write cycle.

During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.

R/W

STOP

AI01941

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (t

) is shown in Table 9,

w

but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the
master.

6/19