ST M29W400BT, M29W400BB User Manual
查询M29W400BB供应商
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory
■ SINGLE 2.7 to 3.6V SUPPLYVOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 5 5ns
■ PROGRAMMING TIME
– 10 µs per Byte/ Word typical
■ 11 MEMORY BLOCKS
– 1 Boot Block (Top or Bot tom Location)
– 2Parameterand8MainBlocks
■ PROGRAM/ERASE CONTROLLER
– Em bedded Byte/Word Program algorithm
– Em bedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
■ ERASE SUSPEND and RESUMEMODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Fas ter Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ 20 YEARS DATA RETENTION
– Defec tivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
– Manuf acturer Code: 0020h
– Top Device Co de M29W400BT: 00EEh
– Bottom Device Code M29W400BB: 00EFh
M29W400BT
M29W400BB
TSOP48 (N)
12 x 20mm
44
1
SO44 (M)
Figure 1. Logic Diagram
V
CC
18
A0-A17
W
E
G
RP
M29W400BT
M29W400BB
FBGA
TFBGA48 (ZA)
6 x 8 ball array
15
DQ0-DQ14
DQ15A–1
BYTE
RB
V
SS
AI02934
1/25June 2001
M29W400BT, M29W400BB
Figure 2. TSOP Connections
A15
A14
A13
A12
A11
A10 DQ14
A9
A8
NC
NC
RP
NC
NC
RB
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
W
12
M29W400BT
M29W400BB
13
24 25
48
37
36
AI02935
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SS
E
A0
Figure 3. SO Connections
NC RP
A17 A8
A7
A6
A5
A4
A3
A2
A1
A0
V
SS
DQ0
DQ8
DQ9
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
M29W400BT
M29W400BB
12
E
13
14
G
15
16
17DQ1
18
19
20
21
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322
AI02936
WRB
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5DQ2
DQ12
DQ4
V
CC
Table 1. Signal Names
A0-A17 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E
G
W
RP
RB
BYTE
V
CC
V
SS
NC Not Connected Internally
2/25
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
Ground
SUMMARY DESCRIPTION
The M29W400B is a 4 Mbit (512Kb x8 or 256Kb
x16) non-volatile memory t hat can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. O n power-up the memory d efau lts to its
Read mode where it c an be read in the same way
as a ROM or EPROM. The M29W400B is fully
backward compatible with the M29W400.
The memory is divided into block s that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase com mands are w ritten to the Com mand Interface of the memory. An
on-chip Program/Erase Controller simp lifies the
process of programm ing or erasing the memory by
taking care of all of the spec ial operations that are
required to update the memory contents. The end
of a program or erase operation c an be detected
and any error c onditions identified. The command
set required to contro l the memory is consistent
with J E DE C standards.
Figure 4. TFBGA Connections (Top view through package)
M29W400BT, M29W400BB
4321
A
B
C
D
E
F
G
A3
A7
A5
DQ0
RB
NCA17A4
NC
DQ10DQ8E
W A13
RP A8
DQ12
V
CC
A9
DQ14
DQ13DQ11DQ9G
65
A12
A14A10NCNCA6A2
A15A11NCA1
A16DQ7DQ5DQ2A0
BYTE
DQ15
A–1
H
SS
DQ3
The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small init ialization code t o start the microprocessor, the t wo 8 Kbyte Parame ter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
DQ4
DQ6DQ1V
V
SS
AI03988
Chip Enab le, Output Enable and Write Enable signals control the bus operation of the memory.
They allo w simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm),
TFBGA48 (0.8mm pitch) and SO44 packages and
it is supplied with all the bits erased (set to ’1’).
3/25
M29W400BT, M29W400BB
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
V
ID
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to A bsolute Maximum Rating conditionsforextended periodsmayaffect device reliability.Refer alsotothe STMicroelectronics SUREProgram and otherrelevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Table 3. Top Boot Block Addresses
M29W400BT
Size
#
(Kbytes)
10 16 7C000h-7FFFFh 3E000h-3FFFFh
9 8 7A000h-7BFFFh 3D000h-3DFFFh
8 8 78000h-79FFFh 3C000h-3CFFFh
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage –0.6 to 4 V
Supply Voltage –0.6 to 4 V
Identification Voltage –0.6 to 13.5 V
Table 4. Bottom Boo t B l ock Addresses
M29W400BB
Address Range
(x8)
Address Range
(x16)
#
(Kbytes)
Size
Address Range
(x8)
Address Range
(x16)
10 64 70000h-7FFFFh 38000h-3FFFFh
9 64 60000h-6FFFFh 30000h-37FFFh
8 64 50000h-5FFFFh 28000h-2FFFFh
7 32 70000h-77FFFh 38000h-3BFFFh
6 64 60000h-6FFFFh 30000h-37FFFh
5 64 50000h-5FFFFh 28000h-2FFFFh
4 64 40000h-4FFFFh 20000h-27FFFh
3 64 30000h-3FFFFh 18000h-1FFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh
7 64 40000h-4FFFFh 20000h-27FFFh
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 00000h-03FFFh 00000h-01FFFh
4/25
M29W400BT, M29W400BB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and T able 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus W r ite operations they control the commands sent to the
Command Interface of the internal state machine.
Data I np uts/Ou tputs (DQ0-DQ7). TheDataInputs/Outputs output the data stored at the selected
address during a Bus Read op eration. During Bus
Write op erations they represent the commands
sent to the Command Interface of the internal state
machine.
Data I np uts/Ou tputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are hi gh im pedance. During Bus
Write operations the Command Register does not
use thes e bits. When reading the Status R egister
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When B Y TE
is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE
is Low, VIL, this pin behaves as an address
pin; DQ15A–1 L ow will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the M SB. Throughout the text c onsider references
to the Data Input/Output to include this pin when
is High and references to the Address In-
BYTE
puts to include this pin when BYTE
is Low except
when stated explicitly otherwise.
Chip Enable (E
). The Chip Enable, E, activates
thememory,allowingBusReadandBusWriteoperations to be performed. When Chip Enable is
High, V
Output Enable (G
, all other pins are ignored.
IH
). T he Output Enable, G, con-
trols the Bus Read operation of the memory.
WriteEnable(W
). The Write Enable, W, controls
the Bus W rite operation of th e memory’s Command Interface.
Reset/Block Temporary Unprotect (RP
). The Re-
set/Block Temporary Unprotect pin can be us ed to
apply a Hardware Res et to the memory or to temporarily unprotect all Blocks that h ave been protected.
A Hardware Reset is ac hieved by holding Reset/
Block Temporary Unprotect Low, V
. After Reset/Block Temporary Unprotect
t
PLPX
goes High, V
, the memory will be read y for Bus
IH
Read and Bus Write operations after t
, for at least
IL
PHEL
or
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 17 and Figure 12, Reset/
Temporary Unprotect A C Characteristics for more
details.
Holding RP
at VIDwill temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will b e possible.
The transition from V
t
PHPHH
.
Ready/Busy Output (RB
to VIDmust be slower than
IH
). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-imp edance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and B us Write
operations cannot begin until Ready /Bus y becomes hi gh-impedance. See Table 17 and Figure
12, R es et /T emporary Unprotect AC Characteristics.
During Program or Erase operations Re ady /Busy
is Low, V
. Ready/Busy will remain Low during
OL
Read/Reset commands or Hardware Resets until
the memory is ready to ente r Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The Byte/
Word Organization Selec t pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low,
, the memory is in 8-bit mode, when it is High,
V
IL
V
, the mem ory is in 16-bit mode.
IH
Supply Voltage. The VCCSupply Voltage
V
CC
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is program min g or erasing during
this time then the operation aborts an d the memory contents being altered will be invalid.
A 0.1µF capacitor should be c onnec ted between
the V
Supply Voltage pin and the VSSGround
CC
pin to decouple the current s urges from the power
supply. The PCB track widths must be sufficient to
carry the c urrent s required during program and
erase operations,I
Ground. The VSSGround is the reference for
V
SS
CC3
.
all voltage measurements.
5/25
M29W400BT, M29W400BB
BUS OPERATIONS
Thereare five standard bus operations that control
the device. These are Bus Read, Bus Write, OutPut Disable, Standby and Automat ic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ig nored by the memory and do
not affect bus operations.
Bus Read. B us Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read ope ra tion involves setting the desired address on the Address
Inputs, applying a Low sig nal, V
, to Chip Enable
IL
and Output Enable and keeping Write Enable
High, V
. The Data Inputs/Outputs will output the
IH
value, see Figure 9, Read Mode AC Waveforms,
and Table 14, Read AC Charac teristics, for details
of when the output becom es valid.
Bus Write. Bus Write op erations write to the
Command Interface. A valid Bus Write o peration
begins by setting the desired address on the Address Inputs. The Addres s Inputs are latched by
the Command Interface on the falling edge of Chip
Table 5. Bus Operations, BYTE
Operation E G W
=V
IL
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
orWrite Enable, whichever occurs first.Output Enable must rem ain High, V
, during the whole Bus
IH
Write operation. See Figures 10 and 11, Write AC
Waveforms, and Tab les 15 and 16, Write AC
Characteristics, for details of the timi ng requirements.
Output Disable. The Dat a Inputs/Outputs are in
the high im pedance state when Output E nable is
High, V
.
IH
Standby. When Chip Enable is High, V
memory enters St andby mode and th e Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to t he
Standby Supply Current, I
be held within V
±0.2V. For the Standby current
CC
, Chip Enable should
CC2
level see Table 13 , DC Charac teristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, for P r ogram or Erase operations un-
CC3
til the operation completes.
Address Inputs
DQ15A–1, A0-A17
Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
,the
IH
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VILor VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
X X X Hi-Z Hi-Z
V
IL
V
IL
Table 6. Bus Operations, BYTE =V
Operation E
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VILor VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
G W
V
IL
V
IH
V
IH
X X X Hi-Z
V
IL
V
IL
V
Cell Address Hi-Z Data Output
IH
V
Command Address Hi-Z Data Input
IL
V
X Hi-Z Hi-Z
IH
A0 = VIL,A1=VIL,A9=VID,
V
IH
Others V
A0=VIH,A1=VIL,A9=VID,
V
IH
Others VILor V
IH
or V
IL
IH
IH
Address Inputs
A0-A17
V
Cell Address Data Output
IH
V
Command Address Data Input
IL
V
X Hi-Z
IH
A0 = VIL,A1=VIL,A9=VID,
V
IH
Others V
A0=VIH,A1=VIL,A9=VID,
V
IH
Others V
or V
IL
IH
or V
IL
IH
Hi-Z 20h
Hi-Z
EEh (M29W400BT)
EFh (M29W400BB)
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
0020h
00EEh (M29W400BT)
00EFh (M29W400BB)
6/25
M29W400BT, M29W400BB
Automatic Standby. If CMOS levels (VCC±0.2V)
are used to drive the bus and the bus is inactive for
150ns or more t he memory enters Automatic
Standby where the internal Supply Current is reduced to t he Standby Supply Current, I
CC2
.The
Data Inputs/Outputs will still o utpu t data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. Thes e bus operations are intended for use by programming equipment and are not usually used in applications.
They require V
to be applie d to some pin s.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 5 and 6, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against accidental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protec ting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. For further inform ation refer to Appl icati on
Note A N 1122, Applying Protection and Unprotection to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations t o the memory are interpreted by t he Comman d Interface. Com mands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations wil l result in the memory returning t o Re ad mode. The long command sequences
are imposed to maximize dat a security.
The address used for the co mm ands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on
the configuration that is being used, for a summary of the comm ands .
Read/Reset Command. The Rea d/Reset command returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset co mm and is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take up to
10µs to abort. During the abort period no valid data
can be read from the memory. Issuing a Read/Reset c ommand during a Block Erase operation wi ll
leave invalid data in the m emory.
Auto Select Command. The Aut o Selec t command is used to read the Manufacturer C ode, the
Device Code and t he Block Protection Stat us.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V
and A1 = VIL. Th e other address bits
IL
or VIH. The Manufacturer
IL
Code for STMicroelectronics is 0020h.
The D evice Code can be read using a Bus Read
operation with A0 = V
address bits may be set to either V
and A1 = VIL. The other
IH
or VIH.The
IL
Device Code for the M29W400BT is 00EEh and
for the M29W400BB is 00EFh.
The Block Protection Status of each block can be
read using a Bus Read op eration with A0 = V
A1 = V
, and A12-A17 specifying the address of
IH
IL
the bl oc k. The other address bits may be set to either V
or VIH. If the addressed block is protected
IL
then 01h is output on Dat a Inputs/Outputs D Q0DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations, the final write operation latches t he address and data in the internal
state machine and starts t he Program/Erase Controller.
If the address fa lls in a protected bloc k then the
Program command i s ignored, the d ata remains
unchanged. The Status R egister is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or paus e the operation. Typical
program times are given in Table 9. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue t o output the Status Register. A Read/Reset command must be issued to reset the error condition and return t o Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1. One of the Er as e Commands must be used to s et all the bit s in a block or
in the whole mem ory from ’ 0’ to ’1’.
,
7/25
M29W400BT, M29W400BB
Table 7. Commands, 16-bit mode, BYTE =V
IH
Bus Write Operations
Command
Read/Reset
1X F0
3 555 AA 2AA 55 X F0
1st 2nd 3rd 4th 5th 6th
Length
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program
2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Table 8. Commands, 8-bit mode, BYTE =V
IL
Bus Write Operations
Command
Read/Reset
1X F0
3 AAA AA 555 55 X F0
1st 2nd 3rd 4th 5th 6th
Length
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program
2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program orUnlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
is VILor DQ15 when BYTE is VIH.
8/25
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