ST M29W400BT, M29W400BB User Manual

M29W400BB

M29W400BT

M29W400BB

4 Mbit (512Kb x8 or 256Kb x16, Boot Block) Low Voltage Single Supply Flash Memory

■SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS

■ACCESS TIME: 55ns

■PROGRAMMING TIME

–10µs per Byte/Word typical

■11 MEMORY BLOCKS

–1 Boot Block (Top or Bottom Location)

–2 Parameter and 8 Main Blocks

■PROGRAM/ERASE CONTROLLER

–Embedded Byte/Word Program algorithm

–Embedded Multi-Block/Chip Erase algorithm

–Status Register Polling and Toggle Bits

–Ready/Busy Output Pin

■ERASE SUSPEND and RESUME MODES

–Read and Program another Block during Erase Suspend

■UNLOCK BYPASS PROGRAM COMMAND

–Faster Production/Batch Programming

■TEMPORARY BLOCK UNPROTECTION MODE

■LOW POWER CONSUMPTION

–Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■20 YEARS DATA RETENTION

–Defectivity below 1 ppm/year

■ELECTRONIC SIGNATURE

–Manufacturer Code: 0020h

–Top Device Code M29W400BT: 00EEh

–Bottom Device Code M29W400BB: 00EFh

	FBGA
TSOP48 (N)	TFBGA48 (ZA)
12 x 20mm	6 x 8 ball array

44

1

SO44 (M)

Figure 1. Logic Diagram

		VCC
	18		15
	A0-A17		DQ0-DQ14
	W		DQ15A–1
	E	M29W400BT	BYTE
		M29W400BB
	G		RB
	RP

VSS

AI02934

June 2001

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M29W400BT, M29W400BB

Figure 2. TSOP Connections

A15

1

48

A16

A14

BYTE

A13

VSS

A12

DQ15A–1

A11

DQ7

A10

DQ14

A9

DQ6

A8

DQ13

NC

DQ5

NC

DQ12

DQ4

W

12

37

VCC

RP

M29W400BT

NC

13

M29W400BB

36

DQ11

NC

DQ3

DQ10

RB

NC

DQ2

A17

DQ9

A7

DQ1

A6

DQ8

A5

DQ0

A4

G

A3

VSS

A2

E

A1

24

25

A0

AI02935

Table 1. Signal Names

	A0-A17					Address Inputs
	DQ0-DQ7					Data Inputs/Outputs
	DQ8-DQ14					Data Inputs/Outputs
	DQ15A–1					Data Input/Output or Address Input
						Chip Enable
	E
						Output Enable
	G
						Write Enable
	W
						Reset/Block Temporary Unprotect
	RP
						Ready/Busy Output
	RB
						Byte/Word Organization Select
	BYTE
	VCC					Supply Voltage
	VSS					Ground
	NC					Not Connected Internally
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Figure 3. SO Connections

NC			1	44		RP
				43
RB			2			W
A17			3	42		A8
A7			4	41		A9
A6			5	40		A10
A5			6	39		A11
A4			7	38		A12
A3			8	37		A13
A2			9	36		A14
A1			10	35		A15
A0			11	M29W400BT 34		A16
				M29W400BB 33
	E		12			BYTE
VSS			13	32		VSS
G			14	31		DQ15A–1
DQ0			15	30		DQ7
DQ8			16	29		DQ14
DQ1			17	28		DQ6
DQ9			18	27		DQ13
DQ2			19	26		DQ5
DQ10			20	25		DQ12
DQ3			21	24		DQ4
DQ11			22	23		VCC
				AI02936

SUMMARY DESCRIPTION

The M29W400B is a 4 Mbit (512Kb x8 or 256Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W400B is fully backward compatible with the M29W400.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

M29W400BT, M29W400BB

Figure 4. TFBGA Connections (Top view through package)

		1	2	3	4	5	6
	A	A3	A7	RB	W	A9	A13
	B	A4	A17	NC	RP	A8	A12
	C	A2	A6	NC	NC	A10	A14
	D	A1	A5	NC	NC	A11	A15
	E	A0	DQ0	DQ2	DQ5	DQ7	A16
	F	E	DQ8	DQ10	DQ12	DQ14	BYTE
	G	G	DQ9	DQ11	VCC	DQ13	DQ15
							A–1
	H	VSS	DQ1	DQ3	DQ4	DQ6	VSS

AI03988

The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm), TFBGA48 (0.8mm pitch) and SO44 packages and it is supplied with all the bits erased (set to ’1’).

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M29W400BT, M29W400BB

Table 2. Absolute Maximum Ratings (1)

	Symbol	Parameter	Value	Unit
	TA	Ambient Operating Temperature (Temperature Range Option 1)	0 to 70	°C
		Ambient Operating Temperature (Temperature Range Option 6)	–40 to 85	°C
	TBIAS	Temperature Under Bias	–50 to 125	°C
	TSTG	Storage Temperature	–65 to 150	°C
	VIO (2)	Input or Output Voltage	–0.6 to 4	V
	VCC	Supply Voltage	–0.6 to 4	V
	VID	Identification Voltage	–0.6 to 13.5	V

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Table 3. Top Boot Block Addresses

M29W400BT

	#	Size	Address Range	Address Range
		(Kbytes)	(x8)	(x16)
	10	16	7C000h-7FFFFh	3E000h-3FFFFh
	9	8	7A000h-7BFFFh	3D000h-3DFFFh
	8	8	78000h-79FFFh	3C000h-3CFFFh
	7	32	70000h-77FFFh	38000h-3BFFFh
	6	64	60000h-6FFFFh	30000h-37FFFh
	5	64	50000h-5FFFFh	28000h-2FFFFh
	4	64	40000h-4FFFFh	20000h-27FFFh
	3	64	30000h-3FFFFh	18000h-1FFFFh
	2	64	20000h-2FFFFh	10000h-17FFFh
	1	64	10000h-1FFFFh	08000h-0FFFFh
	0	64	00000h-0FFFFh	00000h-07FFFh

Table 4. Bottom Boot Block Addresses

M29W400BB

	#	Size	Address Range	Address Range
		(Kbytes)	(x8)	(x16)
	10	64	70000h-7FFFFh	38000h-3FFFFh
	9	64	60000h-6FFFFh	30000h-37FFFh
	8	64	50000h-5FFFFh	28000h-2FFFFh
	7	64	40000h-4FFFFh	20000h-27FFFh
	6	64	30000h-3FFFFh	18000h-1FFFFh
	5	64	20000h-2FFFFh	10000h-17FFFh
	4	64	10000h-1FFFFh	08000h-0FFFFh
	3	32	08000h-0FFFFh	04000h-07FFFh
	2	8	06000h-07FFFh	03000h-03FFFh
	1	8	04000h-05FFFh	02000h-02FFFh
	0	16	00000h-03FFFh	00000h-01FFFh

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M29W400BT, M29W400BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A17). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 17 and Figure 12, Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure 12, Reset/Temporary Unprotect AC Characteristics.

During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The Byte/ Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode.

VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3.

VSS Ground. The VSS Ground is the reference for all voltage measurements.

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M29W400BT, M29W400BB

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, OutPut Disable, Standby and Automatic Standby. See Tables 5 and 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9, Read Mode AC Waveforms, and Table 14, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip

Table 5. Bus Operations, BYTE = VIL

Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 10 and 11, Write AC Waveforms, and Tables 15 and 16, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 13, DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.

Address Inputs

Data Inputs/Outputs

Operation

E

G

W

DQ15A–1, A0-A17

DQ14-DQ8

DQ7-DQ0

Bus Read

VIL

VIL

VIH

Cell Address

Hi-Z

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Hi-Z

Data Input

Output Disable

X

VIH

VIH

X

Hi-Z

Hi-Z

Standby

VIH

X

X

X

Hi-Z

Hi-Z

Read Manufacturer

VIL

VIL

VIH

A0 = VIL, A1 = VIL, A9 = VID,

Hi-Z

20h

Code

Others VIL or VIH

Read Device Code

VIL

VIL

VIH

A0 = VIH, A1 = VIL, A9 = VID,

Hi-Z

EEh (M29W400BT)

Others VIL or VIH

EFh (M29W400BB)

Note: X = VIL or VIH.

Table 6. Bus Operations, BYTE = VIH

Address Inputs

Data Inputs/Outputs

Operation

E

G

W

A0-A17

DQ15A–1, DQ14-DQ0

Bus Read

VIL

VIL

VIH

Cell Address

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Data Input

Output Disable

X

VIH

VIH

X

Hi-Z

Standby

VIH

X

X

X

Hi-Z

Read Manufacturer

VIL

VIL

VIH

A0 = VIL, A1 = VIL, A9 = VID,

0020h

Code

Others VIL or VIH

Read Device Code

VIL

VIL

VIH

A0 = VIH, A1 = VIL, A9 = VID,

00EEh (M29W400BT)

Others VIL or VIH

00EFh (M29W400BB)

Note: X = VIL or VIH.

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M29W400BT, M29W400BB

Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 5 and 6, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-bit or 8- bit mode. See either Table 7, or 8, depending on the configuration that is being used, for a summary of the commands.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29W400BT is 00EEh and for the M29W400BB is 00EFh.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A17 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 9. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

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M29W400BT, M29W400BB

Table 7. Commands, 16-bit mode, BYTE = VIH

Length

Bus Write Operations

Command

1st

2nd

3rd

4th

5th

6th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

1

X

F0

3

555

AA

2AA

55

X

F0

Auto Select

3

555

AA

2AA

55

555

90

Program

4

555

AA

2AA

55

555

A0

PA

PD

Unlock Bypass

3

555

AA

2AA

55

555

20

Unlock Bypass

2

X

A0

PA

PD

Program

Unlock Bypass Reset

2

X

90

X

00

Chip Erase

6

555

AA

2AA

55

555

80

555

AA

2AA

55

555

10

Block Erase

6+

555

AA

2AA

55

555

80

555

AA

2AA

55

BA

30

Erase Suspend

1

X

B0

Erase Resume

1

X

30

Table 8. Commands, 8-bit mode, BYTE = VIL

Length

Bus Write Operations

Command

1st

2nd

3rd

4th

5th

6th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

1

X

F0

3

AAA

AA

555

55

X

F0

Auto Select

3

AAA

AA

555

55

AAA

90

Program

4

AAA

AA

555

55

AAA

A0

PA

PD

Unlock Bypass

3

AAA

AA

555

55

AAA

20

Unlock Bypass

2

X

A0

PA

PD

Program

Unlock Bypass Reset

2

X

90

X

00

Chip Erase

6

AAA

AA

555

55

AAA

80

AAA

AA

555

55

AAA

10

Block Erase

6+

AAA

AA

555

55

AAA

80

AAA

AA

555

55

BA

30

Erase Suspend

1

X

B0

Erase Resume

1

X

30

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode.

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