ST M29W320DT, M29W320DB User Manual

M29W320

M29W320DT

M29W320DB

32 Mbit (4Mb x8 or 2Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■SUPPLY VOLTAGE

–VCC = 2.7V to 3.6V for Program, Erase and Read

–VPP =12V for Fast Program (optional)

■ACCESS TIME: 70, 90ns

■PROGRAMMING TIME

–10µs per Byte/Word typical

■67 MEMORY BLOCKS

–1 Boot Block (Top or Bottom Location)

–2 Parameter and 64 Main Blocks

■PROGRAM/ERASE CONTROLLER

–Embedded Byte/Word Program algorithms

■ERASE SUSPEND and RESUME MODES

–Read and Program another Block during Erase Suspend

■UNLOCK BYPASS PROGRAM COMMAND

–Faster Production/Batch Programming

■VPP/WP PIN for FAST PROGRAM and WRITE PROTECT

■TEMPORARY BLOCK UNPROTECTION MODE

■COMMON FLASH INTERFACE

–64 bit Security Code

■LOW POWER CONSUMPTION

–Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■ELECTRONIC SIGNATURE

–Manufacturer Code: 0020h

–Top Device Code M29W320DT: 22CAh

–Bottom Device Code M29W320DB: 22CBh

Figure 1. Packages

TSOP48 (N) 12 x 20mm

FBGA

TFBGA63 (ZA)

TFBGA48 (ZE)

August 2005

1/46

M29W320DT, M29W320DB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. TFBGA63 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2/46

M29W320DT, M29W320DB

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10.Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Bottom View Package Outline . . 28 Table 15. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 28 Figure 19.TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline. . . . . . . . . . . 29 Table 16. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . . 29

3/46

M29W320DT, M29W320DB

Figure 20.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 30 Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 30

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19. Top Boot Block Addresses, M29W320DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. Bottom Boot Block Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 22. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 27. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 21.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 22.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 23.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 24.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4/46

M29W320DT, M29W320DB

SUMMARY DESCRIPTION

The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are asymmetrically arranged, see Figure 6. and Figure 7., Table 19. and Table 20.The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32 Kbyte is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm) TFBGA63 (7x11mm, 0.8mm pitch) and TFBGA48 (6x8mm, 0.8mm pitch) packages. The memory is supplied with all the bits erased (set to 1).

Figure 2. Logic Diagram

		VCC VPP/WP
	21	15
	A0-A20	DQ0-DQ14
	W	DQ15A–1
	E	M29W320DT
		M29W320DB
	G	RB
	RP
	BYTE

VSS

AI90189B

Table 1. Signal Names

	A0-A20								Address Inputs
	DQ0-DQ7								Data Inputs/Outputs
	DQ8-DQ14								Data Inputs/Outputs
	DQ15A–1								Data Input/Output or Address Input
									Chip Enable
	E
									Output Enable
	G
									Write Enable
	W
									Reset/Block Temporary Unprotect
	RP
									Ready/Busy Output
	RB
									Byte/Word Organization Select
	BYTE
	VCC								Supply Voltage
	VPP
						/WP			VPP/Write Protect
	VSS								Ground
	NC								Not Connected Internally

5/46

M29W320DT, M29W320DB

Figure 3. TSOP Connections

A16

A15

1

48

A14

BYTE

A13

VSS

A12

DQ15A–1

A11

DQ7

A10

DQ14

A9

DQ6

A8

DQ13

A19

DQ5

A20

DQ12

DQ4

W

12

37

VCC

RP

M29W320DT

NC

13

M29W320DB

36

DQ11

VPP

DQ3

/WP

DQ10

RB

A18

DQ2

A17

DQ9

A7

DQ1

A6

DQ8

A5

DQ0

A4

G

A3

VSS

A2

E

A1

24

25

A0

AI90190

6/46

M29W320DT, M29W320DB

Figure 4. TFBGA63 Connections (Top view through package)

	1	2	3	4	5	6	7	8
A	NC(1)	NC(1)					NC(1)	NC(1)
B	NC(1)						NC(1)	NC(1)
C		A3	A7	RB	W	A9	A13
D		A4	A17	VPP/WP	RP	A8	A12
E		A2	A6	A18	NC	A10	A14
F		A1	A5	A20	A19	A11	A15
G		A0	DQ0	DQ2	DQ5	DQ7	A16
H		E	DQ8	DQ10	DQ12	DQ14	BYTE
J		G	DQ9	DQ11	VCC	DQ13	DQ15
							A–1
K		VSS	DQ1	DQ3	DQ4	DQ6	VSS
L	NC(1)	NC(1)					NC(1)	NC(1)
M	NC(1)	NC(1)					NC(1)	NC(1)

AI05525B

Note: 1. Balls are shorted together via the substrate but not connected to the die.

7/46

M29W320DT, M29W320DB

Figure 5. TFBGA48 Connections (Top view through package)

	1	2	3	4	5	6
A	A3	A7	RB	W	A9	A13
B	A4	A17	VPP/WP	RP	A8	A12
C	A2	A6	A18	NC	A10	A14
D	A1	A5	A20	A19	A11	A15
E	A0	DQ0	DQ2	DQ5	DQ7	A16
F	E	DQ8	DQ10	DQ12	DQ14	BYTE
G	G	DQ9	DQ11	VCC	DQ13	DQ15
						A–1
H	VSS	DQ1	DQ3	DQ4	DQ6	VSS

AI08084

8/46

					M29W320DT, M29W320DB
Figure 6. Block Addresses (x8)
	M29W320DT				M29W320DB
Top Boot Block Addresses (x8)				Bottom Boot Block Addresses (x8)
3FFFFFh	16 KByte			3FFFFFh	64 KByte
3FC000h				3F0000h
3FBFFFh	8 KByte			3EFFFFh	64 KByte
3FA000h				3E0000h
3F9FFFh	8 KByte					Total of 63
						64 KByte Blocks
3F8000h
3F7FFFh	32 KByte
3F0000h
3EFFFFh	64 KByte			01FFFFh
					64 KByte
3E0000h
				010000h
				00FFFFh	32 KByte
				008000h
			Total of 63	007FFFh	8 KByte
			64 KByte Blocks
				006000h
01FFFFh
	64 KByte			005FFFh	8 KByte
010000h				004000h
00FFFFh	64 KByte			003FFFh	16 KByte
000000h				000000h		AI90192

Note: Also see APPENDIX A., Table 19. and Table 20. for a full listing of the Block Addresses.

9/46

M29W320DT, M29W320DB

Figure 7. Block Addresses (x16)

	M29W320DT				M29W320DB
Top Boot Block Addresses (x16)				Bottom Boot Block Addresses (x16)
1FFFFFh	8 KWord			1FFFFFh	32 KWord
1FE000h				1F8000h
1FDFFFh	4 KWord			1F7FFFh	32 KWord
1FD000h				1F0000h
1FCFFFh	4 KWord					Total of 63
						32 KWord Blocks
1FC000h
1FBFFFh	16 KWord
1F8000h
1F7FFFh	32 KWord			00FFFFh
					32 KWord
1F0000h
				008000h
				007FFFh	16 KWord
				004000h
			Total of 63	003FFFh	4 KWord
			32 KWord Blocks
				003000h
00FFFFh
	32 KWord			002FFFh	4 KWord
008000h				002000h
007FFFh	32 KWord			001FFFh	8 KWord
000000h				000000h		AI90193

Note: Also see Appendix APPENDIX A., Table 19. and Table 20. for a full listing of the Block Addresses.

10/46

M29W320DT, M29W320DB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output or Address Input (DQ15A–1).

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

VPP/Write Protect (VPP/WP). The VPP/Write Protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Unlock Bypass Program operations. The Write Protect function provides a hardware method of protecting the 16 Kbyte Boot Block. The VPP/Write Protect pin must not be left floating or unconnected.

When VPP/Write Protect is Low, VIL, the memory protects the 16 Kbyte Boot Block; Program and Erase operations in this block are ignored while VPP/Write Protect is Low.

When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the 16 Kbyte boot block. Program and Erase operations can now modify the data in the 16 Kbyte Boot Block unless the block is protected using Block Protection.

When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from

VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 17..

Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state.

A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP.

Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected.

Note that if VPP/WP is at VIL, then the 16 KByte outermost boot block will remain protect even if RP

is at VID.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 14. and Figure 16., Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-im- pedance during Read mode, Auto Select mode and Erase Suspend mode.

11/46

M29W320DT, M29W320DB

Note that if VPP/WP is at VIL, then the 16 KByte outermost boot block will remain protect even if RP

is at VID.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 14. and Figure Figure 16., Reset/Temporary Unprotect AC Characteristics.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode.

12/46

VCC Supply Voltage (2.7V to 3.6V). VCC provides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, ICC3.

VSS Ground. VSS is the reference for all voltage measurements.

M29W320DT, M29W320DB

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Figure 8. and Table 2., Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 13., Read Mode AC Waveforms, and Table 11., Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 14. and Figure 15., Write AC Waveforms, and Table 12. and Table 13., Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data In-

Figure 8. Bus Operations, BYTE = VIL

puts/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 10., DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.

Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Figure 8. and Table 2., Bus Operations.

Block Protect and Chip Unprotect. Each block can be separately protected against accidental Program or Erase. The whole chip can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in APPENDIX C..

Address Inputs

Data Inputs/Outputs

Operation

E

G

W

DQ15A–1, A0-A20

DQ14-DQ8

DQ7-DQ0

Bus Read

VIL

VIL

VIH

Cell Address

Hi-Z

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Hi-Z

Data Input

Output Disable

X

VIH

VIH

X

Hi-Z

Hi-Z

Standby

VIH

X

X

X

Hi-Z

Hi-Z

Read Manufacturer

VIL

VIL

VIH

A0 = VIL, A1 = VIL, A9 = VID,

Hi-Z

20h

Code

Others VIL or VIH

Read Device Code

VIL

VIL

VIH

A0 = VIH, A1 = VIL,

Hi-Z

CAh (M29W320DT)

A9 = VID, Others VIL or VIH

CBh (M29W320DB)

Note: X = VIL or VIH.

13/46

M29W320DT, M29W320DB

Table 2. Bus Operations, BYTE = VIH

Address Inputs

Data Inputs/Outputs

Operation

E

G

W

A0-A20

DQ15A–1, DQ14-DQ0

Bus Read

VIL

VIL

VIH

Cell Address

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Data Input

Output Disable

X

VIH

VIH

X

Hi-Z

Standby

VIH

X

X

X

Hi-Z

Read Manufacturer

VIL

VIL

VIH

A0 = VIL, A1 = VIL, A9 = VID,

0020h

Code

Others VIL or VIH

Read Device Code

VIL

VIL

VIH

A0 = VIH, A1 = VIL, A9 = VID,

22CAh (M29W320DT)

Others VIL or VIH

22CBh (M29W320DB)

Note: X = VIL or VIH.

14/46