M29W200BT
M29W200BB
2 Mbit (256Kb x8 or 128Kb x16, Boot Block) Low Voltage Single Supply Flash Memory
■SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
■ACCESS TIME: 55ns
■PROGRAMMING TIME
–10µs per Byte/Word typical
■7 MEMORY BLOCKS
–1 Boot Block (Top or Bottom Location)
–2 Parameter and 4 Main Blocks
■PROGRAM/ERASE CONTROLLER
–Embedded Byte/Word Program algorithm
–Embedded Multi-Block/Chip Erase algorithm
–Status Register Polling and Toggle Bits
–Ready/Busy Output Pin
■ERASE SUSPEND and RESUME MODES
–Read and Program another Block during Erase Suspend
■UNLOCK BYPASS PROGRAM COMMAND
–Faster Production/Batch Programming
■TEMPORARY BLOCK UNPROTECTION MODE
■LOW POWER CONSUMPTION
–Standby and Automatic Standby
■100,000 PROGRAM/ERASE CYCLES per BLOCK
■20 YEARS DATA RETENTION
–Defectivity below 1 ppm/year
■ELECTRONIC SIGNATURE
–Manufacturer Code: 0020h
–Top Device Code M29W200BT: 0051h
–Bottom Device Code: M29W200BB 0057h
■ECOPACK® PACKAGES AVAILABLE
44
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1 |
TSOP48 (N) |
SO44 (M) |
12 x 20mm |
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VCC |
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17 |
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15 |
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A0-A16 |
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DQ0-DQ14 |
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W |
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DQ15A–1 |
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E |
M29W200BT |
BYTE |
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M29W200BB |
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G |
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RB |
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RP |
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VSS
AI02948
September 2005 |
1/22 |
M29W200BT, M29W200BB
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A16 |
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A15 |
1 |
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A14 |
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BYTE |
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A13 |
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VSS |
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A12 |
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DQ15A–1 |
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A11 |
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DQ7 |
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A10 |
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DQ14 |
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A9 |
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DQ6 |
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A8 |
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DQ13 |
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NC |
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DQ5 |
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NC |
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DQ12 |
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DQ4 |
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VCC |
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RP |
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13 |
M29W200BB |
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DQ11 |
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DQ3 |
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DQ10 |
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RB |
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NC |
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DQ2 |
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DQ9 |
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A7 |
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DQ1 |
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A6 |
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DQ8 |
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A5 |
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DQ0 |
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A4 |
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G |
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A3 |
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VSS |
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A2 |
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E |
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A1 |
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A0 |
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AI02944 |
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A0-A16 |
Address Inputs |
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DQ0-DQ7 |
Data Inputs/Outputs |
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DQ8-DQ14 |
Data Inputs/Outputs |
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DQ15A–1 |
Data Input/Output or Address Input |
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Chip Enable |
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E |
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Output Enable |
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G |
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Write Enable |
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W |
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Reset/Block Temporary Unprotect |
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RP |
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Ready/Busy Output |
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RB |
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Byte/Word Organization Select |
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BYTE |
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VCC |
Supply Voltage |
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VSS |
Ground |
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NC |
Not Connected Internally |
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2/22 |
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44 |
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RB |
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A8 |
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A7 |
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A9 |
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A6 |
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A10 |
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A5 |
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A11 |
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A4 |
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A12 |
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A3 |
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A13 |
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A2 |
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36 |
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A14 |
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A1 |
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A15 |
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A0 |
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11 |
M29W200BT 34 |
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A16 |
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M29W200BB 33 |
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E |
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12 |
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BYTE |
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VSS |
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13 |
32 |
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VSS |
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G |
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14 |
31 |
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DQ15A–1 |
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DQ0 |
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DQ7 |
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DQ8 |
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16 |
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DQ14 |
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DQ1 |
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DQ6 |
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DQ9 |
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DQ13 |
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DQ2 |
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26 |
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DQ5 |
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DQ10 |
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DQ12 |
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DQ3 |
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24 |
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DQ4 |
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DQ11 |
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VCC |
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AI02945 |
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The M29W200B is a 2 Mbit (256Kb x8 or 128Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W200B is fully backward compatible with the M29W200.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
M29W200BT, M29W200BB
Symbol |
Parameter |
Value |
Unit |
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TA |
Ambient Operating Temperature (Temperature Range Option 1) |
0 to 70 |
°C |
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Ambient Operating Temperature (Temperature Range Option 6) |
–40 to 85 |
°C |
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TBIAS |
Temperature Under Bias |
–50 to 125 |
°C |
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TSTG |
Storage Temperature |
–65 to 150 |
°C |
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VIO (2) |
Input or Output Voltage |
–0.6 to 4 |
V |
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VCC |
Supply Voltage |
–0.6 to 4 |
V |
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VID |
Identification Voltage |
–0.6 to 13.5 |
V |
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Table 3. Top Boot Block Addresses
M29W200BT
# |
Size |
Address Range |
Address Range |
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(Kbytes) |
(x8) |
(x16) |
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6 |
16 |
3C000h-3FFFFh |
1E000h-1FFFFh |
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5 |
8 |
3A000h-3BFFFh |
1D000h-1DFFFh |
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4 |
8 |
38000h-39FFFh |
1C000h-1CFFFh |
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3 |
32 |
30000h-37FFFh |
18000h-1BFFFh |
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2 |
64 |
20000h-2FFFFh |
10000h-17FFFh |
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1 |
64 |
10000h-1FFFFh |
08000h-0FFFFh |
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0 |
64 |
00000h-0FFFFh |
00000h-07FFFh |
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The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.
Table 4. Bottom Boot Block Addresses
M29W200BB
# |
Size |
Address Range |
Address Range |
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(Kbytes) |
(x8) |
(x16) |
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6 |
64 |
30000h-3FFFFh |
18000h-1FFFFh |
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5 |
64 |
20000h-2FFFFh |
10000h-17FFFh |
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4 |
64 |
10000h-1FFFFh |
08000h-0FFFFh |
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3 |
32 |
08000h-0FFFFh |
04000h-07FFFh |
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2 |
8 |
06000h-07FFFh |
03000h-03FFFh |
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1 |
8 |
04000h-05FFFh |
02000h-02FFFh |
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0 |
16 |
00000h-03FFFh |
00000h-01FFFh |
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The memory is offered in TSOP48 (12 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, ST offers the M29W200B in ECOPACK® packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
3/22
M29W200BT, M29W200BB
See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device.
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.
A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 17 and Figure 11, Reset/ Temporary Unprotect AC Characteristics for more details.
Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than
tPHPHH.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure 11, Reset/Temporary Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.
VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3.
VSS Ground. The VSS Ground is the reference for all voltage measurements.
4/22
M29W200BT, M29W200BB
There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 5 and 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 9 and 10, Write AC Waveforms, and Tables 15 and 16, Write AC Characteristics, for details of the timing requirements.
During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.
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Address Inputs |
Data Inputs/Outputs |
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Operation |
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G |
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W |
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DQ15A–1, A0-A16 |
DQ14-DQ8 |
DQ7-DQ0 |
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Bus Read |
VIL |
VIL |
VIH |
Cell Address |
Hi-Z |
Data Output |
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Bus Write |
VIL |
VIH |
VIL |
Command Address |
Hi-Z |
Data Input |
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Output Disable |
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VIH |
VIH |
X |
Hi-Z |
Hi-Z |
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Standby |
VIH |
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X |
Hi-Z |
Hi-Z |
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Read Manufacturer |
VIL |
VIL |
VIH |
A0 = VIL, A1 = VIL, A9 = VID, |
Hi-Z |
20h |
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Code |
Others VIL or VIH |
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Read Device Code |
VIL |
VIL |
VIH |
A0 = VIH, A1 = VIL, A9 = VID, |
Hi-Z |
51h (M29W200BT) |
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Others VIL or VIH |
57h (M29W200BB) |
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Note: X = VIL or VIH.
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Address Inputs |
Data Inputs/Outputs |
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Operation |
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E |
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G |
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W |
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A0-A16 |
DQ15A–1, DQ14-DQ0 |
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Bus Read |
VIL |
VIL |
VIH |
Cell Address |
Data Output |
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Bus Write |
VIL |
VIH |
VIL |
Command Address |
Data Input |
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Output Disable |
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X |
VIH |
VIH |
X |
Hi-Z |
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Standby |
VIH |
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X |
Hi-Z |
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Read Manufacturer |
VIL |
VIL |
VIH |
A0 = VIL, A1 = VIL, A9 = VID, |
0020h |
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Code |
Others VIL or VIH |
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Read Device Code |
VIL |
VIL |
VIH |
A0 = VIH, A1 = VIL, A9 = VID, |
0051h (M29W200BT) |
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Others VIL or VIH |
0057h (M29W200BB) |
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Note: X = VIL or VIH. |
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5/22 |
M29W200BT, M29W200BB
Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.
Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8- bit mode. See either Table 7, or 8, depending on the configuration that is being used, for a summary of the commands.
If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.
6/22
From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29W200BT is 0051h and for the M29W200BB is 0057h.
The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A16 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 9. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.
After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
M29W200BT, M29W200BB
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Length |
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Bus Write Operations |
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Command |
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1st |
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2nd |
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3rd |
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4th |
5th |
6th |
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|||||||||||||
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||||
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|
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
|||
|
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Read/Reset |
1 |
X |
|
F0 |
|
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3 |
555 |
|
AA |
2AA |
|
55 |
X |
|
F0 |
|
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|||||||
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Auto Select |
3 |
555 |
|
AA |
2AA |
|
55 |
555 |
|
90 |
|
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|
Program |
4 |
555 |
|
AA |
2AA |
|
55 |
555 |
|
A0 |
PA |
PD |
|
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|
|
|
|
Unlock Bypass |
3 |
555 |
|
AA |
2AA |
|
55 |
555 |
|
20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Unlock Bypass |
2 |
X |
|
A0 |
PA |
|
PD |
|
|
|
|
|
|
|
|
|
Program |
|
|
|
|
|
|
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|||||
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|
|
|
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|
|
Unlock Bypass Reset |
2 |
X |
|
90 |
X |
|
00 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Chip Erase |
6 |
555 |
|
AA |
2AA |
|
55 |
555 |
|
80 |
555 |
AA |
2AA |
55 |
555 |
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block Erase |
6+ |
555 |
|
AA |
2AA |
|
55 |
555 |
|
80 |
555 |
AA |
2AA |
55 |
BA |
30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Erase Suspend |
1 |
X |
|
B0 |
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Erase Resume |
1 |
X |
|
30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
Length |
|
|
|
|
|
|
Bus Write Operations |
|
|
|
|
||||
|
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|
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|
|
|
|
|
|
|
|
Command |
1st |
|
2nd |
|
3rd |
|
4th |
5th |
6th |
|||||||
|
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|
|||||||||||||
|
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||||
|
|
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Read/Reset |
1 |
X |
|
F0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3 |
AAA |
|
AA |
555 |
|
55 |
X |
|
F0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Auto Select |
3 |
AAA |
|
AA |
555 |
|
55 |
AAA |
|
90 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Program |
4 |
AAA |
|
AA |
555 |
|
55 |
AAA |
|
A0 |
PA |
PD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Unlock Bypass |
3 |
AAA |
|
AA |
555 |
|
55 |
AAA |
|
20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Unlock Bypass |
2 |
X |
|
A0 |
PA |
|
PD |
|
|
|
|
|
|
|
|
|
Program |
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Unlock Bypass Reset |
2 |
X |
|
90 |
X |
|
00 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Chip Erase |
6 |
AAA |
|
AA |
555 |
|
55 |
AAA |
|
80 |
AAA |
AA |
555 |
55 |
AAA |
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block Erase |
6+ |
AAA |
|
AA |
555 |
|
55 |
AAA |
|
80 |
AAA |
AA |
555 |
55 |
BA |
30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Erase Suspend |
1 |
X |
|
B0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Erase Resume |
1 |
X |
|
30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
7/22