ST M29F200T, M29F200B User Manual

M295V200B-120M1R

M29F200T

M29F200B

2 Mbit (256Kb x8 or 128Kb x16, Boot Block) Single Supply Flash Memory

5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS

FAST ACCESS TIME: 55ns

FAST PROGRAMMING TIME

±10μs by Byte / 16μs by Word typical PROGRAM/ERASE CONTROLLER (P/E.C.)

±Program Byte-by-Byte or Word-by-Word

±Status Register bits and Ready/Busy Output

44

1

MEMORY BLOCKS

±Boot Block (Top or Bottom location)

±Parameter and Main blocks

BLOCK, MULTI-BLOCK and CHIP ERASE

MULTI-BLOCK PROTECTION/TEMPORARY

UNPROTECTION MODES

ERASE SUSPEND and RESUME MODES

±Read and Program another Block during Erase Suspend

LOW POWER CONSUMPTION

± Stand-by and Automatic Stand-by

100,000 PROGRAM/ERASE CYCLES per BLOCK

20 YEARS DATA RETENTION

±Defectivity below 1ppm/year ELECTRONIC SIGNATURE

±Manufacturer Code: 0020h

±Device Code, M29F200T: 00D3h

±Device Code, M29F200B: 00D4h

DESCRIPTION

The M29F200 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byteor Word- by-Word basis using only a single 5V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers.

The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application.

TSOP48 (N)	SO44 (M)
12 x 20 mm

Figure 1. Logic Diagram

		VCC
	17		15
	A0-A16		DQ0-DQ14
	W		DQ15A±1
	E	M29F200T	BYTE
		M29F200B
	G		RB
	RP

VSS

AI01986

July 1998

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M29F200T, M29F200B

	Figure 2A. TSOP Pin Connections					Figure 2B. TSOP Reverse Pin Connections
	A15	1		48	A16	A16	1		48	A15
	A14				BYTE	BYTE				A14
	A13				VSS	VSS				A13
	A12				DQ15A±1	DQ15A±1				A12
	A11				DQ7	DQ7				A11
	A10				DQ14	DQ14				A10
	A9				DQ6	DQ6				A9
	A8				DQ13	DQ13				A8
	NC				DQ5	DQ5				NC
	NC				DQ12	DQ12				NC
	W		M29F200T		DQ4	DQ4		M29F200T		W
	RP	12		37	VCC	VCC	12		37	RP
			M29F200B					M29F200B
	NC	13		36	DQ11	DQ11	13		36	NC
			(Normal)					(Reverse)
	NC				DQ3	DQ3				NC
	RB				DQ10	DQ10				RB
	NC				DQ2	DQ2				NC
	NC				DQ9	DQ9				NC
	A7				DQ1	DQ1				A7
	A6				DQ8	DQ8				A6
	A5				DQ0	DQ0				A5
	A4				G	G				A4
	A3				VSS	VSS				A3
	A2				E	E				A2
	A1	24		25	A0	A0	24		25	A1
				AI01987					AI01988
	Warning: NC = Not Connected.					Warning: NC = Not Connected.
	Figure 2C. SO Pin Connections					Table 1. Signal Names
						A0-A16	Address Inputs
	NC		1	44	RP	DQ0-DQ7	Data Input/Outputs, Command Inputs
	RB		2	43	W
	NC		3	42	A8	DQ8-DQ14	Data Input/Outputs
	A7		4	41	A9
	A6		5	40	A10	DQ15A±1	Data Input/Output or Address Input
	A5		6	39	A11
	A4		7	38	A12	E	Chip Enable
	A3		8	37	A13
	A2		9	36	A14	G	Output Enable
	A1		10	35	A15
	A0		11 M29F200T 34		A16	W	Write Enable
	E		12 M29F200B 33		BYTE
	VSS		13	32	VSS	RP	Reset / Block Temporary Unprotect
	G		14	31	DQ15A±1
	DQ0		15	30	DQ7	RB	Ready/Busy Output
	DQ8		16	29	DQ14
	DQ1		17	28	DQ6	BYTE	Byte/Word Organisation
	DQ9		18	27	DQ13	VCC	Supply Voltage
	DQ2		19	26	DQ5
	DQ10		20	25	DQ12	VSS	Ground
	DQ3		21	24	DQ4
	DQ11		22	23	VCC

AI01989

Warning: NC = Not Connected.

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M29F200T, M29F200B

Table 2. Absolute Maximum Ratings (1)

Symbol		Parameter	Value	Unit
TA		Ambient Operating Temperature (3)	±40 to 125	°C
TBIAS		Temperature Under Bias	±50 to 125	°C
TSTG		Storage Temperature	±65 to 150	°C
VIO (2)		Input or Output Voltages	±0.6 to 7	V
VCC		Supply Voltage	±0.6 to 7	V
V(A9, E, G, RP)	(2)	A9, E, G, RP Voltage	±0.6 to 13.5	V

Notes: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum Voltage may undershoot to ±2V during transition and for less than 20ns.

3.Depends on range.

DESCRIPTION (Cont'd)

Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Blockand Chip Erase, Erase Suspend and Resume are written to the device in cycles of commandsto a Command Interfaceusing standard microprocessor write timings.

The device is offered in TSOP48 (12 x 20mm) and SO44 packages. Both normal and reverse pinouts are available for the TSOP48 package.

Organisation

The M29F200 is organisedas 256Kx8 or 128K x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A±1 and A0-A16. The Data Input/Output signal DQ15A±1 acts as address line A±1 which selects the lower or upper Byte of the memory word for output on DQ0-DQ7, DQ8-DQ14 remain at High impedance. When BYTE is High the memory uses the address inputs A0-A16 and the Data Input/Outputs DQ0-DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs.

AReset/Block TemporaryUnprotection RPtri-level input provides a hardware reset when pulled Low, and when heldHigh (at VID) temporarily unprotects blocks previously protected allowing them to be programedand erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of

the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms.

Memory Blocks

The devices feature asymmetrically blocked architecture providing system memory integration.Both M29F200T and M29F200B devices have an array of 7 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWords and three Main Blocks of 64 KBytes or 32 KWords. The M29F200T has the Boot Block at the top of the memory address space and the M29F200B locates the Boot Block starting at the bottom. The memory maps are showed in Figure 3. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed.

Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application.

Bus Operations

The following operations can be performed using the appropriatebus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Pro- t ect io n , Unp ro t e ct io n, P ro t e cti on Verif y, Unprotection Verify and Block Temporary Unprotection. See Tables 4 and 5.

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M29F200T, M29F200B

Figure 3. Memory Map and Block Address Table (x8)

M29F200T	M29F200B
3FFFFh	3FFFFh
16K BOOT BLOCK	64K MAIN BLOCK
3C000h	30000h
3BFFFh	2FFFFh
8K PARAMETER BLOCK	64K MAIN BLOCK
3A000h	20000h
39FFFh	1FFFFh
8K PARAMETER BLOCK	64K MAIN BLOCK
38000h	10000h
37FFFh	0FFFFh
32K MAIN BLOCK	32K MAIN BLOCK
30000h	08000h
2FFFFh	07FFFh
64K MAIN BLOCK	8K PARAMETER BLOCK
20000h	06000h
1FFFFh	05FFFh
64K MAIN BLOCK	8K PARAMETER BLOCK
10000h	04000h
0FFFFh	03FFFh
64K MAIN BLOCK	16K BOOT BLOCK
00000h	00000h
	AI01990

Table 3A. M29F200T Block Address Table

Address Range (x8)	Address Range (x16)	A16	A15	A14	A13	A12
00000h-0FFFFh	00000h-07FFFh	0	0	X	X	X
10000h-1FFFFh	08000h-0FFFFh	0	1	X	X	X
20000h-2FFFFh	10000h-17FFFh	1	0	X	X	X
30000h-37FFFh	18000h-1BFFFh	1	1	0	X	X
38000h-39FFFh	1C000h-1CFFFh	1	1	1	0	0
3A000h-3BFFFh	1D000h-1DFFFh	1	1	1	0	1
3C000h-3FFFFh	1E000h-1FFFFh	1	1	1	1	X

Table 3B. M29F200B Block Address Table

Address Range (x8)	Address Range (x16)	A16	A15	A14	A13	A12
00000h-03FFFh	00000h-01FFFh	0	0	0	0	X
04000h-05FFFh	02000h-02FFFh	0	0	0	1	0
06000h-07FFFh	03000h-03FFFh	0	0	0	1	1
08000h-0FFFFh	04000h-07FFFh	0	0	1	X	X
10000h-1FFFFh	08000h-0FFFFh	0	1	X	X	X
20000h-2FFFFh	10000h-17FFFh	1	0	X	X	X
30000h-3FFFFh	18000h-1FFFFh	1	1	X	X	X

4/33

Command Interface

Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second,fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The 'Command' itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device to Read Array mode.

Instructions

Seven instructions are defined to perform Read Array, Auto Select(to read the ElectronicSignature or Block ProtectionStatus), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations.The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation.

Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interfacewhich iscommon to all instructions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection,the instructions for Program and Block or Chip Erase require furthercommandinputs. For a Programinstruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended,in orderto readdata from another block or to program data in another block, and then resumed.

When power is first applied or if VCC falls below VLKO, the command interface is reset to Read Array.

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A16). The address inputs for the memory array are latched during a write operation on the falling edge of Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A16, in Byte-wide organisation DQ15A±1 acts as an additional LSB address line.

M29F200T, M29F200B

When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A6, A12 and A15.

Data Input/Outputs (DQ0-DQ7). Th e se I n- puts/Outputsare used in the Byte-wide and Wordwide organisations. The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputsare disabled and when RP is at a Low level.

Data Input/Outputs (DQ8-DQ14 and DQ15A±1).

These Inputs/Outputs are additionally used in the Word-wide organisation.When BYTEis High DQ8DQ14 and DQ15A±1 act as the MSB of the Data Input or Output, functioning as described for DQ0DQ7 above, and DQ8-DQ15 are 'don't care' for command inputs or status outputs. When BYTE is Low, DQ8-DQ14 are high impedance, DQ15A±1 is the Address A±1 input.

Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselectsthe memory and reduces the power consumptionto the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Unprotection operation.

Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to VID level during Block Protection and Unprotection operations.

Write Enable (W). This input controls writing to the Command Registerand Addressand Datalatches.

Byte/Word Organization Select (BYTE). The BYTE input selects the output configuration for the device: Byte-wide (x8) mode or Word-wide (x16) mode. When BYTE is Low, the Byte-wide mode is selected and the data is read and programmed on DQ0-DQ7. In this mode, DQ8-DQ14 are at high impedance and DQ15A±1 is the LSB address. When BYTE is High, the Word-wide mode is selected and the data is read and programmed on DQ0-DQ15.

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M29F200T, M29F200B

Ready/Busy Output (RB). Ready/Busy is an open-drainoutput and gives the internalstate of the P/E.C. of the device. When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. WhenRB is High, the deviceis readyfor any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Standby modes.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset and protected block(s) temporary unprotection functions. Reset of the memory is acheived by pulling RP to VIL for at least 500ns. When the reset pulse is given, if the memory is in Read or Standby modes, it will be available for new operations in 50ns after the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take 10μs during which the RB signal will be held at VIL. The end of thememoryreset will beindicated by the rising edge of RB. A hardware reset during an Eraseor Programoperation will corrupt the data being programmed or the sector(s) being erased.

Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transition of RP from VIH to VID must slower than 500ns. When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected.

VCC Supply Voltage. The power supply for all operations (Read, Program and Erase).

VSS Ground. VSS is the reference for all voltage measurements.

DEVICE OPERATIONS

See Tables 4, 5 and 6.

Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory.

Write. Write operationsare used to give Instruction Commands to the memory or to latch input data to be programmed. A write operationis initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whicheveroccurs last. Commands and Input Data are latchedon the rising edge of W or E whichever occurs first.

Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High.

Standby. The memory is in standby when Chip Enable E is High and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs.

Automatic Standby. After 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus.

Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory. The manufacturer's code for STMicroelectronicsis 20h, the device code is D3h for the M29F200T (Top Boot) and D4h for the M29F200B (Bottom Boot). These codes allow programming equipment or applications to automatically match their interface to the characteristics of the M29F200. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at VID and address input A1 is Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7.

The Electronic Signature can also be read, without raising A9 to VID, by giving the memory the Instruction AS. If the Byte-wide configuration is selected the codes are output on DQ0-DQ7with DQ8-DQ14 at High impedance; if the Word-wide configuration is selected the codes are output on DQ0-DQ7 with DQ8-DQ15 at 00h.

Block Protection. Each block can be separately protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or eraseoperations.Thismode is activatedwhen both A9 and G are raised to VID and an address in the block is applied on A12-A16. The Block Protection algorithm is shown in Figure 14. Block protection is initiated on the edge of W falling to VIL. Then after a delay of 100μs, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G, E, A0and A6 to VIL and A1

to VIH, while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if

the block defined by the inputs on A12-A16 is protected. Any attempt to program or erase a protected block will be ignored by the device.

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M29F200T, M29F200B

Table 4. User Bus Operations (1)

Operation

E

G

W

RP

BYTE

A0

A1

A6

A9

A12

A15

DQ15

DQ8-

DQ0-DQ7

A±1

DQ14

Read Word

VIL

VIL

VIH

VIH

VIH

A0

A1

A6

A9

A12

A15

Data

Data

Data

Output

Output

Output

Read Byte

VIL

VIL

VIH

VIH

VIL

A0

A1

A6

A9

A12

A15

Address

Hi-Z

Data

Input

Output

Write Word

VIL

VIH

VIL

VIH

VIH

A0

A1

A6

A9

A12

A15

Data Input

Data Input

Data

Input

Write Byte

VIL

VIH

VIL

VIH

VIL

A0

A1

A6

A9

A12

A15

Address

Hi-Z

Data

Input

Input

Output Disable

VIL

VIH

VIH

VIH

X

X

X

X

X

X

X

Hi-Z

Hi-Z

Hi-Z

Standby

VIH

X

X

VIH

X

X

X

X

X

X

X

Hi-Z

Hi-Z

Hi-Z

Reset

X

X

X

VIL

X

X

X

X

X

X

X

Hi-Z

Hi-Z

Hi-Z

Block

VIL

VID

VIL Pulse

VIH

X

X

X

X

VID

X

X

X

X

X

Protection(2,4)

Blocks

VID

VID

VIL Pulse

VIH

X

X

X

X

VID

VIH

VIH

X

X

X

Unprotection(4)

Block

Block

Protection

VIL

VIL

VIH

VIH

X

VIL

VIH

VIL

VID

A12

A15

X

X

Protect

Verify(2,4)

Status (3)

Block

Block

Unprotection

VIL

VIL

VIH

VIH

X

VIL

VIH

VIH

VID

A12

A15

X

X

Protect

Verify(2,4)

Status (3)

Block

X

X

X

VID

X

X

X

X

X

X

X

X

X

X

Temporary

Unprotection

Notes: 1. X = VIL or VIH

2.Block Address must be given on A12-A16 bits.

3.See Table 6.

4.Operation performed on programming equipment.

Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)

	Org.	Code	Device	E	G	W	BYTE	A0	A1	Other	DQ15
										Addresses	A±1
		Manufact.		VIL	VIL	VIH	VIH	VIL	VIL	Don't Care	0
	Word-	Code
	wide	Device	M29F200T	VIL	VIL	VIH	VIH	VIH	VIL	Don't Care	0
		Code	M29F200B	VIL	VIL	VIH	VIH	VIH	VIL	Don't Care	0
		Manufact.		VIL	VIL	VIH	VIL	VIL	VIL	Don't Care	Don't
		Code									Care
	Byte-		M29F200T	VIL	VIL	VIH	VIL	VIH	VIL	Don't Care	Don't
	wide
		Device									Care
		Code									Don't
			M29F200B	VIL	VIL	VIH	VIL	VIH	VIL	Don't Care
											Care

DQ8 -	DQ0 -
DQ14	DQ7
00h	20h
00h	D3h
00h	D4h
Hi-Z	20h
Hi-Z	D3h
Hi-Z	D4h

Table 6. Read Block Protection with AS Instruction

	Code	E	G	W	A0	A1	A12 - A16	Other	DQ0 - DQ7
								Addresses
	Protected Block	VIL	VIL	VIH	VIL	VIH	Block Address	Don't Care	01h
	Unprotected Block	VIL	VIL	VIH	VIL	VIH	Block Address	Don't Care	00h

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M29F200T, M29F200B

Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporaryunprotection mode is activated by bringing RP to VID. During the temporary unprotection mode the previously protected blocks are unprotected. A block can be selected and data can be modified by executingthe Erase or Program instruction with the RP signal held at VID. When RP is returned to VIH, all the previously protected blocks are again protected.

Block Unprotection. All protected blocks can be unprotected on programming equipment to allow updating of bit contents. All blocks must first be protected before the unprotection operation. Block unprotection is activated when A9, G and E are at VID and A12, A15 at VIH. The Block Unprotection algorithm is shown in Figure 15. Unprotection is initiatedby theedge of W falling to VIL. Aftera delay of 10ms, the unprotection operation will end. Unprotectionverify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A12-A16 has been succesfully unprotected. Each block must be separatelyverified by giving its address in order to ensure that it has been unprotected.

INSTRUCTIONS AND COMMANDS

The Command Interface latches commands written to the memory. Instructions are made up from one or more commands to perform Read Memory Array, Read Electronic Signature, Read Block Protection, Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made of addressand data sequences. The instructionsrequire from 1 to 6 cycles,the first or firstthree of which are always write operationsused to initiate the instruction. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Instructions are initialised by two initial Coded cycles which unlock the Command Interface.In addition, for Erase, instruction confirmation is again preceded by the two Coded cycles.

Status Register Bits

P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase command executionwill automaticallyoutput these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked. See Tables 9 and 10.

Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. During Erase operation, it outputs a '0'. After completion of the operation, DQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. If all the blocks selected for erasure are protected, DQ7 will be set to '0' for about 100μs, and then return to the previous addressed memory data value. See Figure 11 for the Data Polling flowchart and Figure 10 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend mode, DQ7 will output '1' if the read is attempted on a blockbeing erasedand the data valueon other blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behaviour as in the normal program execution outside of the suspend mode.

Table 7. Commands

	Hex Code	Command
	00h	Invalid/Reserved
	10h	Chip Erase Confirm
	20h	Reserved
	30h	Block Erase Resume/Confirm
	80h	Set-up Erase
	90h	Read Electronic Signature/
		Block Protection Status
	A0h	Program
	B0h	Erase Suspend
	F0h	Read Array/Reset

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M29F200T, M29F200B

Table 8. Instructions (1)

Mne.

RD (2,4)

AS (4)

PG

BE

CE

ES (10)

ER

Instr.

Read/Reset

Memory Array

Auto Select

Program

Block Erase

Chip Erase

Erase

Suspend

Erase

Resume

Cyc.				1st Cyc.	2nd Cyc.	3rd Cyc.	4th Cyc.	5th Cyc.	6th Cyc.	7th Cyc.
1+	Addr. (3,7)			X	Read Memory Array until a new write cycle is initiated.
	Data			F0h
	Addr. (3,7)		Byte	AAAAh	5555h	AAAAh	Read Memory Array until a new write cycle
3+
			Word	5555h	2AAAh	5555h	is initiated.
	Data			AAh	55h	F0h
	Addr. (3,7)		Byte	AAAAh	5555h	AAAAh	Read Electronic Signature or Block
3+
			Word	5555h	2AAAh	5555h	Protection Status until a new write cycle is
							initiated. See Note 5 and 6.
	Data			AAh	55h	90h
	Addr. (3,7)		Byte	AAAAh	5555h	AAAAh	Program
4			Word	5555h	2AAAh	5555h	Address	Read Data Polling or Toggle Bit
								until Program completes.
	Data			AAh	55h	A0h	Program
							Data
	Addr.	(3,7)	Byte	AAAAh	5555h	AAAAh	AAAAh	5555h	Block	Additional
6			Word	5555h	2AAAh	5555h	5555h	2AAAh	Address	Block (8)
	Data			AAh	55h	80h	AAh	55h	30h	30h
	Addr. (3,7)		Byte	AAAAh	5555h	AAAAh	AAAAh	5555h	AAAAh
6										Note 9
			Word	5555h	2AAAh	5555h	5555h	2AAAh	5555h
	Data			AAh	55h	80h	AAh	55h	10h
1	Addr. (3,7)			X	Read until Toggle stops, then read all the data needed from any
					Block(s) not being erased then Resume Erase.
	Data			B0h
1	Addr. (3,7)			X	Read Data Polling or Toggle Bits until Erase completes or Erase is
					suspended another time
	Data			30h

Notes: 1. Commands not interpreted in this table will default to read array mode.

2.A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation.

3.X = Don't Care.

4.The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles.

5.Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output Device code.

6.Block Protection Address: A0 at VIL, A1 at VIH and A12-A16 within the Block will output the Block Protection status.

7.For Coded cycles address inputs A15 and A16 are don't care.

8.Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).

When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.

9.Read Data Polling, Toggle bits or RB until Erase completes.

10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

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M29F200T, M29F200B

Table 9. Status Register Bits

DQ	Name	Logic Level	Definition
		'1'	Erase Complete or erase
			block in Erase Suspend
7	Data	'0'	Erase On-going
	Polling
			Program Complete or data
		DQ	of non erase block during
			Erase Suspend
		DQ	Program On-going
		'-1-0-1-0-1-0-1-'	Erase or Program On-going
6	Toggle Bit	DQ	Program Complete
			Erase Complete or Erase
		'-1-1-1-1-1-1-1-'	Suspend on currently
			addressed block
5	Error Bit	'1'	Program or Erase Error
		'0'	Program or Erase On-going
4	Reserved
	Erase	'1'	Erase Timeout Period Expired
3
	Time Bit

'0'

'-1-0-1-0-1-0-1-'

2 Toggle Bit

1

DQ

1	Reserved
0	Reserved

Erase Timeout Period

On-going

Chip Erase, Erase or Erase Suspend on the currently addressed block.

Erase Error due to the currently addressed block (when DQ5 = '1').

Program on-going, Erase on-going on another block or Erase Complete

Erase Suspend read on non Erase Suspend block

Note

Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success.

Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged.

This bit is set to '1' in the case of Programming or Erase failure.

P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES).

An additional block to be erased in parallel can be entered to the P/E.C.

Indicates the erase status and allows to identify the erased block

Notes: Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementarydata. DQ6 will toggle following toggling of either G, or E when G is low. The operation is completed when two successive reads yield the same output data. The next readwill outputthe bit last programmed or a '1'after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for

Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100μs and then return back to Read. DQ6 will be set to '1' if a Read operationis attemptedon an Erase Suspendblock. When erase is suspended DQ6 will toggle during programming operations in a block different to the block in Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See Figure 12 for Toggle Bit flowchart and Figure 13 for Toggle Bit waveforms.

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