ST M29F102BB User Manual

查询29F102BB供应商

1 Mbit (64Kb x16, Boot Block) Single Supply Flash Memory

FEATURES SUMMARY

■ SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ
OPERATIONS

■ ACCESS TIME: 35ns

■ PROGRAMMING TIME

– 8µs per Word typical

■ 5 MEMORY BLOCKS

– 1 Boot Block (Bottom Location)
– 2 Parameter and 2 Main Blocks

■ PROGRAM/ERASE CONTROLLER

– Embedded Word Program algorithm
– Embedded Multi-Block/Chip Erase

algorithm

– Status Register Polling and Toggle Bits

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ M28F102 COMPATIBLE

– Pin-out and Read Mode

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– Bottom Device Code M29F102BB: 0097h

■ PACKAGES

– Compliant with Lead-Free Soldering

Processes

– Lead-Free Versions

M29F102BB

Figure 1. Package

PLCC44 (K)

TSOP40 (N)

10 x 14mm

1/24November 2004

M29F102BB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Bottom Boot Block Addresses, M29F102BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Inputs (A0-A15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Enable (E
Output Enable (G
Write Enable (W
Reset/Block Temporary Unprotect (RP
V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CC

Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

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M29F102BB

Table 5. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C). . . . . . 10

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Absolute Maximum Ratings (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9. Capacitance (TA = 25 °C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 10. DC Characteristics (T

Table 11. Read AC Characteristics (TA = 0 to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 °C) . . . . . . . . . . . . . . . 17

Figure 10.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 °C) . . . . . . . . . . . . . . . 18

Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 14. Reset/Block Temporary Unprotect AC Characteristics (T

Figure 12.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

= 0 to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

A

= 0 to 70°C). . . . . . . . . . . . . 19

A

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13.PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline . . . . . . . . . . . . . . . . . 20

Table 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data . . . . . . . . . . 20

Figure 14.TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Outline . . . . . . . . . 21

Table 16. PTSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Mechanical Data 21

ORDERING INFORMATION SCHEME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 18. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3/24

M29F102BB

SUMMARY DESCRIPTION

The M29F102BB is a 1 Mbit (64Kb x16) non-vola­tile memory that c an be read, erased and r epro­grammed. These operations can be performed
using a single 5V supply. On power-up the memo­ry defaults to i ts R ead m ode wh er e it c an b e re ad
in the same way as a ROM or EPROM.

The memory is divided into blocks that can be
erased independently s o i t is po ss ible to preserve
valid data while old data is erased. Each block can
be protected independen tly to prevent accidental
Program or Erase com mands from modifying the
memory. Program and Erase co mmands are writ­ten to the Command Int erface of the memo ry. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation ca n be detected
and any error conditions ide nti fie d. T he co mma nd
set required to control the memory is consistent
with JEDEC standards.

The blocks in the memo ry are asymmet rically ar­ranged, see Table 2., Bottom Boot Block Address-

es, M29F102BB. Th e first 32 Kwords have been

divided into four additional blocks. The 8 Kword
Boot Block can be used for small initialization code
to start the microproces sor, the two 4 Kword Pa­rameter Blocks can be used for parameter storage
and the remaining 16 Kwords are a small Main
Block where the application may be stored.

Chip Enable, Output Enable and Write Enable sig­nals control the bus operation of the memory.
They allow simple connection to most micropro­cessors, often without additional logic.

The memory is offered in PLCC44 and TSOP40
(10 x 14mm) packages. In addition to the standard
version, the packages are also avail able in Lead­free version, in compliance with JEDEC Std J­STD-020B, the ST ECOPACK 7191395 Specifica­tion, and the RoHS (Restriction of Hazardous Sub­stances) di rective. A ll package s are compli ant with
Lead-free soldering processes.

The memory is supplied with all the bits erased
(set to ’1’).

Figure 2. Logic Diagram

V

CC

16

A0-A15

W

E

G

RP

M29F102BB

V

SS

Table 1. Signal Names

A0-A15 Address Inputs
DQ0-DQ15 Data Inputs/Outputs
E
G
W
RP
V

CC

V

SS

NC Not Connected Inter na lly

Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Supply Voltage
Ground

16

DQ0-DQ15

AI02130C

Table 2. Bottom Boot Block Addresses, M29F102BB

# Size (KWords) Address Range

4 32 8000h-FFFFh
3 16 4000h-7FFFh
2 4 3000h-3FFFh
1 4 2000h-2FFFh
0 8 0000h-1FFFh

4/24

Figure 3. PLCC Connections Figure 4. TSOP Connections

M29F102BB

DQ12
DQ11
DQ10

DQ9
DQ8
V

SS

NC

DQ6
DQ5
DQ4

12

DQ13

DQ14

DQ3

DQ2

DQ15

RP

E

M29F102BB

23

G

DQ1

DQ0

A9

A10

CC

W

V

NC

44

1

NC

A15

A14

34

A13
A12
A11
A10
A9
V

SS

NC
A8DQ7
A7
A6
A5

A11
A12
A13
A14
A15

NC

V

CC
RP

DQ15
DQ14
DQ13
DQ12

A3

NC

A0

A1

A2

A4

AI02131C

DQ11
DQ10

DQ9
DQ8

1

W

10

M29F102BB

11

E

20 21

40

31
30

AI02132C

V

SS

A8
A7
A6
A5
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V

SS

5/24

M29F102BB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table

1., Signal Names, for a brief overview of the sig-

nals connected to this device.
Address Inputs (A0-A15). The Address Inputs

select the cells in the memory array to access dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the
Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ15). The Data In­puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations DQ0-DQ7 represent the com­mands sent to the Command Interface of the inter­nal state machine; the Comma nd Interface does
not use DQ8-DQ15 to decode the commands.

Chip Enable (E

the memory, allowing Bus Read and Bus Write op­erations to be performed. When Chip Enable is
High, V

IH

Output Enable (G

trols the Bus Read operation of the memory.

Write Enable (W

the Bus Write operation of the memory’s Com­mand Interface.

Reset/Block Temporary Un protect (RP

set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem­porarily unprotect al l blocks that have been pro­tected.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unp rotect Low, V

. After Reset/Block Temporary Unprotect

t

PLPX

goes High, V

). The Chip Enable, E, activates

, all other pins are ignored.

). The Output Enable, G, con-

). The Write Enabl e, W, controls

IL

, the memory will be ready fo r Bus

IH

). The Re-

, for at least

Read and Bus Write operations after t
or t

, whichever occurs last. See Table

PLYH

PHEL

13., Write AC Characteristics, Chip Enable Con­trolled (TA = 0 to 70 °C) and Figure 12., Reset/
Block Temporary Unprotect AC Waveforms.

Holding RP

at VID will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t

PHPHH

.

to VID must be slower than

IH

Reset/Block Temporary Unprotect can be left un­connected. A weak internal pull-up resistor en­sures that the memory always operates correctly.

Supply Voltage. The VCC Supply Voltage

V

CC

supplies the power for all operations (Read, Pro­gram, Erase etc.).

The Command Interface is disabled when the V

CC

Supply Voltage is le ss than the Lockout Vo ltage,

. This prevents Bus Write operations from ac-

V

LKO

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo­ry contents being altered will be invalid.

A 0.1µF capacito r should be connected between
the V

Supply Voltage pin and the VSS Ground

CC

pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

Vss Ground. The V

.

CC3

Ground is the reference

SS

for all voltage measurements.

6/24

BUS OPERATIONS

There are five standard bus operations that control
the device. These are Bus Read, Bus Writ e, Out­put Disable, Standby and Automatic Standby. See

Table 3., Bus Operations, for a summary. Ty pi cal-

ly glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the m emo ry and do not af­fect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address
Inputs, applying a Low s ig nal, V
and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will ou tpu t the

IH

value, see Figure 9., Read Mode AC Wavefor ms,
and Table 11., Read AC Characteristics (TA = 0 to

70°C), for details of wh en t he o utpu t be comes val-

id.
Bus Write. Bus Write operations write to the

Command Interface. A v alid Bus Write operati on
begins by setting the desired address on the Ad­dress Inputs. The Ad dress Inputs are latched b y
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs ar e latched by the Com ­mand Interface on the rising ed ge of Chip Enab le
or Write Enable, whichever occurs first. Output En­able must remain High, V

IH

Write operation. See Figures 10 and 11, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require­ments.

Output Disable. The Data Inputs/Outpu ts are in
the high impedance state when Output Enable is
High, V

.

IH

Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high-imped­ance state. To reduce the Su pply Current to the

, to Chip Enable

IL

, during the whole Bus

, the

IH

M29F102BB

Standby Supply Current, I
be held within V

± 0.2V. For the Standby current

CC

level see Table 10., DC Characteristics (T

70°C).

During program or eras e operations the memory
will continue to use the Program/Erase Supply
Current, I

, for Program or Erase operations un-

CC3

til the operation completes.
Automatic Standby. If CMOS levels (V

are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the interna l Supply Current is re­duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera­tions are intended for us e by progr ammin g equip ­ment and are not usually used in applications.
They require V

to be applied to some pins.

ID

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can b e read b y apply ing the sig nals
listed in Table 3., Bus Operat ion s.

Block Protection and Blocks Unprotection. Each
block can be separately protected against acci­dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.

There are two methods available for protecting
and unprotecting the b locks, one for use on pro­gramming equipment and t he other for in-system
use. For further information refer to Application
Note AN1122, Applying Protectio n and Unpr otec­tion to M29 Series Flash.

, Chip Enable should

CC2

CC

CC2

= 0 to

A

± 0.2V)

. The

Table 3. Bus Operations

Operation E G W Address Inputs

Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer

Code

Read Device Code

Note: 1. X = VIL or VIH.

Data

Inputs/Outputs

V

IL

V

IL

V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

X X X Hi-Z

V

IL

V

IL

V
V
V

V

V

Cell Address Data Output

IH

Command Address Data Input

IL

X Hi-Z

IH

A0 = VIL, A1 = VIL, A9 = VID,

IH

Others V
A0 = VIH, A1 = VIL, A9 = VID,

IH

Others V

IL

IL

or V

or V

IH

IH

0020h

0097h

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M29F102BB

COMMAND INTERFACE

All Bus Write operations to the memory are inter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. Failure to observe a valid sequence of Bus
Write operation s will result in the memory return ­ing to Read mode. The long command sequences
are imposed to maximize data security.

The commands are summarized in Table

4., Commands. Refer to Table 4. in conjunction

with the text descriptions below.
Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where
it behaves lik e a ROM or EPROM. I t also resets
the errors in the Status Register. Either one or
three Bus Write o perations can be us ed to issue
the Read/Reset command.

If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take up to 10
to abort. During the abort period no valid data can
be read from the memory. Issu ing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.

Auto Select Command. The Auto Select com­mand is used to read t he Manu facturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re­quired to issue the Auto Sel ect command. Once
the Auto Select comman d is issued the memory
remains in Auto Sele ct mode until another com­mand is issued.

From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V

and A1 = VIL. The other address bits

IL

or VIH. The Manufacturer

IL

Code for STMicroelectronics is 0020h.
The Device Code ca n be read using a Bu s Read

operation with A0 = V
address bits may be s et to either V

and A1 = VIL. The other

IH

or VIH. The

IL

Device Code for the M29F102BB is 0097h.
The Block Protectio n Statu s of ea ch block c an be

read using a Bus Read ope ration with A0 = V
A1 = V

, and A12-A15 s pecifying the addr ess of

IH

the block. The other address bits may be set to ei­ther V

or VIH. If the addressed block is protected

IL

then 01h is output on Data Inputs/Outputs
DQ0-DQ7, otherwise 00h is output.

Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re­quires four Bus Write operations, the final write op­eration latches the address and data in the internal
state machine and starts the Program/Erase Con­troller.

µs

IL

If the address falls in a protect ed block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.

During the program operation th e memory will ig ­nore all commands. It is no t possib le to is sue any
command to abort or pause the operation. Typical
program times are given in Table 5.. Bus Read op­erations during the p rogram operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.

After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

Note that the Program command cannot change a
bit set at ’0’ back t o ’1’. One of the Erase Com­mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo­ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com­mands. Three Bu s Write operations are r equired
to issue the Unlock Bypass command.

Once the Unlock Bypass c ommand has been is­sued the memory will only accept the Unlock By­pass Program com mand and the Unlock B ypass
Reset command. The memory can be read as if in
Read mode.

Unlock Bypass Program Command. The Un­lock Bypass Program command can be used to
program one address in memory at a time. The
command requires t wo Bus Write oper ations, the
final write operati on lat ches the a ddress and d ata
in the internal state machine and starts the Pro­gram/Erase Controller.

,

The Program operation us ing the Unlock Bypass
Program command behaves identically to the Pro­gram operation using the Program command. A
protected block cannot be progra mme d; the op er­ation cannot be aborted and the Status Register is
read. Errors must be reset using th e Read/Reset
command, which leav es the device in Unlock By­pass Mode. See the Program command for details
on the behavior.

Unlock Bypass Reset Command. The Unlock
Bypass Reset comm and can b e used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command.

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