ST M29F100BT, M29F100BB User Manual

查询M295V100B-B120M1T供应商

1 Mbit (128Kb x8 or 64Kb x16, Boot Block)

■ SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 45ns

■ PROGRAMMING TIME

–8µs per Byte/Word typical

■ 5 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 2 Main Blocks

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– Top Device Code M29F100BT: 00D0h
– Bottom Device Code M29F100BB: 00D1h

M29F100BT

M29F100BB

Single Supply Flash Memory

44

1

TSOP48 (N)

12 x 20mm

Figure 1. Logic Diagram

V

CC

16

A0-A15

W

E

G

RP

M29F100BT

M29F100BB

V

SS

SO44 (M)

15

DQ0-DQ14

DQ15A–1
BYTE
RB

AI02916

1/22July 2000

M29F100BT, M29F100BB

Figure 2. TSOP Connections

A15
A14
A13
A12
A11
A10 DQ14

NC
NC

RP
NC
NC
RB
NC
NC

1

A9
A8

W

12

M29F100BT
M29F100BB

13

A7
A6
A5
A4
A3
A2

24 25

A1

48

37
36

AI02917

NC
BYTE
V

SS

DQ15A–1
DQ7

DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V

SS

E
A0

Figure 3. SO Connections

NC RP

NC A8

V

SS

DQ0
DQ8

DQ9

DQ10

DQ3

DQ11

A7
A6
A5
A4
A3
A2
A1
A0

1
2
3
4
5
6
7
8
9
10
11

M29F100BT

E

G

M29F100BB

12
13
14
15
16
17DQ1
18
19
20
21

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322

AI02918

WRB

A9
A10
A11
A12
A13
A14
A15
NC
BYTE
V

SS

DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5DQ2
DQ12
DQ4
V

CC

Table 1. Signal Names

A0-A15 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
V

CC

V

SS

NC Not Connected Internally

2/22

Supply Voltage
Ground

SUMMARY DESCRIPTION

The M29F100B isa 1 Mbit (128Kbx8 or 64Kb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per­formed using a single 5V supply.On power-up the
memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM. The
M29F100B is fully backward compatible with the
M29F100.

The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ­ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memoryby
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

M29F100BT, M29F100BB

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

V

ID

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions for extended periods may affect device reliability. Referalso to the STMicroelectronics SUREProgram and otherrelevant qual­ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C
Temperature Under Bias –50 to 125 °C

Storage Temperature –65 to 150 °C
Input or Output Voltage –0.6 to 6 V
Supply Voltage –0.6 to 6 V

Identification Voltage –0.6 to 13.5 V

The blocks in the memory are asymmetrically ar­ranged, seeTables3 and 4,Block Addresses.The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small initialization code to start the micro­processor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application

(1)

Chip Enable, Output Enableand Write Enable sig­nals control the bus operation of the memory.
They allow simple connection to most micropro­cessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).

may be stored.

Table 3. Top Boot Block Addresses
M29F100BT

Size

#

(Kbyte

4 16 1C000h-1FFFFh E000h-FFFFh
3 8 1A000h-1BFFFh D000h-DFFFh
2 8 18000h-19FFFh C000h-CFFFh
1 32 10000h-17FFFh 8000h-BFFFh
0 64 00000h-0FFFFh 0000h-7FFFh

s)

Address Range

(x8)

Address Range

(x16)

Table 4. Bottom Boot Block Addresses
M29F100BB

Size

#

(Kbyte

4 64 10000h-1FFFFh 8000h-FFFFh
3 32 08000h-0FFFFh 4000h-7FFFh
2 8 06000h-07FFFh 3000h-3FFFh
1 8 04000h-05FFFh 2000h-2FFFh
0 16 00000h-03FFFh 0000h-1FFFh

s)

Address Range

(x8)

Address Range

(x16)

3/22

M29F100BT, M29F100BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal
Names, forabrief overview of the signals connect­ed to this device.

Address Inputs (A0-A15). The Address Inputs
select the cells in the memory array to access dur­ing Bus Read operations. During BusWrite opera­tions they control the commands sent to the
Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In­puts/Outputs outputthedatastoredat the selected
address during a Bus Read operation. DuringBus
Write operations they represent the commands
sent totheCommandInterface of theinternalstate
machine.

Data Inputs/Outputs (DQ8-DQ14). The Data In­puts/Outputs outputthedatastoredat the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low willselect the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In­puts to include this pin when BYTE is Low except
when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates
the memory,allowing Bus Read and Bus Writeop­erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con­trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com­mand Interface.

Reset/BlockTemporaryUnprotect(RP). The Re­set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem­porarily unprotect all Blocks that have been pro­tected.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
t

. After Reset/Block Temporary Unprotect

PLPX

goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after t

PHEL

or

t

, whicheveroccurs last. See the Ready/Busy

RHEL

Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.

Holding RP at VIDwill temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIHtoVIDmustbe slower than
t

PHPHH

.

Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode,Auto Select
mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be­comes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteris­tics.

During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/
Busy pins from several memories tobe connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se­lect is Low, VIL, the memory is in 8-bit mode, when
it is High, VIH, the memory is in 16-bit mode.

VCCSupply Voltage. The VCCSupply Voltage
supplies the power for all operations (Read, Pro­gram, Erase etc.).

The Command Interface is disabled when the V

CC

Supply Voltage is less than the Lockout Voltage,
V

. Thisprevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo­ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between
the VCCSupply Voltage pin and the VSSGround
pin to decouple the current surges from the power
supply. The PCB track widthsmust be sufficient to
carry the currents required during program and
erase operations, I

CC4

.

Vss Ground. The VSSGround is the reference
for all voltage measurements.

4/22

M29F100BT, M29F100BB

BUS OPERATIONS

There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out­put Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than5ns on Chip Enable
or Write Enable are ignoredby the memory and do
not affect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.

Table 5. Bus Operations, BYTE = V

Operation E G W

Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer

Code

Read Device Code

Note: X = VILor VIH.

V

IL

V

IL

V

IH

V

IL

V

IL

IL

V

IL

V

IH

V

IH

V

Cell Address Hi-Z Data Output

IH

V

Command Address Hi-Z Data Input

IL

V

X Hi-Z Hi-Z

IH

X X X Hi-Z Hi-Z

V

IL

V

IL

A0 = VIL,A1=VIL,A9=VID,

V

IH

Others V
A0 = VIH,A1=VIL,A9=VID,

V

IH

Others V

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad­dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com­mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occursfirst. OutputEn­able must remain High, VIH, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing require­ments.

Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.

Address Inputs

DQ15A–1, A0-A15

or V

IL

IH

or V

IL

IH

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Hi-Z 20h

Hi-Z

D0h (M29F100BT)
D1h (M29F100BB)

Table 6. Bus Operations, BYTE = V

Operation E G W

Bus Read V
Bus Write

IL

V

IL

Output Disable X V
Standby
Read Manufacturer

Code

Read Device Code

Note: X = VILor VIH.

V

IH

V

IL

V

IL

V

IL

V

IH

IH

X X X Hi-Z

V

IL

V

IL

IH

Address Inputs

A0-A15

V

Cell Address Data Output

IH

V

Command Address Data Input

IL

V

X Hi-Z

IH

A0 = VIL,A1=VIL,A9=VID,

V

IH

Others V
A0 = VIH,A1=VIL,A9=VID,

V

IH

Others V

IL

IL

or V

or V

IH

IH

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

0020h

00D0h (M29F100BT)
00D1h (M29F100BB)

5/22

M29F100BT, M29F100BB

Standby. When Chip Enable is High, VIH, the

Data Inputs/Outputs pins are placed in the high­impedance state and the Supply Current is re­duced to the Standby level.

When Chip Enable is at VIHthe Supply Current is
reduced to the TTL Standby Supply Current, I

CC2

To furtherreduce the Supply Current to theCMOS
Standby Supply Current, I

, ChipEnableshould

CC3

be held within VCC± 0.2V. For Standby current
levels see Table 13, DC Characteristics.

During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

, forProgram or Erase operations un-

CC4

til the operation completes.
AutomaticStandby. If CMOS levels (VCC± 0.2V)

are usedto drive the busand the busis inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re­duced totheCMOS Standby Supply Current, I

CC3

The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera­tions are intended for use by programming equip­ment and are not usually used in applications.
They require VIDto be applied to some pins.

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 5 and 6, Bus Operations.

Block Protection and BlocksUnprotection. Each
block can be separately protected against acci­dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.

There are two methods available for protecting
and unprotecting the blocks, one for use on pro­gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec­tion to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are inter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return­ing to Readmode. The long command sequences
are imposed to maximize data security.

The address used for the commands changes de-

.

pending on whether the memory is in 16-bit or 8­bit mode. See either Table 7, or 8, depending on
the configuration that isbeing used, for a summary
of the commands.

Read/Reset Command. The Read/Reset com­mand returnsthe memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.

If the Read/Reset command is issued during a
Block Erase operation or following aProgramming
or Erase error then the memory will take upto 10µs

.

to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.

Auto Select Command. The Auto Select com­mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re­quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com­mand is issued.

From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VILandA1 = VIL. The other address bits
may be set to either VILor VIH. The Manufacturer
Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read
operation with A0 = VIHand A1 = VIL. The other
address bits may be set to either VILor VIH. The
Device Code for the M29F100BT is 00D0h and for
the M29F100BB is 00D1h.

The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A15 specifying the address of
the block. The other address bits may be set to ei­ther VILor VIH. If the addressed block is protect­ed then 01h is output on Data Inputs/Outputs
DQ0-DQ7, otherwise 00h is output.

6/22

M29F100BT, M29F100BB

Table 7. Commands, 16-bit mode, BYTE = V

IH

Bus Write Operations

Command

Read/Reset

1X F0
3 555 AA 2AA 55 X F0

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30

Table 8. Commands, 8-bit mode, BYTE = V

IL

Bus Write Operations

Command

Read/Reset

1X F0
3 AAA AA 555 55 X F0

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A15, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is V

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After theEraseSuspend command read non-erasing memory blocks as normal, issue AutoSelect and Program commands

on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

or DQ15 when BYTE is VIH.

IL

7/22