ST M29F080D User Manual
FEATURES SUMMARY
■ SUPPLY VOLTAGE
–V
5V ±10% for PROGRAM, ERASE and
CC =
READ OPERATIONS
■ ACCESS TIME: 55, 70, 90ns
■ PROGRAMMING TIME
– 10µs per Byte typical
■ 16 UNIFORM 64Kbyte MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithms
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code : 20h
– Device Code: F1h
■ ECOPACK
®
PACKAGES AVAILABLE
M29F080D
8 Mbit (1Mb x8, Uniform Block)
5V Supply Flash Memory
Figure 1. Packages
TSOP40 (N)
10 x 20mm
SO44 (M)
1/37September 2005
M29F080D
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
Supply Voltage (5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
V
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SS
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29F080D
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 13
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 23
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 23
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline. . . . . . . . . . . . . . . . 24
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . . . . . . . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Block Addresses, M29F080D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/37
M29F080D
Table 16. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 17. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 18. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 20. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. Programmer Tech niq ue Bus Ope ra tio ns , BYTE = V
Figure 14. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
or VIL . . . . . . . . . . . . . . . . . . . . . 31
IH
4/37
SUMMARY DESCRIPTION
The M29F080D is a 8 Mb it (1Mb x8) non-v olatile
memory that can be read, erased and reprogrammed. These operations can be performed using a single low volta ge 5V supply. On power-up
the memory defaults to its Read mode where it can
be read in the same way as a ROM or EPROM.
The memory is divided into 16 un iform blocks of
64Kbytes (see Figure 5, Block Addresses) that
can be erased in dependently so it is possible to
preserve valid data while old data is erased.
Blocks can be pr otect ed in grou ps of 4 to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the proces s of programming or era sing
the memory by taking care of all of the special operations that are required to upd ate the memory
contents. The end of a program or erase operation
can be detected an d any error conditions identified. The command set required to control the
memory is consistent with JEDEC standards.
M29F080D
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP40 (10 x 20mm) and
SO44 packages. Access times of 55, 70 and 90ns
are available.
In order to meet environme ntal requirements, ST
offers the M29F080D in ECOPACK
ECOPACK packages are Lead-free. The category
of second Level Interconnect is marked on the
package and on the inner box label, in compliance
with JEDE C Stand ard JESD 97. The m aximum ratings related to soldering conditions are also
marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
The memory is supplied with all the bits erased
(set to ’1’).
®
packages.
Figure 2. Logic Diagram Table 1. Signal Names
A0-A19 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
E
G
W
RP
RB
V
CC
V
SS
NC Not Connected Internally
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
Ground
A0-A19
RP
W
V
CC
20
E
G
M29F080D
V
SS
8
DQ0-DQ7
RB
AI06141
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M29F080D
Figure 3. TSOP Connections Figure 4. SO Connections
A19
A18
A17
A16
A15
A14
A13
A12
V
A11
CC
NC
RP
A9
A8
A7
A6
A5
A4
1
E
10
M29F080D
11
20 21
40
31
30
NC
NC
W
G
RB
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2A10
DQ1
DQ0
A0
A1
A2
A3
NC
RP
A11 A12
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
M29F080D
12
13
14
15
16
17DQ0
DQ1
18
19
DQ3
V
SS
V
SS
20
21
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322
V
E
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
W
G
RB
DQ7
DQ6DQ2
DQ5
DQ4
V
CC
CC
AI06142
AI06143
6/37
Figure 5. Block Addresses
M29F080D
M29F080D
Block Addresses
0FFFFFh
0F0000h
0EFFFFh
0E0000h
0DFFFFh
0D0000h
0CFFFFh
02FFFFh
020000h
01FFFFh
010000h
00FFFFh
000000h
Note: Also see Appendix A, Table 15 for a full listing of the Block Addresses.
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
Total of 16
64 KByte Blocks
AI06144
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M29F080D
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diag ra m, an d T ab le 1 , Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they repr esent the commands s ent to the Command Interface of th e internal state machine.
Chip Enable (E
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
IH
Output Enable (G
trols the Bus Read operation of the memory.
Write Enable (W
the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to ap p l y a Ha rd w a r e Reset to th e m e mo ry or to temporarily unprotect a ll Bloc k s that have been protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unp rotect Low, V
. After Reset/Block Temporary Unprotect
t
PLPX
goes High, V
Read and Bus Write operations after t
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP
protected Blocks in the memory. Program and
). The Chip Enable, E, activates
, all other pins are ignored.
). The Output Enable, G, con -
). The Write Enable, W, controls
, for at least
IL
, the memory will be ready fo r Bus
IH
PHEL
at VID will temporarily unprotect the
or
Erase operations on all blocks will be possible.
The transition from V
t
PHPHH
.
Ready/Busy Output (RB
to VID must be slower than
IH
). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
. Ready/Busy is hig h-im-
OL
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedan ce . S ee Tabl e 13 an d F i gure
13, Reset/Temporary Unprotect AC Characteristics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V
Supply Voltage (5V). VCC provides the
CC
power supply for all operations (Read, Program
and Erase).
The Command Interface is disabled when the V
CC
Supply Voltage is le ss than the Lockout Vo ltage,
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor sh ould be connected between
the V
Supply Voltage pin and the VSS Ground
CC
pin to decouple the current surges from the power
supply, see Figure 10, AC Measurement Load Circuit. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
V
Ground. VSS is the referenc e for all volta ge
SS
CC3
.
measurements.
8/37
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Writ e, Output Disable, Standby and Automatic Standby. See
Tables 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the m emo ry and do not affect bus operations.
Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low s ig nal, V
, to Chip Enable
IL
and Output Enable and keeping Write Enable
High, V
. The Data Inputs/Outputs will ou tpu t the
IH
value, see Figure 10, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the Command Interface. A v alid Bus Write operati on begins by setting the desired address on the Address Inputs. The Ad dress Inputs are latched b y the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs ar e latched by the Com mand Interface on the rising ed ge of Chip Enab le or Write Enable, whichever occurs first. Output Enable must remain High, V
, during the whole Bus
IH
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs /Outputs are in the high impedance state when Output Enable is High, V
Standby. When Chip Enable is High, V
.
IH
, the
IH
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Su pply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
M29F080D
be held within V
level see Table 9, DC Characteristics.
During program or eras e operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
til the operation completes. Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the interna l Supply Current is reduced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for us e by progr ammin g equip ment and are not usually used in applications.
They require V
Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can b e read b y apply ing the sig nals listed in Tables 2, Bus Operations.
Block Protection and Blocks Unprotection.
Blocks can be protected in groups of 4 against ac-
cidental Program or Erase. See Appendix A, Table
15, Block Addresses, for de tails of which blocks
must be protected to gether a s a g roup. Protec ted
blocks can be unprotected to allow data to be
changed.
There are two methods available for protecting
and unprotecting the b locks, one for use on programming equipment and t he other for in-system
use. Block Protect a nd Chip Unprotect operations
are described in Appendix C.
± 0.2V. For the Standby current
CC
, for Program or Erase operations un-
± 0.2V)
CC
. The
CC2
to be applied to some pins.
ID
Table 2. Bus Operations
Operation E G W
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VIL or VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
Address Inputs
A0-A19
V
IL
V
IH
V
IH
X X X Hi-Z
V
IL
V
IL
V
Cell Address Data Output
IH
V
Command Address Data Input
IL
V
X Hi-Z
IH
A0 = VIL, A1 = VIL, A9 = VID, Others
V
IH
V
IH
or V
V
IL
IH
A0 = VIH, A1 = VIL,
A9 = VID, Others VIL or V
IH
Data Inputs/Outputs
DQ7-DQ0
20h
F1h
9/37
M29F080D
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operation s will result in the memory return ing to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Table 3, Comman ds, in conjunction wi th
the following text descriptions.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the erro rs in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. Once th e pro gram or era se oper ation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select command is used to read t he Manu facturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Sel ect command. Once the Auto Select comman d is issued the memory remains in Auto Sele ct mode until a Read/Res et command is issue d. Read CFI Query and Re ad/ Reset commands are accepted in Auto Select mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V
Code for STMicroelectronics is 20h.
The Device Code ca n be read using a Bu s Read
operation with A0 = V
address bits may be s et to either V
Device Code for the M29F080D F1h.
The Block Protection Status of each block can be
read using a Bus Read oper ation with A0 = V
A1 = V
the block. The other address bits may be set to either V
IL
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.
and A1 = VIL. The other address bits
IL
, and A12-A19 specifying the address of
IH
or VIH. The Manufacturer
IL
and A1 = VIL. The other
IH
or VIH. The
IL
or VIH. If the addressed block is protected
IL
If the address falls in a protect ed block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation th e memory will ig nore all commands. It is no t possib le to is sue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read operations during the p rogram operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back t o ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the cycle time to th e device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bu s Write operations are r equired to issue the Unlock Bypass command.
Once the Unlock Bypass c ommand has been issued the memory will only accept the Unlock Bypass Program com mand and the Unlock B ypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the int ernal state machine and starts the Program/Erase Controller.
The Program operation us ing the Unlock Bypass
Program command behaves identically to the Pro-
,
gram operation using the Program command. A
protected block cannot be progra mme d; the op eration cannot be aborted and the Status Register is
read. Errors must be reset using th e Read/Reset
command, which leav es the device in Unlock Bypass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock Bypass Reset comm and can b e used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset
10/37
M29F080D
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unc hanged . No er ror con dition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, includin g the Er ase S usp end command. It is not po ssible to issue any co mmand to
abort the operation. Typ ical chip erase times ar e
given in Table 4. All Bus Read ope rations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase o per at ion has c om ple ted the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase command can be used to erase a l ist of one or more blocks. Six Bus W rite operations are required to select the first block in the list. Each additional block in the list can be select ed by repeating the sixth Bus Write operation using the address of the additional block. The Bloc k Er as e op erati on st ar ts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth
Bus Write operation. See the Status Register section for details on how to identify if the Program/
Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the sel ected blocks are pr otected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Eras e o perat ion the memory will
ignore all comman ds except the Erase Suspe nd
command. Typical block eras e times a re given in
Table 4. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. S ee the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error conditio n and return to Read mode.
The Block Erase Comma nd sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase S u sp en d Command may be used to tempor arily suspend a Block Erase operation a nd return the memory to Read mode. The command requires one Bus Write operation.
The Program/Erase Control ler will sus pend with in
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additiona l block (before
the Program/Erase Controller starts) then the
Erase is suspende d i mme di atel y and will start immediately when the Eras e Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
11/37
M29F080D
During Erase Suspend i t is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. I f any atte mpt is made to
program in a protected bloc k or in the susp ended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error c ondition is gi ven. Read ing from blocks that are being erased will output
the Status Register.
It is also possible to iss ue the Auto Select, Read
CFI Query and Unlock Bypass com mands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be accepted.
Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller after an Erase Suspend. The device must be in Read Array mode before t he Resume command will be accepted. An erase can be suspended and resumed more than once.
Read CFI Query Command. The Read CFI Query Command is used to read data from the Common Fl ash In ter face (CFI) Memor y Ar ea. Th is
command is valid when the device is in the Read
Array mode, or when the device is in Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command . Once the command is issued subsequent Bus Read operatio ns read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issue d to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/
Reset command would be needed if the d evice i s
to be put in the Read Array mode from Autoselected mode.
See Appendix B, Tables 16, 17, 18, 19, 20 and 21
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Block Protect and Chip Unprotect Com-
mands. Groups of blocks can be protected
against accidental Progr am or Er as e. The Pr o tec tion Groups are show n in Appendix A, Table 15.
The whole chip ca n be unprotected to allow the
data inside the blocks to be changed.
Block Protect an d Chip Unprotect ope rations are
described in Appendix C.
12/37
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