ST M29F040 User Manual

M29F040

4 Mbit (512Kb x8, Uniform Block) Singl e Supply Flash Memory

NOT FOR NEW DESIGN

M29F040 is replaced by the M29F040B

5V ± 10% SUPPLY VOLTAGE for PROGRAM , ERASE and READ OPERATIONS

FA ST A CCE SS TI ME: 70ns BYTE PROGRAMMING TIME: 10µs typical ERASE TIME – Block: 1.0 sec typical – Chip: 2.5 sec typical PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Byte-by-Byte – Data Polling and Toggle bits Protocol for

P/E.C. Stat us MEMORY ERASE in BLOCKS – 8 Uniform Blocks of 64 KBytes each – Block Protection – Multiblock Erase ERASE SUSPEND and RESUME MODES LOW POWER CONSUMP TION – Read mode: 8mA typical (at 12MHz) – Stand-by mode: 25µA typical – Automatic Stand-by mode 100,000 PROGRAM/ERASE CYCLES per

BLOCK 20 YEARS DAT A RETENTION – Defectivity below 1ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: E2h

Figure 1. Logic Diagram

PLCC32 (K) TSOP32 (N)

A0-A18

M29F040

8 x 20 mm

DQ0-DQ7

Table 1. Signal Names

A0-A18 Address Inputs DQ0-DQ7 Data Input / Outputs E Chip Enable G Output Enable W Write Enable V

November 1999 1/31

This is information on a product still in production but not recommended for new designs.

Supply Voltage Ground

AI01372

M29F040

Figure 2A. LCC Pin Connections

A18

DQ3

DQ4

DQ5

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A16

A12

A15

DQ1

DQ2

M29F040

A17

DQ6

A14 A13 A8 A9 A11 G A10 E DQ7

AI01378

Figure 2B. TSOP Pin Connections

A11 G

A13 A14 A17

A18 A16 A15 A12

1 A9 A8

M29F040

(Normal)

A7 A6 A5

16 17

A4 A3

25 24

AI01379

A10 E DQ7 DQ6 DQ5 DQ4 DQ3 V

DQ2 DQ1 DQ0 A0 A1 A2

Figure 2C. TSOP Reverse Pin Connections

A11G A9 A8 A13 A14 A17 W V

A18 A16 A15 A12 A7 A6 A5 A4A3

A10

DQ7 DQ6 DQ5 DQ4 DQ3 V

DQ2 DQ1 DQ0

A0 A1 A2

8 9

16 17

M29F040

(Reverse)

25 24

AI01174B

DESCRIPTION

The M29F040 is a non-volatile memory that may be erased electrically at the block level, and programmed Byte-by-Byte.

The interface is directly compatible with most microprocessors. PLCC32 and TSOP32 (8 x 20mm) packages are available. Both normal and reverse pin outs are available for the TSOP32 package.

Organisation

The Flash Memory organisation is 512K x8 bits with Address lines A0-A18 and Data Inputs/Outputs DQ0-DQ7. Memory control is provided by Chip Enable, Output Enable and Write Enable Inputs.

Erase and Program are performed through the internal Program/Erase Controller (P/E.C.).

Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to indicate the Ready/Busy state of the internal Program/Erase Controller.

Memory Blocks

Erasure of the memory is in blocks. There are 8 uniform blocks of 64 Kbytes each in the memory address space. Each block can be programmed and erased over 100,000 cycles. Each uniform block may separately be protected and unpro-

2/31

M29F040

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

Notes:

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to t he STM icro e lect ronics SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 Storage Temperature –65 to 150 Input or Output Voltages –0.6 to 7 V Supply Voltage –0.6 to 7 V A9 Voltage –0.6 to 13.5 V

tected against program and erase. Block erasure may be suspended, while data is read from other blocks of the memory, and then resumed.

Bus Operations

Seven operations can be performed by the appropriate bus cycles, Read Array, Read Electronic Signature, Output Disable, Standby , P rotect Block, Unprotect Block, and Write the Command of an Instruction.

Command Interface

Command Bytes can be written to a Command Interface (C.I.) latch to perform Reading (from the Array or Electronic Signature), Erasure or Programming. For added da ta protection, command execution starts after 4 or 6 command cycles. The first, second, fourth and fifth cycles are used to input a code sequence to the Command Inter face (C.I.). This sequence is equal for all P/E.C. instructions. Command itself and its confirmation - if it applies - are given on the third and fourth or sixth cycles.

Instructions

Seven instructions are defined to perform Reset, Read Electronic Signature, Auto Program, Block Auto Erase, Chip Auto Erase, Block Erase S uspend and Block Erase Resume. The internal Program/Erase Controller (P/E.C.) handles all timing and verification of the Program and Erase instruc-

(1)

(3)

–40 to 125

tions and provides Data Polling, T oggle, and Status data to indicate completion of Program and Erase Operations.

Instructions are composed of up to six cycles. The first two cycles input a code sequence to the Command Interface which is common to all P/E.C. instructions (see Table 7 for Command Descriptions). The third cycle inputs the instruction set up command instruction to the Command Interface. Subsequent cycles output Signature, Block Protection or the addressed data for Read operations. For added data protection, the instructions for program, and block or chip erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (block or chip), the fourth and fifth cycles input a further code sequence before the Erase confirm command on the sixth cycle. Byte programming t akes typically 10µs while erase is performed in typically 1.0 second.

Erasure of a memory block may be suspended, in order to read data from another block, and then resumed. Data Polling, Toggle and Error data may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. When power is first applied or if V falls below V

, the command interface is reset to

LKO

Read Array.

3/31

M29F040

Table 3. Operations

Operation E G W DQ0 - DQ7

Read V Write V Output Disable V Standby V

Note:

X = V

or V

Table 4. Electronic Signature

X X Hi-Z

Data Output

Data Input

Hi-Z

Code E G WA0A1A6A9

Manufact. Code V Device Code V

Table 5. Block Protection Status

Code E G W A0 A1 A6 A16 A17 A18

Protected Block V Unprotected Block V

Note:

SA = Address of block being checked

DEVICE OPERATION Signal Descriptions Address Inputs (A0-A18).

the memory array are latched during a write operation. The A9 address input is used also for the Electronic Signature read and Block Protect verification. When A9 is raised to V Manufacturer Code, Read Device Code or Verify Block Protection is enabled depending on the com bination of levels on A0, A1 and A6. When A0, A1 and A6 are Low, the Electronic Signature Manufacturer code is read, when A0 is High and A1 and A6 are Low, the Device code is read, and when A1 is High and A0 and A6 ar e low, the Block Protection Status is read for the block addressed by A16, A17, A18.

Data Input/Outputs (DQ0-DQ7).

a byte to be programmed or a command written to the C.I. Both are latched when Chip Enable Write Enable

W are active. The data output is from the memory Array, the Electronic Signature, the Data Polling bit (DQ7), t he Toggle Bit (DQ6), the Error bit (DQ5) or the Erase Timer bit (DQ3). Ouputs are valid when Chip Enable Enable

G are active. The output is high impedance

The address inputs for

, either a Read

The data input is

E and Output

V V

E and

SA SA SA Don’t Care 01h

SA SA SA Don’t Care 00h

when the chip is deselected or the outputs are disabled.

Chip Enable (

memory control logic, input buffers, decoders and sense amplifiers. reduces the power consumption to the standby

E can also be used to control writing to the

level. command register and to the memory array, while W remains at a low level. Addresses are then latched on the falling edge of on the rising edge of forced to V

Output Enable (

outputs through the data buffers during a read operation. Block Protect and Block Unprotect operations.

Write Enable (

Command Register and Address and Data latches. Addresses are latched on the falling edge of Data Inputs are latched on the rising edge of

Supply Voltage.

operations (Read, Program and Erase).

Ground.

measurements.

Other

Addresses

V V

E).

Don’t Care 20h Don’t Care E2h

Other

Addresses

The Chip Enable activates the

DQ0 - DQ7

E High deselects the memory and

E while data is latched

E. The Chip Enable must be

during Block Unprotect operations.

The Output Enable gates the

G).

G must be forced to VID level during

This input controls writing to the

W).

W, and

The power supply for all

is the reference for all voltage

4/31

M29F040

Table 6. Instructions

(1,2)

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

(3,7)

RST

RSIG

(4)

Reset

Read Electronic

Read Array/

(4,10)

Signature

RBP

Protection

Read Block

(4)

PG Program 4

BE Block Erase 6

Addr.

Data

Addr.

Data

Addr.

Data

Addr.

Data

Addr.

Data

Addr.

(3,7)

Read Memory Array until a new write cycle is initiated.

F0h

5555h 2AAAh 5555h

Read Memory Array until a new write cycle is initiated.

AAh 55h F0h

5555h 2AAAh 5555h

Read Electronic Signature until a new write cycle is initiated. See Note 5.

AAh 55h 90h

5555h 2AAAh 5555h

Read Block Protection until a new write cycle is initiated. See Note 6.

AAh 55h 90h

5555h 2AAAh 5555h

Program

Address

Read Data Polling or Toggle Bit until Program completes.

AAh 55h A0h

Program

Data

5555h 2AAAh 5555h 5555h 2AAAh

Block

Address

Additional

Block

(8)

Data

Addr.

CE Chip Erase 6

Data

Addr.

Erase Suspend

Data

Addr.

Erase Resume

Data

Notes:

1. Command not interpreted in this table will default to read array mode.

2. While writing any command or duri ng RS G and RSP execution, the P/E.C. can be reset by writing the command 00h to the C.I.

3. X = Don’t Care.

4. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or Electronic Signature codes. Any number of read cycles can occur after one command cycle.

5. Signature Address bits A0, A1, A6 at V Device code.

6. Protection Address: A0, A6 at V status.

7. Address bits A15-A18 are don’t care for coded address inputs.

8. Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.

9. Read Data Polling or Toggle bit until Erase completes.

10. A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase status, before starting any operation.

, A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the Block Protection

AAh 55h 80h AAh 55h 30h 30h

(3,7)

5555h 2AAAh 5555h 5555h 2AAAh 5555h

AAh 55h 80h AAh 55h 10h

(3,7)

Read until Toggle stops, then read all the data needed from any uniform block(s) not being erased then Resume Erase.

B0h

(3,7)

Read Data Polling or Toggle Bit until Erase completes or Erase is suspended another time

30h

will output Manufacturer code (20h). Address bits A0 at VIH and A1, A6 at VIL will output

Note 9

5/31

M29F040

Memory Blocks

The memory blocks of the M29F040 are shown in Figure 3. The memory array is divided in 8 uniform blocks of 64 Kbytes. Each block can be erased separately or any combination of blocks can be erased simultaneously. The Block Erase operation is managed automatically by the P/E.C. The operation can be suspended in order to read from any other block, and then resumed.

Block Protection provides additional data security. Each uniform block can be separately protected or unprotected against Program or Erase. Bringing A9

G to VID initiates protection, while bringing A9,

and G and E to VID cancels the protection. T he block affected during protection is addressed by the inputs on A16, A17, and A18. Unprotect operation affects all blocks.

Operations

Operations are defined as specific bus cycles and signals which allow Memory Read, Command Write, Output Disable, Standby, Read Status Bits, Block Protect/Unprotect, Block Protection Check and Electronic Signature Read. They are shown in Tables 3, 4, 5.

Read.

Read operations are used to output the contents of the Memory Array, the Status Register or the Electronic Signature. Both Chip Enable and Output Enable

G must be low in order to read the output of the memory. The Chip Enable input also provides power control and should be us ed for device selection. Output Enable should be used to gate data onto the output independent of the device selection. The data read depends on the previous command written to the memory (see instructions RST and RSIG, and Status Bits).

Write operations are used to give Instruction

Write.

Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable with Output Enable on the falling edge of

E is Low and Write Enable W is Low

G High. Addresses are latched

W or E whichever occurs last. Commands and Input Data are latched on the rising edge of

Output Disable.

ance when the Output Enable Enable

Standby.

Enable

W or E whichever occurs first.

The data outputs are high imped-

G is High with Write

W High.

The memory is in standby when Chip

E is High and Program/Erase Controller P/E.C. is Idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable Write Enable

Automatic Standby.

W inputs.

After 150ns of inactivity and

G or

when CMOS levels are driving the addresses, the chip automatically enters a pseudo standby mode

where consumption is reduced to the CMOS standby value, while outputs are still driving the bus.

Electronic Signature.

Two codes identifying the manufacturer and the device can be read from the memory, the manufacturer’s code for STMicroelectronics is 20h, and t he device c ode is E2h for the M29F040. These codes allow programming equipment or applications to automatically match their interface to the characteristics of the particular manufacturer’s product. The Electronic Signature is output by a Read op eration when the voltage applied to A9 is at V

and address inputs A1 and

A6 are at Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. This is shown in Table 4.

The Electronic Signature can also be read, without raising A9 to V

by giving the memory the instruc-

tion RSIG (see below).

Block Protection.

Each uniform block can be separately protected against Program or Erase. Block Protection provides additional data security, as it disables all program or erase operations. This mode is activated when both A9 and V

and the block address is applied on A16-A18.

Block Protection is programmed using a Presto F program like algorithm. Protection is initiated on the edge of the edge of

W falling to VIL. Then after a delay of 100µs,

W rising to VIH ends the protection operation. Protection verify is achieved by bringing G, E and A6 to VIL while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A16-A18 is protected. Any att empt to program or erase a protected block will be ignored by the device.

Any protected block can be unprotected to allow updating of bit contents. All blocks must be protected before an unprotect operation. Block Unprotect is activated when A9,

G and E are at VID. The addresses inputs A6, A12, A16 must be maintained at V

. Block Unprotect is performed through

a Presto F Erase like algorithm. Unprotect is initiated by the edge of of 10ms, the edge of

W falling to VIL. After a delay

W rising to VIH will end the unprotection operation. Unprotect verify is achieved by bringing

G and E to VIL while A6 and W are at VIH and A9 at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs on A16-A18 has been successfully unprotected. All combinations of A16A18 must be addressed in order to ensure that all of the 8 uniform blocks have been unprotected. Block Protection Status is shown in Table 5.

G are set to

6/31

Figure 3. Memory Map and Block Address Table

M29F040

A18

AI01362B

A17

1 64K Bytes Block

001

000

A16

Instructions and Commands

The Command Interface ( C.I .) latches commands written to the memory. Instructions are made up from one or more commands to perform Read Array/Reset, Read Electronic Signature, Block Erase, Chip Erase, Program, Block Erase Suspend and Erase Resume. Commands are made of address and data sequences. Addresses are latched on the falling edge of on the rising of

W or E. The instructions require from

W or E and data is latched

1 to 6 cycles, the fi rst or first three of which are always write operations used to initiate the command. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Commands are initialised by two preceding coded cycles which unlock the Command Interface. In addition, for Erase, command confirmation is again preceeded by the two coded cycles.

P/E.C. status is indicated during command execution by Data Polling on DQ7, detection of Toggle on

64K Bytes Block

TOP

ADDRESS

7FFFFh

6FFFFh

5FFFFh

4FFFFh

3FFFFh

2FFFFh

1FFFFh

0FFFFh

BOTTOM

ADDRESS

70000h

60000h

50000h

40000h

30000h

20000h

10000h

00000h

T ab le 7. Commands

Hex Code Command

00h Read 10h Chip Erase Confirm 30h Block Erase Resume/Confirm 80h Set-up Erase

90h

Read Electronic Signature/

Block Protection Status A0h Program B0h Erase Suspend F0h Read Array/Reset

DQ6, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase command execution will automatically output those four bits. The P/E.C. automatically sets bits DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and DQ4) are reserved for future use and should be masked.

7/31

M29F040

Table 8. Status Register

DQ Name Logic Level Definition Note

’1’ Erase Complete

Data

Polling

’0’ Erase on Going DQ Program Complete DQ Program on Going

Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success.

’-1-0-1-0-1-0-1-’ Erase or Program on Going Successive read output complementary

6 Toggle Bit

5 Error Bit

Erase

Time Bit

2 Reserved 1 Reserved 0 Reserved

Note:

Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

’-0-0-0-0-0-0-0-’

’-1-1-1-1-1-1-1-’

Data Po ll ing b it (DQ7 ).

’1’ Program or Erase Error

’0’ Program or Erase on Going

’1’

’0’

’1’ Erase Timeout Period Expired P/E.C. Erase operation has started. Only

’0’

When Programming op-

Program (’0’ on DQ6) Complete

Erase or Program (’1’ on DQ6) Complete

Erase Timeout Period on Going

erations are in pr ogress, this bit outputs t he complement of the bit being programmed on DQ7. During Erase operation, it outputs a ’0’. After completion of the operation, DQ7 will output the bit last programmed or a ’1’ after erasing. Data Polling is valid only effective during P/E.C. operation, that is after the fourth the sixth

W pulse for programming or after

W pulse for Erase. It must be performed at the address being programmed or at an address within the block being erased. If the byte to be programmed belongs to a protected block the command is ignored. If all the blocks selected for erasure are protected, DQ7 will set to ’0’ for about 100µs, and then return to previous addressed memory data. See Figure 9 for the Data Polling flowchart and Figure 10 for the Data Polling waveforms.

Toggle bit (DQ6).

When Programming operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either

G or E when G is low.

data on DQ6 while Programming or Erase operations are going on. DQ6 remain at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged.

This bit is set to ’1’ if P/E.C. has exceded the specified time limits.

possible command entry is Erase Suspend (ES). An additional block to be erased in parallel can be entered to the P/E.C.

The operation is completed when two successive reads yield the same output data. The next read will output the bit las t programmed or a ’1’ after erasing. The toggle bit is valid only effective during P/E.C. operations, that is after the fourth for programming or after the sixth

W pulse

W pulse for Erase. If the byte to be programmed belongs to a protected block the command will be ignored. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then return back to Read. See Figure 11 for Toggle Bit flowchart and Figure 12 for Toggle Bit waveforms.

Error bit (DQ5).

This bit is set to ’1’ by the P/E.C when there is a failure of byte programming, block erase, or chip erase that results in invalid data being programmed in the memory block. In case of error in block erase or byte program, the block in which the error occured or to which the programmed byte belongs, must be discarded. Other blocks may still be used. Error bit resets after Reset (RST) instruction. In case of success, the error bit will set to ’0’ during Program or Erase and to valid data after write operation is completed.

8/31

Table 9. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times Input Pulse Voltages 0 to 3V 0.45V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

10ns

≤

10ns

≤

M29F040

Figure 4. AC Testing Input Output Waveform

High Speed

1.5V

Standard

2.4V

0.45V

(1)

Table 10. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

Note:

1. Sampled only, not 100% tested.

Input Capacitance VIN = 0V 6 pF Output Capacitance V

(TA = 25 °C, f = 1 MHz )

2.0V

0.8V

AI01275B

Figure 5. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance

= 0V 12 pF

OUT

AI01276B

Erase Timer bit (DQ3).

This bit is set to ’0’ by the P/E.C. when the last Block Erase command has been entered to t he Command Interface and it is awaiting the Erase start. When the wait period is finished, after 80 to 120µs, DQ3 returns back to ’1’.

Coded Cycles.

The two coded cycles unlock the Command Interface. They are f ollowed by a c ommand input or a comand confirmation. The coded cycles consist of writing the data AAh at address 5555h during the first cycle and data 55h at address 2AAAh during the second cycle. Addresses are latched on the falling edge of latched on the rising edge of

W or E while data is

W or E. The coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles.

Read Array/Reset (RST) instruction.

The Reset instruction consists of one write operation gi ving the command F0h. It can be optionally preceded by the two coded cycles. A wait state of 5µs before read operations is necessary if the Reset command is applied during an Erase operation.

Read Electronic Signature (RSIG) i nstruction.

This instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 5555h for command setup. A subsequent read will output the manufacturer code, the device code or the Block Protection status depending on the levels of A0, A1, A6, A16, A17 and A18. The manufacturer code, 20h, is output when the addresses lines A0, A1 and A6 are Low, the device code, E2h is output when A0 is High wit h A1 and A6 Low.

9/31

M29F040

Table 11. DC Characteristics

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%)

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

CC3

CC4

Input Leakage Current 0V ≤ VIN ≤ V

Output Leakage Current 0V ≤ V Supply Current (Read) E = VIL, G = VIH, f = 6MHz 15 mA Supply Current (Standby) TTL E = V Supply Current (Standby) CMOS E = VCC ± 0.2V 50

Supply Current (Program or Erase)

Byte Program,

Block Erase

OUT

≤ V

1mA

20 mA

CC5

LKO

Read Block Protection (RBP) instruction.

Supply Current Chip Erase in progress 40 mA Input Low Voltage –0.5 0.8 V

Input High Voltage 2 VCC + 0.5 V

Output Low Voltage IOL = 10mA 0.45 V

Output High Voltage TTL IOH = –2.5mA 2.4 V

Output High Voltage CMOS

A9 Voltage (Electronic Signature) 11.5 12.5 V

A9 Current (Electronic Signature) A9 = V

Supply Voltage (Erase and Program lock-out)

The use of Read Electronic Signature (RSIG) command also allows access to the Block Protection status verify. After giving the RSIG command, A0 and A6 are set to V

with A1 at VIH, while A16, A17 and

A18 define the block of the block to be verified. A read in these conditions will output a 01h if block is protected and a 00h if block is not protected.

This Read Block Protection is the only valid way to check the protection statu s of a block. Nevertheless, it must not be used during the Block Protection phase as a method to verify the block protection. Please refer to Block Protection paragraph.

Chip Erase (CE) instruction.

This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Chip Erase Conf irm com-

= –100µAV

= –2.5mA 0.85 V

–0.4 V

3.2 4.2 V

mand 10h is written at address 5555h on sixth cycle after another two coded cycles. If the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to Read Array . It is not necess ary to program the array with 00h f irst as the P/E.C. will automatically do this before erasing to FFh. Read operations after the sixth rising edge of output the status register bits. During the execution of the erase by the P/E.C. the memory accepts only the Reset (RST) command. Read of Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The T oggle Bit DQ6 toggles dur ing erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because the erasure has not been verified even after the maximum number of erase cycles have been executed.

W or E

10/31

M29F040

Table 12A. Read AC Characteristics

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

(3)

-70 -90

Symbol Alt Parameter Test Condition

VCC = 5V ± 5% VCC = 5V ± 10%

Standard

Interface

Min Max Min Max

AVAV

AVQV

ELQX

ELQV

GLQX

GLQV

EHQX

EHQZ

GHQX

GHQZ

AXQX

Notes:

Address Valid to Next Address Valid E = VIL, G = V

Address Valid to Output Valid E = VIL, G = V

ACC

(1)

tLZChip Enable Low to Output Transition G = V

(2)

tCEChip Enable Low to Output Valid G = V

(1)

(2)

(1)

1. Sampled only, not 100% tested. G may be delayed by up to t

3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and V

Output Enable Low to Output

OLZ

Transition

Output Enable Low to Output Valid E = V

Chip Enable High to Output

Transition

tHZChip Enable High to Output Hi-Z G = V

Output Enable High to Output

Transition

tDFOutput Enable High to Output Hi-Z E = V

Address Transition to Output

Transition

ELQV

- t

after the falling edge of E wit hout increasing t

GLQV

E = VIL, G = V

E = V

G = V

E = V

70 90 ns

00ns

20 20 ns

ELQV

M29F040

Standard

Interface

70 90 ns

30 35 ns

20 20 ns

= 5V ± 5%.

Unit

Block Erase (BE) instruction

. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. T he Block Erase Confirm command 30h is written on sixth cycle after another two coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional Block Erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further coded cycles. The erase will start after an Erase timeout period of about 100µs. Thus, additional Block Erase commands must be given within this delay. The input of a new Block Erase command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C

is erasing the block(s). Before and during Erase timeout, any command different from 30h will abort the instruction and reset the device t o read array mode. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations after the sixth rising edge of

W or E output the status register bits.

During the execution of the erase by the P/E.C., the memory accepts only the ES (Erase Suspend) and RST (Reset) instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The T oggle Bit DQ6 toggles during the erase operation. I t stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because erasure has not completed even after the maximum number of erase cycles have been executed. In this case, it will be necessary to input a Reset (RST) to the command interface in order to reset the P/E.C.

11/31

M29F040

Table 12B. Read AC Characteristics

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Symbol Alt Parameter Test Condition

M29F040

-120 -150

VCC = 5V ± 10% VCC = 5V ± 10%

Unit

AVAV

AVQV

ELQX

ELQV

GLQX

GLQV

EHQX

EHQZ

GHQX

GHQZ

AXQX

Notes:

Address Valid to Next Address Valid E = VIL, G = V

Address Valid to Output Valid E = VIL, G = V

ACC

(1)

tLZChip Enable Low to Output Transition G = V

(2)

tCEChip Enable Low to Output Valid G = V

(1)

(2)

(1)

1. Sampled only, not 100% tested. G may be delayed by up to t

Output Enable Low to Output

OLZ

Transition

Output Enable Low to Output Valid E = V

Chip Enable High to Output

Transition

tHZChip Enable High to Output Hi-Z G = V

Output Enable High to Output

Transition

tDFOutput Enable High to Output Hi-Z E = V

Address Transition to Output

Transition

ELQV

E = V

G = V

E = V

E = VIL, G = V

- t

after the falling edge of E wit hout increasing t

GLQV

Standard

Interface

Standard

Interface

Min Max Min Max

120 150 ns

00ns

20 20 ns

120 150 ns

50 55 ns

30 35 ns

ELQV

Program (PG) instruction.

The memory can be programmed Byte-by-Byte. This instruction uses four write cycles. The Program command A0h is written on the third cycle after two coded cycles. A fourth write operation latches the Address on the falling edge of

W or E and the Data t o be written on its rising edge and starts the P/E.C. During the execution of the program by the P/E.C., the memory will not accept any instruction. Read operations output the status bits after the programming has started. The status bits DQ5, DQ6 and DQ7 allow a check of the status of the programming operation. Memory programming is made only by writing ’0’ in place of ’1’ in a Byte.

Erase Suspend (ES) instruction.

The Block Erase operation may be suspended by this instruction which consists of writing the command 0B0h without any specific address code. No coded cycles are required. It allows reading of data from another

12/31

block while erase is in progress. Erase suspend is accepted only during the B lock Erase instruction execution and defaults to read array mode. W riting this command during Erase timeout will, in addition to suspending the erase, terminate the timeout. The T oggle Bit DQ6 stops toggling when the P/E.C. is suspended. T oggle Bit status must be monitored at an address out of the block being erased. T oggle Bit will stop toggling between 0.1µs and 15µs after the Erase Suspend (ES) command has been written.

The M29F040 will then automatically set to Read Memory Array mode. When erase is suspended, Read from blocks being erased will output invalid data, Read from block not being erased is valid. During the suspension the memory will respond only to Erase Resume (ER) and Reset (RST) instructions. RST command will definitively abort erasure and result in the invalid data in the blocks being erased.

Figure 6. Read Mode AC Waveforms

tEHQZ

tEHQX

tGHQX

M29F040

AI01363B

tGHQZ

VALID

tAVAV

VALID

A0-A18

tAVQV tAXQX

tELQV

tGLQV

tGLQX

tELQX

DQ0-DQ7

OUTPUT ENABLE DATA VALID

ADDRESS VALID

AND CHIP ENABLE

W) = High

Write Enable (

Note:

13/31

M29F040

Table 13A. Write AC Characteristics, Write Enable Controlled

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Symbol Alt Parameter

(2)

VCC = 5V ± 10% VCC = 5V ± 10%

Min Max Min Max

t t

ELWL

WLWH

DVWH

WHDX

WHEH

WHWL

AVWL

WLAX

GHWL

VCHEL

WHQV1

WHQV2

AVAV

Address Valid to Next Address Valid 70 90 ns

tCSChip Enable Low to Write Enable Low 0 0 ns

Write Enable Low to Write Enable High 35 45 ns

tDSInput Valid to Write Enable High 30 45 ns t

Write Enable High to Input Transition 0 0 ns

Write Enable High to Chip Enable High 0 0 ns

Write Enable High to Write Enable Low 20 20 ns

WPH

Address Valid to Write Enable Low 0 0 ns

Write Enable Low to Address Transition 45 45 ns

Output Enable High to Write Enable Low 0 0 ns

(1)

VCSVCC

High to Chip Enable Low 50 50 Write Enable High to Output Valid (Program) 10 10 Write Enable High to Output Valid

(Block Erase)

1.0 30 1.0 30 sec

M29F040

-70 -90

Standard

Interface

Standard

Interface

Unit

WHGL

Note:

1. Time is measured to Data Polling or Toggle Bit, t

2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.

Erase Resume (ER) instruction.

pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any addr ess, and without any coded cycles.

Power Up

The memory Command Interface is reset on power up to Read Array . Either during Power-up to allow maximum security and

Write Enable High to Output Enable Low 0 0 ns

OEH

= t

WHQ7V

+ t

Q7VQV

adge of when V

E or W. Any write cycle initiation is blocked

is below V

LKO

WHQV

If an Erase Sus-

Supply Rails

Normal precautions must be taken for supply voltage decoupling, each device in a system should

rail decoupled with a 1.0µF capacitor

and VSS pins. The PCB trace

E or W must be tied to V

have the V close to the V widths should be sufficient to carry the V

gram and erase currents required.

the possibility to write a command on the first rising

pro-

14/31

M29F040

Table 13B. Write AC Characteristics, Write Enable Controlled

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Symbol Alt Parameter

t t

ELWL

WLWH

DVWH

WHDX

WHEH

WHWL

AVWL

WLAX

GHWL

VCHEL

WHQV1

WHQV2

AVAV

(1)

Address Valid to Next Address Valid 120 150 ns

Chip Enable Low to Write Enable Low 0 0 ns

Write Enable Low to Write Enable High 50 50 ns

Input Valid to Write Enable High 50 50 ns

Write Enable High to Input Transition 0 0 ns

Write Enable High to Chip Enable High 0 0 ns

Write Enable High to Write Enable Low 20 20 ns

WPH

Address Valid to Write Enable Low 0 0 ns

Write Enable Low to Address Transition 50 50 ns

Output Enable High to Write Enable Low 0 0 ns

VCSVCC

High to Chip Enable Low 50 50 Write Enable High to Output Valid (Program) 10 10 Write Enable High to Output Valid

(Block Erase)

VCC = 5V ± 10% VCC = 5V ± 10%

Min Max Min Max

1.0 30 1.0 30 sec

M29F040

-120 -150

Standard

Interface

Standard

Interface

Unit

WHGL

Note:

1. Time is measured to Data Polling or Toggle Bit, t

Write Enable High to Output Enable Low 0 0 ns

OEH

WHQV

= t

WHQ7V

+ t

Q7VQV

15/31

M29F040

Figure 7. Write AC Waveforms, W Controlled

WRITE CYCLE

A0-A18

DQ0-DQ7

Note:

Address are latched on the falling edge of

tVCHEL

VALID

tAVWL

tELWL

tWLWHtGHWL

W, Data is latched on the rising edge of W.

tDVWH

tWLAX

tWHEH

tWHGL

tWHWL

tWHDX

VALID

AI01365B

16/31

M29F040

Table 14A. Write AC Characteristics, Chip Enable Controlled

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Symbol Alt Parameter

WLEL

ELEH

DVEH

EHDX

EHWH

EHEL

t t t

GHEL

VCHWL

EHQV1

EHQV2

AVAV

AVEL

ELAX

Address Valid to Next Address Valid 70 90 ns

Write Enable Low to Chip Enable Low 0 0 ns

Chip Enable Low to Chip Enable High 35 45 ns

Input Valid to Chip Enable High 30 45 ns

Chip Enable High to Input Transition 0 0 ns

Chip Enable High to Write Enable High 0 0 ns

Chip Enable High to Chip Enable Low 20 20 ns

CPH

Address Valid to Chip Enable Low 0 0 ns

Chip Enable Low to Address Transition 45 45 ns

Output Enable High Chip Enable Low 0 0 ns

(1)

VCC High to Write Enable Low 50 50

VCS

Chip Enable High to Output Valid (Program) 10 10 Chip Enable High to Output Valid

(Block Erase)

(2)

VCC = 5V ± 10% VCC = 5V ± 10%

M29F040

-70 -90 Unit

Standard Interface

Min M ax Min Max

1.0301.030sec

Standard

Interface

EHGL

Note:

1. Time is measured to Data Polling or Toggle Bit, t

2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and V

OEH

Chip Enable High to Output Enable Low 0 0 ns

= t

+ t

WHQV

WHQ7V

Q7VQV

= 5V ± 5%.

17/31

M29F040

Table 14B. Write AC Characteristics, Chip Enable Controlled

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Symbol Alt Parameter

WLEL

ELEH

DVEH

EHDX

EHWH

EHEL

t t t

GHEL

VCHWL

EHQV1

EHQV2

AVAV

AVEL

ELAX

Address Valid to Next Address Valid 120 150 ns

Write Enable Low to Chip Enable Low 0 0 ns

Chip Enable Low to Chip Enable High 50 50 ns

Input Valid to Chip Enable High 50 50 ns

Chip Enable High to Input Transition 0 0 ns

Chip Enable High to Write Enable High 0 0 ns

Chip Enable High to Chip Enable Low 20 20 ns

CPH

Address Valid to Chip Enable Low 0 0 ns

Chip Enable Low to Address Transition 50 50 ns

Output Enable High Chip Enable Low 0 0 ns

(1)

VCC High to Write Enable Low 50 50

VCS

Chip Enable High to Output Valid (Program) 10 10 Chip Enable High to Output Valid

(Block Erase)

VCC = 5V ± 10% VCC = 5V ± 10%

M29F040

-120 -150 Unit

Standard Interface

Min Max Min Max

1.0 30 1.0 30 sec

Standard

Interface

µ µ

s s

EHGL

Note:

1. Time is measured to Data Polling or Toggle Bit, t

OEH

Chip Enable High to Output Enable Low 0 0 ns

WHQV

= t

WHQ7V

+ t

Q7VQV

18/31

Figure 8. Write AC Waveforms, E Controlled

M29F040

WRITE CYCLE

A0-A18

DQ0-DQ7

tVCHWL

Note:

Address are latched on the falling edge of

VALID

tAVEL

tWLEL

E, Data is latched on the rising edge of E.

tELEHtGHEL

tDVEH

tELAX

tEHWH

tEHGL

tEHEL

tEHDX

VALID

AI01366B

19/31

M29F040

Table 15A. Data Polling and Toggle Bit AC Characteristics

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Symbol Parameter

(3)

VCC = 5V ± 10% VCC = 5V ± 10%

(1)

M29F040

-70 -90 Unit

Standard

Interface

Min Max Min Max

Write Enable High to DQ7 Valid

Notes:

(2)

WHQ7V1

WHQ7V2

EHQ7V1

EHQ7V2

Q7VQV

WHQV1

WHQV2

EHQV1

EHQV2

1. All other timings are defined in Read AC Characteri st i cs table .

2. t

3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and V

(Program, Write Enable High to DQ7 Valid

(2)

(Block Erase, Chip Enable High to DQ7 Valid

(2)

(Program, Chip Enable High to DQ7 Valid

(2)

(Block Erase, Q7 Valid to Output Valid (Data Polling) 30 35 ns Write Enable High to Output Valid

(Program) Write Enable High to Output Valid

(Block Erase) Chip Enable High to Output Valid

(Program) Chip Enable High to Output Valid

(Block Erase)

is the Program or Erase time.

WHQ7V

W Controlled)

E Controlled)

10 10

1.0 30 1.0 30 sec

10 10

1.0 30 1.0 30 sec

10 10

1.0 30 1.0 30 sec

10 10

1.0 30 1.0 30 sec

Standard

Interface

= 5V ± 5%.

20/31

Table 15B. Data Polling and Toggle Bit AC Characteristics

= 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)

Symbol Parameter

Write Enable High to DQ7 Valid

WHQ7V1

WHQ7V2

EHQ7V1

EHQ7V2

Q7VQV

WHQV1

(2)

(Program, Write Enable High to DQ7 Valid

(2)

(Block Erase, Chip Enable High to DQ7 Valid

(2)

(Program, Chip Enable High to DQ7 Valid

(2)

(Block Erase,

W Controlled)

E Controlled)

E Controlled) Q7 Valid to Output Valid (Data Polling) 50 55 ns Write Enable High to Output Valid

(Program)

= 5V ± 10% VCC = 5V ± 10%

Standard

Interface

Min Max Min Max

10 10

1.0 30 1.0 30 sec

10 10

1.0 30 1.0 30 sec

10 10

(1)

M29F040

-120 150

Standard

Interface

M29F040

Unit

WHQV2

EHQV1

EHQV2

Notes:

1. All other timings are defined in Read AC Characteri st i cs table .

2. t

Write Enable High to Output Valid (Block Erase)

Chip Enable High to Output Valid (Program)

Chip Enable High to Output Valid (Block Erase)

is the Program or Erase time.

WHQ7V

1.0 30 1.0 30 sec

10 10

1.0 30 1.0 30 sec

21/31

M29F040

Figure 9. Data Polling DQ7 AC Waveforms

AI01364B

READ CYCLE

DATA OUTPUT VALID

BYTE ADDRESS (WITHIN BLOCKS)

tELQV

tAVQV

tEHQ7V

tGLQV

VALID

DQ7

tWHQ7V

VALID

tQ7VQV

IGNORE

DATA POLLING (LAST) CYCLE DATA VERIFY

READ CYCLES

DATA POLLING

22/31

A0-A18

OR ERASE

LAST CYCLE

OF PROGRAM

DQ7

DQ0-DQ6

1. All other timings are as a normal Read cycle.

2. DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period.

3. tWHQ7V is the Program or Erase time.

4. During erasing operation Byte address must be within Block being erased.

Notes:

M29F040

Figure 10. Data Polling Flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

YES

DATA

DQ5

= 1

YES

READ DQ7

DQ7

YES

DATA

Figure 11. Data Toggle Flowchart

START

READ

DQ5 & DQ6

READ DQ6

DQ6

TOGGLE

DQ5

= 1

DQ6

TOGGLE

YES

FAIL PASS

AI01369

FAIL PASS

AI01370

Table 16. Program, Erase Times and Program, Erase Endurance Cycles

= 0 to 70°C; VCC = 5V ± 10% or 5V ± 5%)

Parameter

Min Typ Max

Chip Program (Byte) 6 sec Chip Erase (Preprogrammed) 2.5 30 sec Chip Erase 8.5 sec Block Erase (Preprogrammed) 1 30 sec Block Erase 1.5 sec Byte Program 10 1500 Program/Erase Cycles (per Block) 100,000 cycles

M29F040

Unit

23/31

M29F040

Figure 12. Data Toggle DQ6 AC Waveforms

AI01367

VALID

tEHQV

tAVQV

tELQV

tGLQV

VALID

tWHQV

STOP TOGGLE

VALID

IGNORE

READ CYCLE

DATA TOGGLE

24/31

A0-A18

DATA

TOGGLE

READ CYCLE

OF ERASE

LAST CYCLE

OF PROGRAM

DQ6

DQ0-DQ5,

DQ7

All other timings are as a normal Read cycle.

Note:

Figure 13. Block Protection Flowchart

BLOCK ADDRESS

on A16, A17, A18

START

n = 0

G, A9 = VID,

E = V

Wait 4µs

W = V

Wait 100µs

M29F040

W = V

G = V

Wait 4µs

READ DQ0 at PROTECTION

ADDRESS: A0, A6 = VIL, A1 = VIH and

A16, A17, A18 DEFINING BLOCK

DQ0

= 1

YES

A9 = V

PASS

++n

= 25

A9 = V

FAIL

YES

AI01368D

25/31

M29F040

Figure 14. Block Unprotecting Flowchart

START

PROTECT

ALL BLOCKS

n = 0

A6, A12, A16 = V

E, G, A9 = V

Wait 4µs

E, G, A9 = V

Wait 4µs

W = V

Wait 10ms

W = V

E, G = V

Wait 4µs

READ at UNPROTECTION

ADDRESS: A1, A6 = VIH, A0 = V

A16, A17, A18 DEFINING BLOCK

(see Note 1)

and

INCREMENT

BLOCK

Note:

26/31

NO LAST

1. A6 is kept at V reads, A6 must be kept at V

during unprotection algorithm in order to secure best unprotection verification. During all other protection status

++n

= 1000

FAIL

YES

DATA

00h

YESNO

SECT.

YES

PASS

AI01371E

ORDERING INFORMATION SCHEME

Example: M29F040 -70 X N 1 TR

M29F040

Operating Voltage

F5V

Speed

-70 70ns

-90 90ns

-120 120ns

-150 150ns

Power Supplies

blank V

CC CC

± ±

10% 5%

Package

K PLCC32 N TSOP32

8 x 20mm

M29F040 is replaced by the new version M29F040B

Device are shipped from the factory with the memory content erased (to FFh).

Option

R Reverse Pinout

TR Tape & Reel

Packing

Temp. Range

1 0 to 70 °C 3 –40 to 125 °C 5 –20 to 85 °C 6 –40 to 85 °C

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.

27/31

M29F040

PLCC32 - 32 l ead Plastic Leaded Chip Ca rr ier , rectangula r

Symb

Typ Min Max Typ Min Max

A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015

B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430

E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530

e 1.27 – – 0.050 – –

F 0.00 0.25 0.000 0.010

R 0.89 – – 0.035 – –

N32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004

mm inches

Drawing is not to scale.

28/31

PLCC

1 N

E1 E

0.51 (.020)

1.14 (.045)

D2/E2

M29F040

TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm

Symb

Typ Min Max Typ Min Max

A 1.20 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041

B 0.15 0.27 0.006 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728

E 7.90 8.10 0.311 0.319

e 0.50 - - 0.020 - -

L 0.50 0.70 0.020 0.028

N32 32 CP 0.10 0.004

mm inches

Drawing is not to scale.

TSOP-a

N/2

DIE

LA1 α

29/31

M29F040

TSOP32 Rev e rse Pinout - 32 lead Plasti c Thin Small Out l ine, 8 x 20mm

Symb

Typ Min Max Typ Min Max

A 1.20 0.047 A1 0.05 0.17 0.002 0.006 A2 0.95 1.05 0.037 0.041

B 0.15 0.27 0.006 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728

E 7.90 8.10 0.311 0.319

e 0.50 – – 0.020 – –

L 0.50 0.70 0.020 0.028

N32 32 CP 0.10 0.004

mm inches

Drawing is not to scale.

1 N

N/2

DIE

TSOP-b

LA1 α

30/31

M29F040

Information furnished is bel i eved to be accurate and reliable . However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notic e. This publication super sedes and replaces all informatio n previously supplied. STMic roelectronics product s are not authorized for use as critical com ponent s in life suppo rt devic es or systems without express written approval of STMicroelectroni cs.

The ST logo is a registered trademark of STMicroelectronics

All other names are the property of their respective owners.

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