查询M29F016B55M1T供应商
16 Mbit (2Mb x8, Uniform Block) Single Supply Flash Memory
■ SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 55ns
■ PROGRAMMING TIME
–8µs by Byte typical
■ 32 UNIFORM 64 Kbyte MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: ADh
TSOP40 (N)
10 x 20mm
Figure 1. Logic Diagram
V
CC
21
A0-A20
W
E
G
RP
M29F016B
M29F016B
44
1
SO44 (M)
8
DQ0-DQ7
RB
V
SS
AI02964
1/22March 2000
M29F016B
Figure 2. TSOP Connections
A19
A18
A17
A16 G
A15
A14
A13
A12
V
CC
NC
RP
A11
1
E
10
11
A9
A8
A7
A6
A5
A4
20 21
M29F016B
40
31
30
AI02969
A20
NC
W
RB
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2A10
DQ1
DQ0
A0
A1
A2
A3
Figure 3. SO Connections
NC
RP
A11 A12
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ1
DQ3
V
SS
V
SS
1
2
3
4
5
6
7
8
9
10
11
M29F016B
12
13
14
15
16
17DQ0
18
19
20
21
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322
AI02965
V
CC
E
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
NC
W
G
RB
DQ7
DQ6DQ2
DQ5
DQ4
V
CC
Table 1. Signal Names
A0-A20 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
V
CC
V
SS
NC Not Connected Internally
Supply Voltage
Ground
2/22
M29F016B
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
V
ID
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions forextended periods mayaffect device reliability. Referalso to theSTMicroelectronics SURE Program and other relevantquality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage –0.6 to 6 V
Supply Voltage –0.6 to 6 V
Identification Voltage –0.6 to 13.5 V
SUMMARY DESCRIPTION
The M29F016B is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and reprogrammed. These operations can be performedusing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected in groups to prevent accidental Program
or Erase commands from modifying the memory.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
(1)
programming or erasing the memory by taking
care of all of the special operations that are required to update the memory contents. The end of
a program or eraseoperation can be detected and
any error conditions identified. The command set
required to control the memory is consistent with
JEDEC standards.
Chip Enable, Output Enableand Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in a TSOP40 (10 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
Program/Erase Controllersimplifies the process of
3/22
M29F016B
Table 3. Uniform Block Addresses, M29F016B
Size
#
(Kbytes)
31 64 1F0000h-1FFFFFh
30 64 1E0000h-1EFFFFh
29 64 1D0000h-1DFFFFh
28 64 1C0000h-1CFFFFh
27 64 1B0000h-1BFFFFh
26 64 1A0000h-1AFFFFh
25 64 190000h-19FFFFh
24 64 180000h-18FFFFh
23 64 170000h-17FFFFh
22 64 160000h-16FFFFh
21 64 150000h-15FFFFh
20 64 140000h-14FFFFh
19 64 130000h-13FFFFh
18 64 120000h-12FFFFh
17 64 110000h-11FFFFh
16 64 100000h-10FFFFh
15 64 0F0000h-0FFFFFh
14 64 0E0000h-0EFFFFh
13 64 0D0000h-0DFFFFh
12 64 0C0000h-0CFFFFh
11 64 0B0000h-0BFFFFh
10 64 0A0000h-0AFFFFh
9 64 090000h-09FFFFh
8 64 080000h-08FFFFh
7 64 070000h-07FFFFh
6 64 060000h-06FFFFh
5 64 050000h-05FFFFh
4 64 040000h-04FFFFh
3 64 030000h-03FFFFh
2 64 020000h-02FFFFh
1 64 010000h-01FFFFh
0 64 000000h-00FFFFh
Address Range
Protection
Group
7
6
5
4
3
2
1
0
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for abrief overview of the signals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output thedatastoredattheselected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sentto theCommandInterfaceoftheinternalstate
machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Writeoperations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W,controls
the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect(RP). The Reset/Block Temporary Unprotect pin can be usedto
apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
t
. After Reset/Block Temporary Unprotect
PLPX
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after t
t
, whicheveroccurs last. See the Ready/Busy
RHEL
PHEL
or
Output section, Table 14 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at VIDwill temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIHtoVIDmustbe slower than
t
PHPHH
.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that canbeusedto identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
4/22
M29F016B
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 14 and Figure
11, Reset/Temporary Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows theReady/
Busy pinsfrom several memories to be connected
to asinglepull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
VCCSupply Voltage. The VCCSupply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The CommandInterface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasingduring
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCCSupply Voltage pin and the VSSGround
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
VSSGround. TheVSSGroundisthereference for
all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable,Standby and Automatic Standby. See
Table 4, Bus Operations,for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect busoperations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired addresson the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or WriteEnable,whichever occursfirst.OutputEnable must remain High, VIH, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at VIHthe Supply Current is
reduced to the TTLStandby Supply Current, I
CC2
To further reduce the Supply Current to the CMOS
Standby Supply Current, I
, Chip Enableshould
CC3
be held within VCC± 0.2V. For Standby current
levels see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, forProgramorEraseoperations un-
CC4
til the operation completes.
.
Table 4. Bus Operations
Operation E G W Address Inputs
Bus Read
Bus Write
Output Disable X V
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VILor VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
Data
Inputs/Outpu ts
V
IL
V
IH
IH
XXX Hi-Z
V
IL
V
IL
V
V
V
V
V
Cell Address Data Output
IH
Command Address Data Input
IL
XHi-Z
IH
A0 = VIL,A1=VIL,A9=VID,
IH
Others V
A0 = VIH,A1=VIL,A9=VID,
IH
Others V
or V
IL
or V
IL
IH
IH
20h
ADh
5/22
M29F016B
AutomaticStandby. IfCMOSlevels (VCC± 0.2V)
are usedto drive the busand the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC3
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VIDto be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 4, Bus Operations.
Block Protection and Blocks Unprotec tion. Blocks
can beprotectedin groups against accidental Program or Erase. See Table 3, Block Addresses, for
details ofwhich blocks must be protected together
as a group. Protected blocks can be unprotected
to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failureto observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The longcommand sequences
are imposed to maximize data security.
The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the
text descriptions below.
Read/Reset Command. The Read/Reset command returnsthememory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Eraseoperationor following a Programming
or Eraseerrorthenthe memory will take upto 10µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VILandA1 = VIL. The other address bits
may be set to either VILor VIH. The Manufacturer
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = VIHand A1 = VIL. The other
address bits may be set to either VILor VIH. The
Device Code for the M29F016B is ADh.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A16-A20 specifying the address of
the block. The other address bits may be set to either VILor VIH. If the addressed block is protected
then 01his outputon the Data Inputs/Outputs, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires fourBus Write operations,the final write operation latches theaddress and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause theoperation. Typical
program times are given in Table 6. BusRead operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must beissued to reset the error condition and return to Read mode.
Note that the Program command cannotchange a
bit set at ’0’ back to ’1. One of the Erase Commands must be used to set all the bits in ablock or
in the whole memory from ’0’ to ’1’.
6/22
M29F016B
Table 5. Commands
Bus Write Operations
Command
Read/Reset
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory asnormal until another command is issued.
Erase Suspend. After the EraseSuspend command readnon-erasing memory blocksasnormal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
1X F0
3 555 AA 2AA 55 X F0
2X A0PAPD
1st 2nd 3rd 4th 5th 6th
Length
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Programcommandtoprogram the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass
Reset command. The memory can be readas if in
Read mode.
Unlock Bypass Program Command. The Unlock
Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final
write operation latches the address and datainthe
internal state machine and starts the Program/
Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be programmed; the operation cannot be abortedand theStatusRegister is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock Bypass Mode. See theProgram command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
TwoBus Write operationsarerequiredtoissuethe
Unlock Bypass Reset command.
7/22
M29F016B
Chip Erase Command. The Chip Erase com-
mand can be usedto erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears tostart but will terminate withinabout100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. ARead/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets allof the bits in unprotected blocksof the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase command can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controllerabout 50µs after the
last Bus Writeoperation. Oncethe Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs ofthe last block. The50µs
timer restartswhen an additional block isselected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected thentheseare
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged.No error condition is givenwhen protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 6. All Bus Read operations during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completedthe
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must beissued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Parameter Min
Chip Erase (All bits in the memory set to ‘0’) 6 6 sec
Chip Erase 16 16 70 sec
Block Erase (64 Kbytes) 0.6 0.6 4 sec
Program 8 8 150 µs
Chip Program 18 18 70 sec
Program/Erase Cycles (per Block) 100,000 cycles
Note: 1. TA=25°C, VCC=5V.
8/22
Typ
(1)
Typical after
100k W/E Cycles
(1)
Max Unit
M29F016B
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erasewillbesuspended. Ifthe Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start immediately when the Erase Resume Command is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased will output the Status Register. It
is also possible to enter theAuto Select mode: the
memorywill behave as in the Auto Selectmode on
all blocks until a Read/Reset command returns the
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
9/22
M29F016B
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It isalso read during Erase Suspend when an address withinablock beingerased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and BusRead operationsfromtheaddress just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. Aftersuccessful completion of the Erase operation the memory returns to Read mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change froma ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if ithas responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within ablock being
erased. The Toggle Bit will stoptoggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannotchange a
bit set at ’0’ back to ’1’ and attempting to do so,
may or may not set DQ5 at ‘1’. In both cases, a
successive Bus Read operation will show the bit is
still ‘0’. One of the Erase commands must be used
to set all thebits in a block or in the whole memory
from ’0’ to ’1’.
Table 7. Status Register Bits
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During Erase
Suspend
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout
Block Erase
Erase Suspend
Erase Error
Note: Unspecified data bits should be ignored.
10/22
Any Address DQ7 Toggle 0 – – 0
Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erasing Block 1 No Toggle 0 – Toggle 1
Non-Erasing Block Data read as normal 1
Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
M29F016B
Figure 4. Data Polling Flowchart
START
READ DQ5 &
at VALID ADDRESS
NO
READ
at VALID ADDRESS
DQ7
DQ7
YES
=
DATA
NO
DQ5
=1
YES
DQ7
DQ7
YES
=
DATA
NO
FAIL PASS
AI03598
Figure 5. Data Toggle Flowchart
START
READ
DQ5 & DQ6
READ DQ6
DQ6
=
TOGGLE
NO
DQ5
=1
READ
TWICE
DQ6
=
TOGGLE
FAIL PASS
YES
YES
DQ6
YES
NO
NO
AI01370B
Erase Timer Bit(DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command.
Once the Program/Erase Controller starts erasing
the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts theEraseTimerBit is
set to ’0’ and additional blocks to be erased may
be written to the Command Interface. The Erase
Timer Bit is output on DQ3 when the Status Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Eraseoperations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within theblocksbeingerased. Oncetheoperation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative ToggleBit canbe used to
identify whichblock or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change ifthe addressed block has erased correctly.
11/22
M29F016B
Table 8. AC Measurement Conditions
Parameter
55 / 70 90
ACTestConditions High Speed Standard
M29F016B
Load Capacitance (C
) 30pF 100pF
L
Input Rise and Fall Times ≤ 10ns ≤ 10ns
Input Pulse Voltages 0 to 3V 0.45 to 2.4V
Input and Output Timing Ref.Voltages 1.5V 0.8V and 2.0V
Figure 6. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.45V
2.0V
0.8V
AI01275B
Figure 7. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL= 30pF or 100pF
CLincludes JIG capacitance
OUT
AI03027
Table 9. Capacitance
(TA=25°C, f = 1 MHz)
Symbol Parameter Test Condition Min Max Unit
V
V
OUT
IN
=0V
=0V
6pF
12 pF
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance
12/22
M29F016B
Table 10. DC Characteristics
(TA= 0 to 70°C, –40 to 85°C or –40 to 125°C)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC4
V
V
V
OL
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
(1)
Supply Current (Program/Erase)
Input Low Voltage –0.5 0.8 V
IL
Input High Voltage 2
IH
Output Low Voltage
Output High Voltage TTL
V
OH
V
I
ID
V
LKO
Note: 1. Sampled only, not 100% tested.
Output High Voltage CMOS
Identification Voltage 11.5 12.5 V
ID
Identification Current
Program/Erase Lockout Supply
(1)
Voltage
0V ≤ V
0V ≤ V
E=V
,G=VIH, f = 6MHz
IL
E=V
E=V
RP = V
Program/Erase
Controller active
I
OL
I
OH
I
OH
A9 = V
≤ V
IN
CC
≤ V
OUT
CC
IH
± 0.2V,
CC
±0.2V
CC
= 5.8mA
= –2.5mA
= –100µAV
ID
2.4 V
–0.4
CC
3.2 4.2 V
±1 µA
±1 µA
20 mA
2mA
800 µA
20 mA
V
+ 0.5
CC
0.45 V
100 µA
V
V
13/22
M29F016B
Table 11. Read AC Characteristics
(TA = 0to 70°C, –40 to 85°C or –40 to 125°C)
Symbol Alt Parameter Test Condition
E=V
,
t
AVAV
t
AVQV
(1)
t
ELQX
t
ELQV
(1)
t
GLQX
t
GLQV
(1)
t
EHQZ
(1)
t
GHQZ
t
EHQX
t
GHQX
t
AXQX
Note: 1. Sampled only, not 100% tested.
t
t
ACC
t
t
t
OLZ
t
t
t
t
Address Validto Next Address Valid
RC
Address Validto Output Valid
Chip Enable Low to Output
LZ
Transition
Chip Enable Low to Output Valid
CE
Output Enable Low to Output
Transition
Output Enable Low to Output Valid
OE
Chip Enable High to Output Hi-Z
HZ
Output Enable High to Output Hi-Z
DF
Chip Enable, Output Enable or
Address Transitionto Output
OH
Transition
G=V
E=V
G=V
G=V
G=V
E=V
E=V
G=V
E=V
IL
IL
,
IL
IL
IL
IL
IL
IL
IL
IL
M29F016B
Unit
55 70 90
Min 55 70 90 ns
Max 55 70 90 ns
Min 0 0 0 ns
Max 55 70 90 ns
Min 0 0 0 ns
Max 30 30 35 ns
Max 18 20 20 ns
Max 18 20 20 ns
Min 0 0 0 ns
Figure 8. Read Mode AC Waveforms
A0-A20
tAVQV tAXQX
E
G
DQ0-DQ7
tAVAV
VALID
tELQV tEHQX
tELQX tEHQZ
tGLQX tGHQX
tGLQV
tGHQZ
VALID
AI02966
14/22
Table 12. Write AC Characteristics, Write Enable Controlled
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Symbol Alt Parameter
t
AVAV
t
ELWL
t
WLWH
t
DVWH
t
WHDX
t
WHEH
t
WHWL
t
AVWL
t
WLAX
t
GHWL
t
WHGL
(1)
t
WHRL
t
VCHEL
Note: 1. Sampled only, not 100% tested.
t
WC
t
CS
t
WP
t
DS
t
DH
t
CH
t
WPH
t
AS
t
AH
t
OEH
t
BUSY
t
VCS
Address Valid to Next Address Valid Min 55 70 90 ns
Chip Enable Low to Write Enable Low Min 0 0 0 ns
Write Enable Low to Write Enable High Min 40 45 45 ns
Input Validto Write Enable High Min 25 30 45 ns
Write Enable High to Input Transition Min 0 0 0 ns
Write Enable High to Chip Enable High Min 0 0 0 ns
Write Enable High to Write Enable Low Min 20 20 20 ns
Address Valid to Write Enable Low Min 0 0 0 ns
Write Enable Low to Address Transition Min 40 45 45 ns
Output Enable High to Write Enable Low Min 0 0 0 ns
Write Enable High to Output Enable Low Min 0 0 0 ns
Program/Erase Valid to RB Low Max 30 30 35 ns
VCCHigh to Chip Enable Low
M29F016B
M29F016B
Unit
55 70 90
Min 50 50 50 µs
Figure 9. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20
E
G
W
DQ0-DQ7
V
CC
RB
tAVWL
tELWL
tVCHEL
VALID
tWLWHtGHWL
tDVWH
tWLAX
tWHEH
tWHGL
tWHWL
tWHDX
VALID
tWHRL
AI02967
15/22
M29F016B
Table 13. Write AC Characteristics, Chip Enable Controlled
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Symbol Alt Parameter
t
AVAV
t
WLEL
t
ELEH
t
DVEH
t
EHDX
t
EHWH
t
EHEL
t
AVEL
t
ELAX
t
GHEL
t
EHGL
(1)
t
EHRL
t
VCHWL
Note: 1. Sampled only, not 100% tested.
t
WC
t
WS
t
CP
t
DS
t
DH
t
WH
t
CPH
t
AS
t
AH
t
OEH
t
BUSY
t
VCS
Address Valid to Next Address Valid Min 55 70 90 ns
Write Enable Low to Chip Enable Low Min 0 0 0 ns
Chip Enable Low to Chip Enable High Min 40 45 45 ns
Input Validto Chip Enable High Min 25 30 45 ns
Chip Enable High to Input Transition Min 0 0 0 ns
Chip Enable High to Write Enable High Min 0 0 0 ns
Chip Enable High to Chip Enable Low Min 20 20 20 ns
Address Valid to Chip Enable Low Min 0 0 0 ns
Chip Enable Low to Address Transition Min 40 45 45 ns
Output Enable High Chip Enable Low Min 0 0 0 ns
Chip Enable High to Output Enable Low Min 0 0 0 ns
Program/Erase Valid to RB Low Max 30 30 35 ns
VCCHigh to Write Enable Low
M29F016B
Unit
55 70 90
Min 50 50 50 µs
Figure 10. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20
W
G
E
DQ0-DQ7
V
CC
RB
tAVEL
tWLEL
tVCHWL
VALID
tELEHtGHEL
tDVEH
VALID
tELAX
tEHWH
tEHGL
tEHEL
tEHDX
16/22
tEHRL
AI02968
Table 14. Reset/Block Temporary Unprotect AC Characteristics
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Symbol Alt Parameter
(1)
t
PHWL
t
PHEL
(1)
t
PHGL
(1)
t
RHWL
(1)
t
RHEL
(1)
t
RHGL
t
PLPX
(1)
t
PLYH
(1)
t
PHPHH
Note: 1. Sampled only, not 100% tested.
t
t
t
t
READY
t
VIDR
RP High to Write Enable Low, Chip Enable
RH
Low, Output Enable Low
RB High to Write Enable Low, Chip Enable
RB
Low, Output Enable Low
RP Pulse Width Min 500 500 500 ns
RP
Min 50 50 50 ns
Min 0 0 0 ns
RP Low to Read Mode Max 10 10 10 µs
RP Rise Time to V
ID
Min 500 500 500 ns
Figure 11. Reset/Block Temporary Unprotect AC Waveforms
M29F016B
M29F016B
Unit
55 70 90
W,
E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
RP
tPLPX
tPHPHH
tPLYH
AI02931
17/22
M29F016B
Table 15. Ordering Information Scheme
Example: M29F016B 70 N 1 T
Device Type
M29
Operating Voltage
F=V
Device Function
016B = 16 Mbit (2Mb x8), Uniform Block
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Package
N = TSOP40: 10 x 20 mm
M = SO44
Temperature Range
1=0to70°C
3 = –40 to 125 °C
6=–40to85°C
=5V±10%
CC
Option
T = Tape& Reel Packing
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devicesare shipped from the factory with the memorycontent bits erased to ‘1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
18/22
Table 16. Revision History
Date Revision Details
July 1999 First Issue
New document template
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 4)
03/30/00
Data Toggle Flowchart diagram change (Figure 5)
Program/Erase Times Maximum specification added (Table 6)
TestCondition change (Table10)
I
CC3
TSOP40 Package mechanical data change (Table17)
SO44 Package mechanical data change (Table18)
M29F016B
19/22
M29F016B
Table 17. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.17 0.27 0.0067 0.0106
C 0.10 0.21 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953
D1 18.30 18.50 0.7205 0.7283
E 9.90 10.10 0.3898 0.3976
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0276
α 0° 5° 0° 5°
N40 40
CP 0.10 0.0039
mm inches
Figure 12. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20 mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is not to scale.
LA1 α
20/22
M29F016B
Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 2.42 2.62 0.0953 0.1031
A1 0.22 0.23 0.0087 0.0091
A2 2.25 2.35 0.0886 0.0925
B 0.50 0.0197
C 0.10 0.25 0.0039 0.0098
D 28.10 28.30 1.1063 1.1142
E 13.20 13.40 0.5197 0.5276
e 1.27 – – 0.0500 – –
H 15.90 16.10 0.6260 0.6339
L 0.80 – – 0.0315 – –
α 3° ––3°––
N44 44
CP 0.10 0.0039
mm inches
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
B
e
CP
D
N
E
H
1
LA1 α
SO-b
Drawing is not to scale.
21/22
M29F016B
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22/22
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