ST M29F016B User Manual

M29F016B55M1T

M29F016B

16 Mbit (2Mb x8, Uniform Block) Single Supply Flash Memory

■SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS

■ACCESS TIME: 55ns

■PROGRAMMING TIME

±8μs by Byte typical

■32 UNIFORM 64 Kbyte MEMORY BLOCKS

■PROGRAM/ERASE CONTROLLER

±Embedded Byte Program algorithm

±Embedded Multi-Block/Chip Erase algorithm

±Status Register Polling and Toggle Bits

±Ready/Busy Output Pin

■ERASE SUSPEND and RESUME MODES

±Read and Program another Block during Erase Suspend

■TEMPORARY BLOCK UNPROTECTION MODE

■UNLOCK BYPASS PROGRAM COMMAND

±Faster Production/Batch Programming

■LOW POWER CONSUMPTION

±Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■20 YEARS DATA RETENTION

±Defectivity below 1 ppm/year

■ELECTRONIC SIGNATURE

±Manufacturer Code: 20h

±Device Code: ADh

	44
	1
TSOP40 (N)	SO44 (M)
10 x 20mm

Figure 1. Logic Diagram

	VCC
21	8
A0-A20	DQ0-DQ7
W
E	M29F016B
G	RB
RP

VSS

AI02964

March 2000

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M29F016B

Figure 2. TSOP Connections

A19	1	40	A20
A18			NC
A17			W
A16			G
A15			RB
A14			DQ7
A13			DQ6
A12			DQ5
E			DQ4
VCC	10 M29F016B	31	VCC
NC	11	30	VSS
RP			VSS
A11			DQ3
A10			DQ2
A9			DQ1
A8			DQ0
A7			A0
A6			A1
A5			A2
A4	20	21	A3
		AI02969

Table 1. Signal Names

A0-A20	Address Inputs
DQ0-DQ7	Data Inputs/Outputs
E	Chip Enable
G	Output Enable
W	Write Enable
RP	Reset/Block Temporary Unprotect
RB	Ready/Busy Output
VCC	Supply Voltage
VSS	Ground
NC	Not Connected Internally

Figure 3. SO Connections

NC	1	44	VCC
RP	2	43	E
A11	3	42	A12
A10	4	41	A13
A9	5	40	A14
A8	6	39	A15
A7	7	38	A16
A6	8	37	A17
A5	9	36	A18
A4	10	35	A19
NC	11	M29F016B 34	NC
NC	12	33	NC
A3	13	32	A20
A2	14	31	NC
A1	15	30	W
A0	16	29	G
DQ0	17	28	RB
DQ1	18	27	DQ7
DQ2	19	26	DQ6
DQ3	20	25	DQ5
VSS	21	24	DQ4
VSS	22	23	VCC
		AI02965

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			M29F016B
Table 2. Absolute Maximum Ratings (1)
Symbol	Parameter	Value	Unit
	Ambient Operating Temperature (Temperature Range Option 1)	0 to 70	°C
T	Ambient Operating Temperature (Temperature Range Option 6)	±40 to 85	°
A			C
	Ambient Operating Temperature (Temperature Range Option 3)	±40 to 125	°C
T	Temperature Under Bias	±50 to 125	°
BIAS			C
T	Storage Temperature	±65 to 150	°
STG			C
VIO (2)	Input or Output Voltage	±0.6 to 6	V
VCC	Supply Voltage	±0.6 to 6	V
VID	Identification Voltage	±0.6 to 13.5	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to ±2V during transition and for less than 20ns during transitions.

SUMMARY DESCRIPTION

The M29F016B is a 16 Mbit (2Mb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected in groups to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of

programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in a TSOP40 (10 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to '1').

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M29F016B

Table 3. Uniform Block Addresses, M29F016B

	#	Size	Address Range
		(Kbytes)
	31	64	1F0000h-1FFFFFh
	30	64	1E0000h-1EFFFFh
	29	64	1D0000h-1DFFFFh
	28	64	1C0000h-1CFFFFh
	27	64	1B0000h-1BFFFFh
	26	64	1A0000h-1AFFFFh
	25	64	190000h-19FFFFh
	24	64	180000h-18FFFFh
	23	64	170000h-17FFFFh
	22	64	160000h-16FFFFh
	21	64	150000h-15FFFFh
	20	64	140000h-14FFFFh
	19	64	130000h-13FFFFh
	18	64	120000h-12FFFFh
	17	64	110000h-11FFFFh
	16	64	100000h-10FFFFh
	15	64	0F0000h-0FFFFFh
	14	64	0E0000h-0EFFFFh
	13	64	0D0000h-0DFFFFh
	12	64	0C0000h-0CFFFFh
	11	64	0B0000h-0BFFFFh
	10	64	0A0000h-0AFFFFh
	9	64	090000h-09FFFFh
	8	64	080000h-08FFFFh
	7	64	070000h-07FFFFh
	6	64	060000h-06FFFFh
	5	64	050000h-05FFFFh
	4	64	040000h-04FFFFh
	3	64	030000h-03FFFFh
	2	64	020000h-02FFFFh
	1	64	010000h-01FFFFh
	0	64	000000h-00FFFFh

Protection

Group

7

6

5

4

3

2

1

0

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.

Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.

Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 14 and Figure 11, Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.

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After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 14 and Figure 11, Reset/Temporary Unprotect AC Characteristics.

During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1μF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC4.

VSS Ground. The VSS Ground is the reference for all voltage measurements.

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Table 4. Bus Operations

	Operation	E	G	W
	Bus Read	VIL	VIL	VIH
	Bus Write	VIL	VIH	VIL
	Output Disable	X	VIH	VIH
	Standby	VIH	X	X
	Read Manufacturer	VIL	VIL	VIH
	Code
	Read Device Code	VIL	VIL	VIH
	Note: X = VIL or VIH.

M29F016B

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 9 and 10, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.

When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply Current, ICC2. To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 10, DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4, for Program or Erase operations until the operation completes.

Address Inpu ts

Cell Address

Command Address

X

X

A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH

Data Inputs/Outpu ts

Data Output

Data Input

Hi-Z

Hi-Z

20h

ADh

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M29F016B

Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 4, Bus Operations.

Block Protection and Blocks Unprotection. Blocks can be protected in groups against accidental Program or Erase. See Table 3, Block Addresses, for details of which blocks must be protected together as a group. Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10μs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 20h.

The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F016B is ADh.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A16-A20 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on the Data Inputs/Outputs, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at '0' back to '1. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.

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M29F016B

Table 5. Commands

	Length					Bus Write Operations
Command		1st		2nd		3rd		4th		5th
		Addr Data		Addr Data		Addr Data		Addr	Data	Addr	Data
Read/Reset	1	X	F0
	3	555	AA	2AA	55	X	F0
Auto Select	3	555	AA	2AA	55	555	90
Program	4	555	AA	2AA	55	555	A0	PA	PD
Unlock Bypass	3	555	AA	2AA	55	555	20
Unlock Bypass	2	X	A0	PA	PD
Program
Unlock Bypass Reset	2	X	90	X	00
Chip Erase	6	555	AA	2AA	55	555	80	555	AA	2AA	55
Block Erase	6+	555	AA	2AA	55	555	80	555	AA	2AA	55
Erase Suspend	1	X	B0
Erase Resume	1	X	30

Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don't Care.

6th

Addr Data

555	10
BA	30

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e Operations until the Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final

write operation latches the address and data in the internal state machine and starts the Program/ Erase Controller.

The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.

Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

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