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M29F010B
1 Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory
■ SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPE RATI ONS
■ ACCESS TIME: 45 ns
■ PROGRAMMING TIME
– 8 µs per Byte typical
■ 8 UNIFORM 16 KBytes MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
– Manufacturer Code : 20h
– Device Code: 20h
■ ECOPACK
®
PACKAGES AVAILABLE
PLCC32 (K)
Figure 1. Logic Diagram
V
CC
17
A0-A16
W
E
G
M29F010B
TSOP32 (N)
8 x 20mm
8
DQ0-DQ7
V
SS
AI02735
1/20September 2005
M29F010B
Figure 2. PLCC Connections
A16
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A12
9
DQ1
NC
A15
1
32
M29F010B
17
SS
V
DQ2
DQ3
V
DQ4
CC
W
DQ5
NC
25
DQ6
A14
A13
A8
A9
A11
G
A10
E
DQ7
AI02737
Figure 3. TSOP Connections
A11 G
A9
A8
A13
A14
NC
V
CC
NC
A16
A15
A12
A7
A6
A5
A4 A3
1
W
8
M29F010B
9
16 17
32
25
24
AI02738
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
Table 1. Signal Names
A0-A16 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
E
G
W
V
CC
V
SS
NC Not Connected Internally
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
Table 2. Uniform Block Addresses, M29F010B
#
7 16 1C000h-1FFFFh
6 16 18000h-1BFFFh
5 16 14000h-17FFFh
4 16 10000h-13FFFh
3 16 0C000h-0FFFFh
2 16 08000h-0BFFFh
1 16 04000h-07FFFh
0 16 00000h-03FFFh
Size
(Kbytes)
Address Range
2/20
M29F010B
Table 3. Absolute Maximum Ratings
Symbol Parameter Value Unit
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
V
ID
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device re liability. Refer als o to the STMicroelec tronics SURE Program and ot her relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage –0.6 to 6 V
Supply Voltage –0.6 to 6 V
Identification Voltage –0.6 to 13.5 V
SUMMARY DESCRIPTION
The M29F010B is a 1 Mbit (128Kb x8) non-volatile
memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V suppl y. On power-up t he memory
defaults to its Read m ode whe re it can b e read in
the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independentl y s o it is pos si bl e to pres er ve
valid data w hile old da ta is erase d. Eac h block c an
be protected independ ently to prevent accidental
Program or Erase co mmands from modifyin g the
memory. Program an d E ras e c om man ds are wri tten to the Command I nterface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in PLCC32, TSOP32 (8 x
20mm) packages and it is supplied with all the bits
erased (set to ’1’).
In order to meet environm ental requirement s, ST
offers the M29F010B in ECOPACK
ECOPACK packages are Lead-free. The category
of second Level Interconnect is marked on the
package and on the inner box label, in compliance
with JEDEC Standard JESD97.
(1)
®
packages.
The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK
specifications are available at: www.st.com.
SIGNAL DESCRIPTIONS
See Figure 1, Lo gic Diagram, an d Table 1, S ignal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A16). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Rea d ope ra tio n. Dur ing B us
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E
). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
Output Enable (G
, all other pins are ignored.
IH
). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W
). The Write Enable, W, control s
the Bus Write operation of the memory’s Command Interface.
V
Supply Voltage. The VCC Supply Voltage
CC
supplies the power f or all operations (Read, Program, Erase etc.).
The Comman d I n t er f ac e is disabl ed w h en t he V
CC
Supply Voltage is less th an the Lockout Voltage,
3/20
M29F010B
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor sh ould be connected between
the V
Supply Voltage pin and the VSS Ground
CC
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
Vss Ground. The V
.
CC4
Ground is the reference
SS
for all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Writ e, Output Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip En able or Write
Enable are ignored by the m emo ry and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low s ig nal, V
, to Chip Enable
IL
and Output Enable and keeping Write Enable
High, V
. The Data Inputs/Outputs will ou tpu t the
IH
value, see Figure 8, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A v alid Bus Write operati on
begins by setting the desired address on the Address Inputs. The Ad dress Inputs are latched b y
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs ar e latched by the Com mand Interface on the rising ed ge of Chip Enab le
or Write Enable, whichever occurs first. Output Enable must remain High, V
, during the whole Bus
IH
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs /Outputs are in
the high impedance state when Output Enable is
High, V
.
IH
Standby. When Chip Enable is High, V
IH
, the
Data Inputs/Outputs pins are pl aced in the highimpedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at V
reduced to the TTL Stand by Sup ply Current I
the Supply Current is
IH
CC2
To furthe r reduce the Supp ly Curr ent to t he CMOS
Standby Supply Current, I
be held within V
± 0.2V. For Standby current
CC
, Chip Enable should
CC3
levels see T able 10, DC Characteristics.
During program or eras e operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
CC4
til the operation completes.
Automatic Standby. If CMOS levels (V
± 0.2V)
CC
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the interna l Supply Current is reduced to the CMOS Standby Supply Current, I
CC3
The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for us e by progr ammin g equip ment and are not usually used in applications.
They require V
to be applied to some pins.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can b e read b y apply ing the sig nals
listed in Table 4, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against accidental Program or Erase. Protected blocks can be
unprotected to allow data to be changed. Block
Protection and Blocks Unprotection operations
must only be performed on programming equipment. For further informa tion refer to Application
Note AN1122, Applying Protectio n and Unpr otection to M29 Series Flash.
.
.
4/20
Table 4. Bus Operations
Operation E G W Address Inputs
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VIL or VIH.
M29F010B
Data
Inputs/Outputs
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
X X X Hi-Z
V
IL
V
IL
V
V
V
V
V
Cell Address Data Output
IH
Command Address Data Input
IL
X Hi-Z
IH
A0 = VIL, A1 = VIL, A9 = VID,
IH
Others VIL or V
A0 = VIH, A1 = VIL, A9 = VID,
IH
Others VIL or V
IH
IH
20h
20h
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operation s will result in the memory return ing to Read mode. The long command sequences
are imposed to maximize data security.
The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the
text descriptions below.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where
it behaves lik e a ROM or EPROM. I t also resets
the errors in the Status Register. Either one or
three Bus Write o perations can be us ed to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take upto 10
µs
to abort. During the abort period no valid data can
be read from the memory. Issu ing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read t he Manu facturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Sel ect command. Once
the Auto Select comman d is issued the memory
remains in Auto Sele ct mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V
and A1 = VIL. The other address bits
IL
or VIH. The Manufacturer
IL
Code for STMicroelectronics is 20h.
The Device Code ca n be read using a Bu s Read
operation with A0 = V
address bits may be s et to either V
and A1 = VIL. The other
IH
or VIH. The
IL
Device Code for the M29F010B is 20h.
The Block Protectio n Statu s of ea ch block c an be
read using a Bus Read ope ration with A0 = V
A1 = V
, and A14-A16 spec ifying the addr ess of
IH
IL
the block. The other address bits may be set to either V
or VIH. If the addressed block is protected
IL
then 01h is output on the Data Inputs/Outputs, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protect ed block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation th e memory will ig nore all commands. It is no t possib le to is sue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read operations during the p rogram operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back t o ’1’. One of the Erase Com-
,
5/20
M29F010B
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bu s Write operations are r equired
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program com mand and the Unlock B ypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Program command can be used to
program one address in memory at a time. The
command requires t wo Bus Write oper ations, the
final write operati on lat ches the ad dress and d ata
in the internal state machine and starts the Program/Erase Controller.
The Program operation us ing the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be progra mme d; the op eration cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leav es the device in Unlock Bypass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset comm and can b e used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unc hanged . No er ror con dition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase o per at ion has c om ple ted the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase command can be used to erase a l ist of one or more
blocks. Six Bus W rite operations are required to
select the first block in the list. Each additional
block in the lis t can be selec ted by repeating the
sixth Bus Write operation using the address of the
additional block. The Bloc k Er as e op erati on st ar ts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the sel ected blocks are pr otected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Eras e o perat ion the memory will
ignore all comman ds except the Erase Suspend
and Read/Reset commands . Typical block erase
times are given in Table 6. All Bus Read operations during the B lock Erase op eration wil l output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Comma nd sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase S u sp en d
Command may be used to tempor arily suspend a
6/20
M29F010B
Block Erase operation a nd return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Control ler will sus pend with in
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additiona l block (before
the Program/Erase Controller starts) then the
both Read and Program operations behave as
normal on these bloc ks. Re adi ng fro m b lock s t hat
are being erased will output the Status Register. It
is also possible to enter the Auto Select mode: the
memory wil l behav e as in t he Auto Select mo de on
all blocks until a Read/Reset command returns the
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Erase is suspende d i mme di atel y and wil l sta rt im mediately when the Eras e Resume Command is
issued. It will not be possib le to select an y further
blocks for erasure after the Erase Resume.
During Erase Suspend i t is possible to Read and
Program cells in blocks that are not being erased;
Table 5. Commands
Bus Write Operations
Command
Read/Reset
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses address bits A0-A10 to verify the commands , the upper address bits are Don’t Care.
Read/Reset. After a Read/Re set command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program , Ch ip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory ret urns to Read Mode. Add additio nal Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After th e Erase Suspend command read non -erasing memory blocks as no rmal, issue Auto Select and P rogram commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
1X F0
3555 AA2AA 55 X F0
2 X A0 PA PD
1st 2nd 3rd 4th 5th 6th
Length
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
7/20
M29F010B
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
(T
= 0 to 70°C, –40 to 85°C or –40 to 125°C)
A
Parameter Min
Chip Erase (All bits in the memory set to ‘0’) 0.6 0.6 sec
Chip Erase 1.3 1.3 6 sec
Block Erase (16 Kbytes) 0.3 0.3 2 sec
Program 8 8 150 µs
Chip Program 1.2 1.2 4.5 sec
Program/Erase Cycles (per Block) 100,000 cycles
Note: 1. TA = 25°C, VCC = 5V.
Typ
(1)
Typical after
100k W/E Cycles
(1)
Max Unit
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block being erased
is accessed.
The bits in the Status Reg ist er ar e sum ma rize d i n
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has res ponded to an Erase Suspend .
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed outp ut DQ7, not its complement.
During Erase operations the Data Pollin g Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspen d mode the Data Polling Bit will
output a ’1’ during a Bus Read oper ation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an example of how to use the Data Polling Bi t. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase S uspend. The Togg le Bit is
output on DQ6 when the Status Register is read.
During Program and Er ase oper ation s the Tog gle
Bit changes from ’0’ to ’1’ to ’0’ , etc., with s uccessive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowch art, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pr ogram, Block Erase or Chip Erase operation fails to
write the correct data to the memor y. If the Error
Bit is set a Read/Reset comma nd mu st be issue d
before other comman ds are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so may
or may not set D Q5 at ‘ 1’. In bo th cases, a succes sive Bus Read operation will show the bit is still ’0’.
One of the Erase commands mu st be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Erase Timer Bit (DQ3). T he Er ase Tim er Bi t can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program /Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Contr oller starts the Erase Timer
Bit is set to ’0’ an d addition al blocks to be erase d
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
8/20
M29F010B
Erase controller d uring Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0 ’ to ’1’ to ’0’, etc., wi th
successive Bus Rea d operations from ad dresses
within the blocks being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased . Bus Read operations to addresses within blocks not b ei ng e rase d wi ll output
the memory cell data as if in Read mode.
After an Erase o per at ion th at ca us es th e Er ror B it
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses with in blocks that have not
erased correctly. Th e Alternative Toggle B it does
not change if the addressed block has erased correctly.
Table 7. Status Register Bits
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2
Program Any Address DQ7
Program During Erase Suspend Any Address DQ7
Program Error Any Address DQ7
Chip Erase Any Address 0 To gg le 0 1 Togg le
Erasing Block 0 Toggle 0 0 Toggle
Block Erase before timeout
Non-Erasing Block 0 Toggle 0 0 No Toggle
Erasing Block 0 Toggle 0 1 Toggle
Block Erase
Non-Erasing Block 0 Toggle 0 1 No Toggle
Erasing Block 1 No Toggle 0 – Toggle
Erase Suspend
Non-Erasing Block Data read as normal
Good Block Address 0 Toggle 1 1 No Toggle
Erase Error
Faulty Block Address 0 Toggle 1 1 Toggle
Note: Unspecified data bits should be igno red.
Toggle 0 – –
Toggle 0 – –
Toggle 1 – –
9/20
M29F010B
Figure 4. Data Polling Flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
DATA
NO
DQ5
READ DQ7
at VALID ADDRESS
DQ7
DATA
FAIL PASS
= 1
YES
=
NO
YES
YES
=
NO
AI03598
Figure 5. Data Toggle Flowchart
START
READ
DQ5 & DQ6
READ DQ6
DQ6
=
TOGGLE
NO
DQ5
= 1
READ DQ6
TWICE
DQ6
=
TOGGLE
FAIL PASS
NO
YES
YES
NO
YES
AI01370B
10/20
Table 8. AC Measurement Conditions
M29F010B
Parameter
45 70 / 90 / 120
AC Test Conditions High Speed Standard
M29F010B
Load Capacitance (C
)
L
30pF 100pF
Input Rise and Fall Times ≤ 10ns ≤ 10ns
Input Pulse Voltages 0 to 3V 0.45 to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 6. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.45V
2.0V
0.8V
AI01275B
Figure 7. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL = 30pF or 100pF
CL includes JIG capacitance
OUT
AI03027
Table 9. Capacitance
(T
= 25 °C, f = 1 MHz)
A
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 100% tested .
Input Capacitanc e
Output Capacitance
V
V
OUT
IN
= 0V
= 0V
6pF
12 pF
11/20
M29F010B
Table 10. DC Characteristics
(T
= 0 to 70°C, –40 to 85°C or –40 to 125°C)
A
Symbol Parameter Test Condition Min
I
CC4
I
I
I
CC1
I
CC2
I
CC3
V
V
V
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current (Read)
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
(1)
Supply Current (Program/Erase)
Input Low Voltage –0.5 0.8 V
IL
Input High Voltage 2
IH
Output Low Voltage
OL
Output High Voltage TTL
V
OH
Output High Voltage CMOS
V
I
V
LKO
Note: 1. Sampled only, not 100% tested.
Identification Voltage 11.5 12.5 V
ID
Identification Current
ID
Program/Erase Lockout Supply
(1)
Voltage
2. T
= 25°, VCC = 5V.
A
0V ≤ V
≤ V
IN
CC
0V ≤ V
E
= VIL, G = VIH, f = 6MHz
E
≤ V
OUT
CC
E
= V
IH
= VCC ±0.2V
Program/Erase
Controller active
I
= 5.8mA
OL
I
= –2.5mA
OH
= –100µA VCC –0.4
I
OH
A9 = V
ID
Typ
(2)
Max Unit
±1 µA
±1 µA
515mA
1mA
30 100 µA
20 mA
V
+0.5
CC
0.45 V
2.4 V
100 µA
3.2 4.2 V
V
V
12/20
Table 11. Read AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Symbol Alt Parameter Test Condition
= VIL,
Address Valid to Next
t
AVAV
t
AVQV
(1)
t
ELQX
t
ELQV
(1)
t
GLQX
t
GLQV
(1)
t
EHQZ
(1)
t
GHQZ
t
EHQX
t
GHQX
t
AXQX
Note: 1. Sampled only, not 100% tested.
t
t
ACC
t
t
t
OLZ
t
t
t
t
RC
Address Valid
Address Valid to Output Valid
Chip Enable Low to Output
LZ
Transition
Chip Enable Low to Output
CE
Valid
Output Enab le Low to Output
Transition
Output Enab le Low to Output
OE
Valid
Chip Enable High to Output
HZ
Hi-Z
Output Enable High to
DF
Output Hi-Z
Chip Enable, Output Enable
or Address Transition to
OH
Output Transition
E
G = V
E
= VIL,
G = V
= V
G
= V
G
= V
E
= V
E
= V
G
= V
E
IL
IL
IL
IL
IL
IL
IL
IL
M29F010B
M29F010B
Unit
45 70 / 90 / 120
Min 45 70 ns
Max 45 70 ns
Min 0 0 ns
Max 45 70 ns
Min 0 0 ns
Max 25 30 ns
Max 15 20 ns
Max 15 20 ns
Min 0 0 ns
Figure 8. Read Mode AC Waveforms
A0-A16
tAVQV tAXQX
E
G
DQ0-DQ7
tAVAV
VALID
tELQV
tELQX tEHQZ
tGLQX tGHQX
tGLQV
tGHQZ
VALID
tEHQX
AI02926
13/20
M29F010B
Table 12. Write AC Characteristics, Write Enable Controlled
(T
= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
A
Symbol Alt Parameter
t
AVAV
t
ELWL
t
WLWH
t
DVWH
t
WHDX
t
WHEH
t
WHWL
t
AVWL
t
WLAX
t
GHWL
t
WHGL
t
VCHEL
t
Address Valid to Next Address Valid Min 45 70 ns
WC
t
Chip Enable Low to Write Enable Low Min 0 0 ns
CS
t
Write Enable Low to Write Enable High Min 40 45 ns
WP
t
Input Valid to Write Enable High M in 25 30 ns
DS
t
Write Enable High to Input Transition Min 0 0 ns
DH
t
Write Enable High to Chip Enable High Min 0 0 ns
CH
t
Write Enable High to Write Enable Low Min 20 20 ns
WPH
t
Address Valid to Write Enable Low Min 0 0 ns
AS
t
Write Enable Low to Address Transition Min 40 45 ns
AH
Output Enable High to Write Enable Low Min 0 0 ns
t
Write Enable High to Output Enable Low Min 0 0 ns
OEH
t
VCSVCC
High to Chip Enable Low
Min 50 50 µs
M29F010B
Unit
45 70 / 90 / 120
Figure 9. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A16
E
G
W
DQ0-DQ7
V
CC
tAVWL
tELWL
tVCHEL
VALID
tWLWHtGHWL
tDVWH
tWLAX
tWHEH
tWHGL
tWHWL
tWHDX
VALID
AI02927
14/20
Table 13. Write AC Characteristics, Chip Enable Controlled
(T
= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
A
Symbol Alt Parameter
t
AVAV
t
WLEL
t
ELEH
t
DVEH
t
EHDX
t
EHWH
t
EHEL
t
AVEL
t
ELAX
t
GHEL
t
EHGL
t
VCHWL
t
Address Valid to Next Address Valid Min 45 70 ns
WC
t
Write Enable Low to Chip Enable Low Min 0 0 ns
WS
t
Chip Enable Low to Chip Enable High Min 40 45 ns
CP
t
Input Valid to Chip Enable High Min 25 30 ns
DS
t
Chip Enable High to Input Transition Min 0 0 ns
DH
t
Chip Enable High to Write Enable High Min 0 0 ns
WH
t
Chip Enable High to Chip Enable Low Min 20 20 ns
CPH
t
Address Valid to Chip Enable Low Min 0 0 ns
AS
t
Chip Enable Low to Address Transition Min 40 45 ns
AH
Output Enable High Chip Enable Low Min 0 0 ns
t
Chip Enable High to Output Enable Low Min 0 0 ns
OEH
t
VCSVCC
High to Write Enable Low
Min 50 50 µs
M29F010B
M29F010B Unit
45 70 / 90 / 120
Figure 10. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A16
W
G
E
DQ0-DQ7
V
CC
tAVEL
tWLEL
tVCHWL
VALID
tELEHtGHEL
tDVEH
tELAX
tEHWH
tEHGL
tEHEL
tEHDX
VALID
AI02928
15/20
M29F010B
Table 14. Ordering Information Scheme
Example: M29F010B 70 N 1 T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
010B = 1 Mbit (128Kb x8), Uniform Block
Speed
45 = 45 ns
70 = 70 ns
90 = 90 ns
120 = 120ns
Package
K = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
Note: The last two characters of th e ordering cod e may be r eplaced by a letter code for preprogr ammed
parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of availa ble opt ion s (Spe ed, Pac k age , et c... ) or for fu r ther i nfo rm ati on o n a ny aspec t o f th is de vice, please contact the ST Sales Office nearest to you.
16/20
M29F010B
Table 16. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 3.18 3.56 0.125 0.140
A1 1.53 2.41 0.060 0.095
A2 0.38 – 0.015 –
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
CP 0.10 0.004
D 12.32 12.57 0.485 0.495
D1 11.35 11.51 0.447 0.453
D2 4.78 5.66 0.188 0.223
D3 7.62 – – 0.300 – –
E 14.86 15.11 0.585 0.595
E1 13.89 14.05 0.547 0.553
E2 6.05 6.93 0.238 0.273
E310.16– –0.400– –
e 1.27 – – 0.050 – –
F 0.00 0.13 0.000 0.005
N32 32
R 0.89 – – 0.035 – –
millimeters inches
Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline
E3
Note: Drawing is not to scale.
D
D1
1 N
D3
D2 D2
E1 E
F
0.51 (.020)
1.14 (.045)
R
A1
A2
E2
B
E2
CP
B1
e
A
PLCC-A
17/20
M29F010B
Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A1.200.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.15 0.27 0.0059 0.0106
C 0.10 0.21 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953
D1 18.30 18.50 0.7205 0.7283
E 7.90 8.10 0.3110 0.3189
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0276
α 0° 5° 0° 5°
N32 32
CP 0.10 0.0039
millimeters inches
Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
A2
Note: Drawing is not to scale.
1 N
N/2
TSOP-a
D1
D
DIE
E
A
C
e
B
CP
LA1 α
18/20
Table 15. Revision History
Date Rev. Revision Details
July 1999 -01 F irst Issue
New document template
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
28-Jul-2000 -02
22-Apr-2002 -03 PLCC32 package mechanical data modified
19-Sep-2005 4.0
Data Polling Flowchart diagram change (Figure 4)
Data Toggle Flowchart diagram change (Figure 5)
Program/Erase Times specification change (Table 6)
and I
I
CC1
PDIP32 package removed.
Table 14. Ordering Information Scheme: standard package added and ECOPACK version
added for both standard package, and Tape & Reel packing.
Typ. specification added (Table 10)
CC3
M29F010B
19/20
M29F010B
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20/20
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