ST M29F010B User Manual

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M29F010B

1 Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory

■ SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPE RATI ONS

■ ACCESS TIME: 45 ns

■ PROGRAMMING TIME

– 8 µs per Byte typical

■ 8 UNIFORM 16 KBytes MEMORY BLOCKS

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code : 20h – Device Code: 20h

■ ECOPACK

PACKAGES AVAILABLE

PLCC32 (K)

Figure 1. Logic Diagram

A0-A16

M29F010B

TSOP32 (N)

8 x 20mm

DQ0-DQ7

AI02735

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M29F010B

Figure 2. PLCC Connections

A16

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A12

DQ1

A15

M29F010B

DQ2

DQ3

DQ4

DQ5

DQ6

A14 A13 A8 A9 A11 G A10 E DQ7

AI02737

Figure 3. TSOP Connections

A11 G

A8 A13 A14

CC NC

A16 A15 A12

A4 A3

M29F010B

16 17

25 24

AI02738

A10 E DQ7 DQ6 DQ5 DQ4 DQ3 V

DQ2 DQ1 DQ0 A0 A1 A2

Table 1. Signal Names

A0-A16 Address Inputs DQ0-DQ7 Data Inputs/Outputs E G W V

NC Not Connected Internally

Chip Enable Output Enable Write Enable Supply Voltage Ground

Table 2. Uniform Block Addresses, M29F010B

7 16 1C000h-1FFFFh 6 16 18000h-1BFFFh 5 16 14000h-17FFFh 4 16 10000h-13FFFh 3 16 0C000h-0FFFFh 2 16 08000h-0BFFFh 1 16 04000h-07FFFh 0 16 00000h-03FFFh

Size

(Kbytes)

Address Range

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M29F010B

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

BIAS

STG

(2)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device re liability. Refer als o to the STMicroelec tronics SURE Program and ot her relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage –0.6 to 6 V Supply Voltage –0.6 to 6 V

Identification Voltage –0.6 to 13.5 V

SUMMARY DESCRIPTION

The M29F010B is a 1 Mbit (128Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V suppl y. On power-up t he memory defaults to its Read m ode whe re it can b e read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independentl y s o it is pos si bl e to pres er ve valid data w hile old da ta is erase d. Eac h block c an be protected independ ently to prevent accidental Program or Erase co mmands from modifyin g the memory. Program an d E ras e c om man ds are wri tten to the Command I nterface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in PLCC32, TSOP32 (8 x 20mm) packages and it is supplied with all the bits erased (set to ’1’).

In order to meet environm ental requirement s, ST offers the M29F010B in ECOPACK ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97.

(1)

packages.

The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

SIGNAL DESCRIPTIONS

See Figure 1, Lo gic Diagram, an d Table 1, S ignal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A16). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Rea d ope ra tio n. Dur ing B us Write operations they represent the commands sent to the Command Interface of the internal state machine.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V

Output Enable (G

, all other pins are ignored.

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, control s

the Bus Write operation of the memory’s Command Interface.

Supply Voltage. The VCC Supply Voltage

supplies the power f or all operations (Read, Program, Erase etc.).

The Comman d I n t er f ac e is disabl ed w h en t he V

Supply Voltage is less th an the Lockout Voltage,

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M29F010B

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor sh ould be connected between the V

Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I

Vss Ground. The V

CC4

Ground is the reference

for all voltage measurements.

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Writ e, Output Disable, Standby and Automatic Standby. See Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip En able or Write Enable are ignored by the m emo ry and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low s ig nal, V

, to Chip Enable

and Output Enable and keeping Write Enable High, V

. The Data Inputs/Outputs will ou tpu t the

value, see Figure 8, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A v alid Bus Write operati on begins by setting the desired address on the Address Inputs. The Ad dress Inputs are latched b y the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs ar e latched by the Com mand Interface on the rising ed ge of Chip Enab le or Write Enable, whichever occurs first. Output Enable must remain High, V

, during the whole Bus

Write operation. See Figures 9 and 10, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs /Outputs are in the high impedance state when Output Enable is High, V

Standby. When Chip Enable is High, V

, the Data Inputs/Outputs pins are pl aced in the highimpedance state and the Supply Current is reduced to the Standby level.

When Chip Enable is at V reduced to the TTL Stand by Sup ply Current I

the Supply Current is

CC2

To furthe r reduce the Supp ly Curr ent to t he CMOS Standby Supply Current, I be held within V

± 0.2V. For Standby current

, Chip Enable should

CC3

levels see T able 10, DC Characteristics. During program or eras e operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program or Erase operations un-

CC4

til the operation completes. Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the interna l Supply Current is reduced to the CMOS Standby Supply Current, I

CC3

The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for us e by progr ammin g equip ment and are not usually used in applications. They require V

to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can b e read b y apply ing the sig nals listed in Table 4, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Blocks Unprotection operations must only be performed on programming equipment. For further informa tion refer to Application Note AN1122, Applying Protectio n and Unpr otection to M29 Series Flash.

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Table 4. Bus Operations

Operation E G W Address Inputs

Bus Read Bus Write Output Disable X Standby Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

M29F010B

Data

Inputs/Outputs

X X X Hi-Z

V V V

Cell Address Data Output

Command Address Data Input

X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or V A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or V

20h

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operation s will result in the memory return ing to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10

µs

to abort. During the abort period no valid data can be read from the memory. Issu ing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read t he Manu facturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Sel ect command. Once the Auto Select comman d is issued the memory remains in Auto Sele ct mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V may be set to either V

and A1 = VIL. The other address bits

or VIH. The Manufacturer

Code for STMicroelectronics is 20h.

The Device Code ca n be read using a Bu s Read operation with A0 = V address bits may be s et to either V

and A1 = VIL. The other

or VIH. The

Device Code for the M29F010B is 20h. The Block Protectio n Statu s of ea ch block c an be

read using a Bus Read ope ration with A0 = V A1 = V

, and A14-A16 spec ifying the addr ess of

the block. The other address bits may be set to either V

or VIH. If the addressed block is protected

then 01h is output on the Data Inputs/Outputs, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protect ed block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation th e memory will ig nore all commands. It is no t possib le to is sue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the p rogram operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ’0’ back t o ’1’. One of the Erase Com-

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M29F010B

mands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bu s Write operations are r equired to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program com mand and the Unlock B ypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires t wo Bus Write oper ations, the final write operati on lat ches the ad dress and d ata in the internal state machine and starts the Program/Erase Controller.

The Program operation us ing the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be progra mme d; the op eration cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leav es the device in Unlock Bypass Mode. See the Program command for details on the behavior.

Unlock Bypass Reset Command. The Unlock Bypass Reset comm and can b e used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unc hanged . No er ror con dition is given when protected blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more details.

After the Chip Erase o per at ion has c om ple ted the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.

Block Erase Command. The Block Erase command can be used to erase a l ist of one or more blocks. Six Bus W rite operations are required to select the first block in the list. Each additional block in the lis t can be selec ted by repeating the sixth Bus Write operation using the address of the additional block. The Bloc k Er as e op erati on st ar ts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the sel ected blocks are pr otected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the Block Eras e o perat ion the memory will ignore all comman ds except the Erase Suspend and Read/Reset commands . Typical block erase times are given in Table 6. All Bus Read operations during the B lock Erase op eration wil l output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

The Block Erase Comma nd sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.

Erase Suspend Command. The Erase S u sp en d Command may be used to tempor arily suspend a

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