Datasheet M28W640FCT, M28W640FCB Datasheet (ST)

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FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V –V –V

■ ACCESS TIME: 70, 85, 90,100ns

■ PROGRAMMING TIME:

– 10µs typical – Double Word Programming Option – Quadruple Word Programming Option

■ COMMON FLASH INTERFACE

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom – Main Blocks

■ BLOCK LOCKING

– All blocks locked at Power Up – Any combination of blocks can be locked –WP

■ SECURITY

– 128 bit user Programmable OTP cells – 64 bit unique device identifier

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M28W640FCT: 8848h – Bottom Device Code, M28W640FCB:

■ PACKAGES

– Compliant with Lead-Free Soldering – Lead-Free Versions

= 2.7V to 3.6V Core Power Supply

= 1.65V to 3.6V for Input/Output

DDQ

= 12V for fast Program (optional)

location)

for Block Lock-Down

8849h

Processes

M28W640FCT

M28W640FCB

64 Mbit (4Mb x16, Boot Block)

3V Supply Flash Memory

PRELIMINARY DATA

Figure 1. Packages

FBGA

TFBGA48 (ZB)

6.39 x 10.5mm

TSOP48 (N)

12 x 20mm

April 2005

This is preliminary information on a new product no w in developmen t or undergoi ng evaluatio n. Details are subje ct to chan ge without no tic e.

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M28W640FCT, M28W640FCB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E Output Enable (G Write Enable (W Write Protect (WP Reset (RP V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DDQ

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 6. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Program, Erase Times and Program/Erase Endurance Cycles

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

. . . . . . . . . . . . . . . . . . . 16

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 16. Read AC Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 13.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 30

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 30 Figure 14.TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline 31 Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 31

Figure 15.TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 32

Figure 16.TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 32

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 23. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 24. Top Boot Block Addresses, M28W640FCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 25. Bottom Boot Block Addresses, M28W640FCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 27. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 28. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 30. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 31. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 18.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 19.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 20.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 47

Figure 21.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 23.Locking Operations Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 24.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 51

APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . . 52

Table 32. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 33. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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SUMMARY DESCRIPTION

The M28W640FCT and M28W640FCB are 64 Mbit (4 Mbit x 16) non-volatile Flash memories that can be erased electricall y at block level and programmed in-system on a Word-by-Word basis using a 2.7V to 3.6V V a 1.65V to 3.6V V pins. An optional 12V V ed to speed up customer programming.

The devices fe ature an asymmetric al blocked architecture. They have an array of 135 blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. The M28W640FCT has the Parameter Blocks at the top of the memory address space while the M28 W640FCB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5., Block Ad-

dresses.

The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant c ode and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental program ming or erasure. There i s an additional hardware protection against program and erase. When V tected against program or erase. All blocks are locked at Power Up.

Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be susp ended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles.

The device includ es a 192 bi t Protecti on Registe r to increase the protection of a system design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. Th e 64 bit segment contains a unique device number written by ST, while the second one is one-time-pr ogrammabl e by the user. The user programmable segment can be permanently protected. Figure 6., shows the Protection Register Memory Map.

Program and Erase co mmands are writte n to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation c an be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The memory is offered i n TSOP48 (12 X 20mm) and TFBGA48 (6.39 x 10.5mm, 0.75mm pitch) packages and is su pplied with all the bi ts erased (set to ’1’).

supply for the circuitry and

supply for the Input/Out put

DDQ

power supply is provid-

≤ V

all blocks are pro-

PPLK

M28W640FCT, M28W640FCB

In addition to the standard version, the pac kages are also available in Lead-free version, in compliance with JEDEC St d J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free soldering processes.

Figure 2. Logic Diagram

DDQVPP

A0-A21

M28W640FCT M28W640FCB

Table 1. Signal Names

A0-A21 Address Inputs DQ0-DQ15 Data Input/Output E G W RP WP V

DDQ

NC Not Connected Inter na lly

Chip Enable Output Enable Write Enable Reset Write Protect Core Power Supply Power Supply for

Input/Output Optional Supply Voltage for

Fast Program & Erase Ground

DQ0-DQ15

AI09903

5/55

Page 6

M28W640FCT, M28W640FCB

Figure 3. TSOP Connections

A15 A14 A13 A12 A11

A16 V

DDQ

DQ15 DQ7

A10 DQ14

A21 A20

WP A19 A18 A17

A9 A8

A7 A6 A5 A4 A3 A2 A1

M28W640FCT M28W640FCB

24 25

AI09904b

37 36

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

SSQ

E A0

6/55

Page 7

Figure 4. TFBGA Connections (Top view through package)

M28W640FCT, M28W640FCB

87654321

A13

A14

DDQ

DQ15

DQ7V

A8A11

DQ13

RP A18

A21

DQ11

DQ12

DQ4

WP A19

A20

DQ2

A7V

A5A17WA10

DQ0DQ9DQ3DQ6

DQ1DQ10V

A1A3A6A9A12A15

A0EDQ8DQ5DQ14A16

SSQ

AI04380b

7/55

Page 8

M28W640FCT, M28W640FCB

Figure 5. Block Addresses

M28W640FCT

Top Boot Block Addresses

3FFFFF

3FF000

3F8FFF

3F8000

3F7FFF

3F0000

00FFFF

008000

007FFF

000000

Note: Also see APPENDIX A., Tables 24 and 25 for a full listing of the Block Addresses.

4 KWords

Total of 8

4 KWord Blocks

4 KWords

32 KWords

Total of 127

32 KWord Blocks

32 KWords

Bottom Boot Block Addresses

3FFFFF

3F8000

3F7FFF

3F0000

00FFFF

008000

007FFF

007000

000FFF

000000

M28W640FCB

32 KWords

Total of 127

32 KWord Blocks

32 KWords

4 KWords

Total of 8

4 KWord Blocks

4 KWords

AI09905

Figure 6. Protection Register Memory Map

PROTECTION REGISTER

8Ch

User Programmable OTP

85h 84h

81h 80h

Unique device number

Protection Register Lock 1 0

AI05520b

8/55

Page 9

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal

Names, for a brief overview of the signals connect-

ed to this device. Address Inputs (A0-A21). The Address Inputs

select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be progra mmed d uring a Write Bus operation.

Chip Enable (E

vates the memory control lo gic, input buffers, de coders and sense amplifiers. When Chip Enable is at V

and Reset is at VIH the device is in active

mode. When Chip Enable i s at V deselected, the outputs a re high impedance and the power consumption is reduced to the stand-by level.

Output Enable (G

data outputs during the Bus Read operation of the memory.

Write Enable (W

Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip En abl e, E able, W

, whichever occurs first.

Write Protect (WP

that gives an additional hardware protection for each block. When Write Protect is at V Down is enabled and the protection status of the block cannot be changed. When Write Protect is at V

, the Lock-Down is disa bled an d the bl ock c an

be locked or unlocked. (refer to Table 7., Read

Protection Register and Lock Register).

Reset (RP

ware reset of the memory. When Re set is at V the memory is in reset mode: the outputs are high impedance and the curre nt consumption is minimized. After Reset all blocks are in the Locked

). The Chip Enable input acti-

the memory is

). The Output Enable controls

). The Write Enabl e contro ls the

, or Write En-

). Write Protect is an input

, the Lock-

). The Reset input provides a hard-

M28W640FCT, M28W640FCB

state. When Reset is a t V operation. Exiting reset mode the device enters read array mode, but a negative transi tion of Chip Enable or a change of th e address is require d to ensure valid data outputs.

Supply Voltage. VDD provides the power

supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).

Supply Voltage. V

DDQ

supply to the I/O pins and enable s all Outputs to be powered independently from V tied to V

Program Supply Voltage. VPP is both a

or can use a separate supply.

control input and a power supply pin. The two functions are selected by the voltage range applied to the pin . The Supply Voltage V Program Supply Voltage V any order.

If V

is kept in a low voltage range (0V to 3.6V)

is seen as a co ntrol inpu t. In th is ca se a v olt-

age lower than V

PPLK

against program or erase, whi le V ables these function s (see T able 15., DC Charac-

teristics, for the relevant values). V

sampled at the beginning of a program or erase; a change in its valu e afte r the o per ati on has st ar ted does not have any effect on Program or Erase, however for Double or Quadr uple Word Program the results are uncertain.

If V

is in the range 1 1.4V to 12.6V it acts as a

power supply pin. In this condition V stable until the Pr ogram/Erase algorithm is com pleted (see Table 17. and Table 18.).

Ground. VSS is the reference for al l voltage

measurements.

Note: Each device in a system should have V

DD, VDDQ

pacitor close to the pin. See Figure 8., AC Mea-

and VPP decoupled with a 0.1µF ca-

surement Load Circuit. The PCB track widths

should be sufficient to carry the required V program and erase currents.

, the device is in normal

provides the power

DDQ

. V

can be applied in

gives an absolute protection

DDQ

and the

> V

is only

must be

can be

en-

PP1

9/55

Page 10

M28W640FCT, M28W640FCB

BUS OPERATIONS

There are six standard bus operations that control the device. These are Bus Read, Bus Writ e, Output Disable, Standby, Automatic Standby and Reset. See Table 2., Bus Op erations, for a summary.

Typically glitches of les s th an 5ns on C hip Enab le or Write Enable are ignored by the memory and do not affect bus operations.

Read. Read Bus operation s are used to output the contents of the Mem ory Array, the Electr onic Signature, the Status Regi ster and the Common Flash Interface. Both Chip Enable and Output Enable must be at V eration. The Chip E nable inp ut should be used to enable the devi ce. Ou tput E nab le should be us ed to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See

Figure 9., Read AC Waveforms, and Table

16., Read AC Characteristics, for details of wh en

the output becomes valid. Read mode is the default state of the device when

exiting Reset or after power-up. Write. Bus Write oper ations write Commands to

the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V V

. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.

See Figure 10. and Figure 11., Write AC Wave- forms, and Table 17. and Table 18., Write AC

in order to perform a read op-

with Output Enable at

Characteristics, for details of the timing requirements.

Output Disable. The data outputs are high impedance when the Output Enable is at V

Standby. Standby disables most o f the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at V

and the device is in

read mode. The power consumption is reduced to the stand-by level and the ou tputs are set to high impedance, independently from the Output Enable or Write Enable inpu ts. If Chi p E nab le swi tc hes to V

during a program or eras e operation, the de-

vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V current is reduced to I

. The data Inputs/Out-

DD1

, and the supply

puts will st ill ou tp ut dat a if a bus Read ope rati on is in progress.

Reset. During Reset mode w hen Output E nable is Low, V

, the memory is deselected and the out-

puts are high impedance. The memory is in Reset mode when Reset is at V

. The power consump-

tion is reduced to the Standby level, independently from the Chip Enable, Output Enabl e or Write En able inputs. If Reset is pulled to V

during a Pro-

gram or Erase, this operation is aborted and the memory content is no longer valid.

Table 2. Bus Operations

Operation E G W RP WP

Bus Read Bus Write Output Disable Standby Reset X X X

Note: X = VIL or VIH, V

10/55

V V V

= 12V ± 5%.

PPH

X Don't Care Data Output

X X Don't Care Hi-Z X Don't Care Hi-Z X Don't Care Hi-Z

or V

PPH

DQ0-DQ15

Data Input

Page 11

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program /Erase Control ler handles all timings and veri fies the correct executi on of the Program and Eras e commands. The Program/Erase Controlle r provides a Status Registe r whose output may be read at any time dur ing, to monitor the progress of the operation, or the Pro gram/Erase states. See Table 3., Command

Codes, for a summary of the c ommands and s ee APPENDIX D., Table 32., Write State Machine Current/Next, sheet 1 of 2., for a summary of the

Command Interface. The Command Interface is reset to Read mode

when power is first applied, when exiting from Reset or whenever V mand sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 4., Commands, in conjunction with the text descriptions below.

Read Memory Array Command

The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subseque nt read operations will read t he address ed lo catio n a nd out put the data. When a device Reset occurs, the memory defaults to Read mode.

Read Status Register Command

The Status Register indicates w hen a prog ram or erase operation is complete and the success or failure of the operation itself. Is sue a Read Status Register command to read the S tatus Register’s contents. Subseque nt Bus Read operations re ad the Status Register at a ny address, until anothe r command is issued . S ee Tabl e 1 1., Status Regi s-

ter Bits, for details on the definitions of the bits.

The Read Status Regist er command may be issued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will auto matically o utput the content of the Status Register.

Read Electronic Signature Command

The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register.

The Read Electronic Signature command consists of one write cycle, a subsequent read wil l output the Manufacturer Code, the Device Code, the Block Lock and L ock-Dow n Stat us, or the Pro tection and Lock Regi ster. Se e Tab les 5, 6 and 7 for the valid address.

is lower than V

LKO

. Com-

M28W640FCT, M28W640FCB

Table 3. Command Codes

Hex Code Command

01h

10h Program 20h Erase

2Fh

30h Double Word Program 40h Program 50h Clear Status Register 56h Quadruple Word Program

60h

70h Read Status Register 90h Read Electronic Signature 98h Read CFI Query

B0h Program/Erase Suspend

C0h Protection Registe r Prog ram

D0h

FFh Read Memory Array

Read CFI Query Command

The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Com mand. Once the comm and is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See APPENDIX

B., COMMON FLASH INTERFACE (CFI), Tables 26, 27, 28, 29, 30 and 31 for details on the infor-

mation contained in the Com mon Flash Interface memory area.

Block Erase Command

The Block Erase command can be used to eras e a block. It sets all the bits within the selected block to ’1’. All previous data in the bloc k is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error.

Two Bus Write cycles are required to issue the command.

■ The first bus cycle sets up the Erase

command.

Block Lock confirm

Block Lock-Down confirm

Block Lock, Block Unlock, Block LockDown

Program/Erase Resume, Block Unlock confirm

11/55

Page 12

M28W640FCT, M28W640FCB

■ The second latches the block address in the

internal state machine and starts the Program/ Erase Controller.

If the second bus cycle is not Write Erase Confirm (D0h), Status Regist er bits b4 and b5 are s et and the command aborts.

Erase aborts if Reset turns to V

. As data integrity

cannot be guaranteed when the Erase operation is aborted, the block must be erased again.

During Erase operations the memo ry will accept the Read Status Regis ter command a nd the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 8., Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See APPENDIX C., Figure 21., Erase Flowchart

and Pseudo Code, for a suggested flowc hart for

using the Erase command.

Program Command

The memory array can be programmed word-byword. Two bus write cycles ar e required to issue the Program Command.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data

to be written and starts the Program/Erase Controller.

During Program operations the memory will accept the Read Statu s Register comm and and the Program/Erase Sus pend command. Typical Program times are given in Tabl e 8., Program , Erase

Times and Program/Erase Endurance Cycles.

Programming aborts if Rese t goes to V

. As data

integrity cannot be gu aranteed wh en the p rogram operation is aborted, the block containing the memory location must be erased and reprogrammed.

See APPENDIX C., Figure 17., Program Flow-

chart and Pseudo Code, for the flowchart for using

the Program command.

Double Word Program Command

This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two wor ds must differ only for the address A0. Programm ing shoul d not be attempt ed when V

is not at V

PPH

Three bus write cy cles ar e ne ce ss ar y to i ss ue the Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and

the Data of the second word to be written and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has s tarted. Program ming aborts if Reset goes to V

. As data integrit y

cannot be guaranteed when the program operation is aborted, the blo ck containing the memory location must be erased and reprogrammed.

See APPENDIX C., Figure 18., Double Word Pro-

gram Flowchart and Pseudo Code for the flow-

chart for using the Double Word Program command.

Quadruple Word Program Command

This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The fou r words must differ on ly for the addresses A0 and A1. Programming should not be attempted when V

is not at V

PPH

Five bus write cycles are necessary to issue the Quadruple Word Program command.

■ The first bus cycle sets up the Quadruple

Word Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and

the Data of the second word to be written.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has s tarted. Program ming aborts if Reset goes to V

. As data integrit y

cannot be guaranteed when the program operation is aborted, the blo ck containing the memory location must be erased and reprogrammed.

See APPENDIX C., Figure 19., Quadruple Word

Program Flowchart and Pseudo Code, for the

flowchart for using the Q uadruple Word Program command.

Clear Status Register Command

The Clear Status Regist er co mm and ca n be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command.

The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller.

12/55

Page 13

M28W640FCT, M28W640FCB

During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, Block Lock-Down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly.

During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V Reset turns to V

. Program/Erase is aborted if

See APPENDIX C., Figure 20., Program Suspend

& Resume Flowchart and Pseudo Cod e, and Figure 22., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Pro-

gram/Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be used to restart the Program/E rase Controller after a Program/Erase Sus pend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issu ed subsequent Bus Read opera tions read th e Status Register.

See APPENDIX C., Figure 20., Program Suspend

& Resume Flowchart and Pseudo Cod e, and Figure 22., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Pro-

gram/Erase Resume command.

Protection Register Program Command

The Protection Register Program command is used to Program the 128 bit u ser One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’.

Two write cycles are re quire d to is su e th e Pr o tec tion Register Program command.

■ The first bus cycle sets up the Protection

■ The second latches the Address and the Data

to be written to the Protection Register and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has started.

The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure

6., Protection Register Memory Map). Attem pting

to program a previously protected Protection Reg-

ister will result in a Status Register error. The protection of the Protection Register is not reversible.

The Protection Register Progra m cannot be suspended.

Block Lock Command

The Block Lock comma nd is used to loc k a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset.

Two Bus Write cycles are required to issue the Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bu s Writ e cycl e latc hes t he b lock

address.

The lock status can be mo nitored for each block using the Read Electronic Signature command.

Table 10. shows the protection status after issuing

a Block Lock command. The Block Lock bits are vol atile, onc e set th ey re-

main set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation.

Block Unlock Command

The Block Unlock c ommand is used to unlock a block, allowing the block to be programmed or erased. Two Bus Wr ite cycles are required to issue the Block Unlock command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bu s Writ e cycl e latc hes t he b lock

address.

The lock status can be mo nitored for each block using the Read Electronic Signature command.

Table 10. shows the protection status after issuing

a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation.

Block Lock-Down Command

A locked block cannot be Programmed or Erased, or have its protection s tatu s cha nge d whe n W P low, V

. When WP is high, V

the Lock-Down

IH,

function is disabl ed and the locked blocks c an be individually unlocked by the Block Unlock command.

Two Bus Write cycles are required to issue the Block Lock-Down command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bu s Writ e cycl e latc hes t he b lock

address.

The lock status can be mo nitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not

13/55

Page 14

M28W640FCT, M28W640FCB

locked-down) state when the device is reset on power-down. Table 10. shows the protection sta-

Refer to the section, Block Loc king, for a deta iled explanation.

tus after issuing a Block Lock-Down command.

Table 4. Commands

Bus Write Operations

Commands

Read Memory Array

Read Status Register

Read Electronic Signature

Read CFI Query 1+ Wri t e X 98h Read QA QD Erase 2WriteX 20hWriteBA D0h

Program 2 Write X

Double Word Program

Quadruple Word Program

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

Block Lock 2 Write X 60h Write Block Unlock 2 W ri te X 60h Write Block Lock-Down 2 Wri te X 60h Write Protection

Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),

(3)

(4)

QA=Query Address, QD=Q uery Data, BA =Block Addr ess, PA=Progr am Addres s, PD=Progra m Data, PRA= Protection Re gister Address, PRD =P r otection Regi ster Data.

2. The signature addresses are listed in Tables 5, 6 and 7.

3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.

4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

1+ Write X FFh

1+ Write X 70h Read X SRD

1+ Write X 90h Read

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle

Cycles

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

RA RD

Read

(2)

IDh

40h or

Write PA PD

10h

3 Write X 30h Write PA1 PD1 Write PA2 PD2

5 W rite X 56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

1Write X 50h

1Write X B0h

1Write X D0h

01h

BA BA D0h

2Fh

2Write X C0hWrite

PRA

PRD

Table 5. Read Electronic Signature

Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-DQ15

Manufacture Code

M28W640FCT

Device Code

M28W640FCB

Note: RP = VIH.

14/55

ILVIHVIL

ILVIHVIHVIL

0 Don't Care 20h 00h

0 Don't Care 48h 88h 0 Don't Care 49h 88h

Page 15

M28W640FCT, M28W640FCB

Table 6. Read Block Lock Signature

Block Status E G W A0 A1 A2-A7 A8-A11 A12-A21 DQ0 DQ1 DQ2-DQ15

Locked Block Unlocked Block Locked-Down

Block

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Blo ck Locking section .

Table 7. Read Protection Register and Lock Register

Word E

Lock

Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 OTP 4 OTP 5 OTP 6 OTP 7

ILVILVIHVILVIH

0 Don't Care Block Address 1 0 00h 0 Don't Care Block Address 0 0 00h

0 Don't Care Block Address

(1)

1 00h

G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

ILVILVIH

VILVILV VILVILV V

ILVILVIH

VILVILV VILVILV V

ILVILVIH

VILVILV VILVILV VILVILV V

ILVILVIH

VILVILV

80h Don't Care 0

81h Don't Care ID data ID data ID data ID data ID data 82h Don't Care ID data ID data ID data ID data ID data

83h Don't Care ID data ID data ID data ID data ID data

84h Don't Care ID data ID data ID data ID data ID data 85h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta

86h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta

87h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta 88h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta

89h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta

8Ah Don' t C are OT P data OTP data OTP d ata OTP data OTP d a ta

8Bh Don' t C are OT P data OTP data OTP d ata OTP data OTP d a ta 8Ch D on't C are OTP data O TP data OTP data OT P data OTP da ta

OTP Prot.

data

000h00h

15/55

Page 16

M28W640FCT, M28W640FCB

Table 8. Program, Erase Times and Program/Erase Endurance Cycles

Parameter Test Conditions

Word Pr ogram Double Word Program Quadruple Word Program

Main Block Program

Parameter Block Program

Main Block Erase

= 12V ±5%

= V

VPP = 12V ±5%

Parameter Block Erase

= V

Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. Typical time to program a Main or Parameter Block us ing the Doubl e Word Pro gram and t he Q uadruple Word Prog ram comman ds

respectively.

M28W640FCT, M 2 8W 64 0F CB

Min Typ Max

10 200 µ s 10 200 µ s 10 200 µ s

0.16/0.08

(1)

0.32 5 s

0.02/0.01

(1)

0.04 4 s 110s 110s

0.4 10 s

Unit

16/55

Page 17

BLOCK LOCKING

The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be changed.

■ V

The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 10., defines all of the possible protection states (WP DQ1, DQ0) , and APPENDIX C., Figure 23., shows a flowchart for the locking operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6., will output the protec tion sta tus of tha t block. T he lock status is represen ted b y D Q0 and DQ 1. DQ0 indicates the Block Lock/Unlock sta tus and is set by the Lock command and cleared by the Unl ock command. It is als o au tom ati ca ll y s et when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down.

The following sections explain the operation of the locking system.

Locked State

The default status of all blo cks on po wer -up o r af ter a hardware reset is Locked (states (0,0,1) o r (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locke d block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate

≤ V

- the third level offers a complete

PPLK

hardware protection against program and erase on all blocks.

M28W640FCT, M28W640FCB

software commands. A locked block can be unlocked by issuing the Unlock command.

Lock-Dow n St a t e

Blocks that are Locked-Down (state (0,1,x))are protected from program an d erase operati ons (as for Locked blocks) but the ir prote ction stat us can not be changed using so ftware comman ds alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Lock ed state whe n the device is reset or powered-down.

The Lock-Down function is depend ent on the W P input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP

=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be i ndividually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These bl ocks can th en be reloc ked (1,1,1) and unlock ed (1,1,0) as desired whi le WP remains high. When WP is low , blocks that were previously Locked-Down re turn to the Lock-Down state (0,1,x) regardless of any changes made while WP

was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a bl oc k. T his is u se fu l in t h e c a se whe n another block needs to be updated while an erase operation is in progress.

To change block loc king during an erase operation, first write the Erase Suspend command, then check the status register unti l it indicates that the erase operation h as been suspended. Next write the desired Lock command s equence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command.

If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immedi ately, but when the er ase is resumed, the erase operation will complete.

Locking operations cann ot be perfor med during a program suspend. Re fer to APPENDIX D., Command Interface and Program/Erase Controller State, for detailed information on which commands are valid during erase suspend.

17/55

Page 18

M28W640FCT, M28W640FCB

Table 9. Block Lock Status

Item Address Data

Block Lock Configuration

Block is Unlocked DQ0=0

xx002

Block is Locked DQ0=1

Block is Locked-Down DQ1=1

Table 10. Protection Status

Allowed

(1)

After Block

Lock Command

Next Protection Status

(WP, DQ1, DQ0)

After Block

Unlock

Command

After Block Lock-

Down Command

Current Protection Status

(WP, DQ1, DQ0)

Current State

Program/Erase

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1

(2)

no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1

(2)

no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The lock status is defined by the write p rot ect pin and by DQ1 (‘1’ for a lo cked-do wn blo ck) and DQ0 ( ‘1’ f or a locked block) as read

in the Read Electronic Signature command with A1 = V

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP

3. A WP

transition to VIH on a locked block will restore the previou s DQ0 value, giving a 111 or 110.

and A0 = VIL.

(1)

status.

LOCK

After WP

transition

1,1,1 or 1,1,0

(3)

18/55

Page 19

STATUS REGISTER

The Status Register p rovides information on the current or previo us Program or Erase operati on. The various bits convey in formation and errors on the operation. To read the Status register the Read Status Register command can be issued, refer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V able or Output Ena ble must be toggled to update the latched data.

Bus Read operations from any address always read the Status Register during Program and Erase operations.

The bits in the Status R egi st er are s umm ar iz ed in

Table 11., Status Register Bits. Refer to Table 11.

in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The

Program/Erase Controller Status bit indicates whether the Program/Er as e Cont ro ller is a ct ive o r inactive. When the Program /Er as e Con troll er Sta tus bit is Low (set to ‘0’ ), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Con troller is inacti ve, and the device is ready to process a new command.

The Program/Erase Control ler Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/E ras e Contr ol le r paus es the bit is High .

During Program, Erase, op erations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes th e operation and the bit is High.

After the Program/Eras e Controller completes its operation the Erase S tatus, Program Status , V Status and Block Lock Status bits should be tested for errors.

Erase Suspend Status (Bit 6). The Erase Suspend Status bit indica tes that an Erase op eration has been suspended or is going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memor y is waitin g for a Pro gram/Erase Resume command.

The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode.

. Either Chip En-

M28W640FCT, M28W640FCB

When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase St atus bit can be used to identify if the memory has faile d to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1 ’), the Program/ Erase Controller has appli ed the maximum number of pulses to th e block and still fa iled to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con troller inactive).

Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be r eset before a new Program or Erase comm and is is su ed, otherwise the new command will appear to fail.

Program Status (Bit 4). The Progr am Status bit is used to identify a Program failure. When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con troller inactive).

Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

Status (Bit 3). The VPP Status bit can be

used to identify an invali d voltage on the V during Program and Erase operations. The V pin is only sampled at the beginning of a Program or Erase operation. Indeterminate res ults can oc cur if V

When the V age on the V when the V

becomes invalid during an operation.

Status bit is Low (set to ‘0’), the volt-

pin was sampled at a valid voltage;

Status bit is High (set to ‘1’), the V

pin has a voltage that is belo w the VPP Lockout Voltage, V

, the memory is protect ed a n d Pro-

PPLK

gram and Erase operations cannot be performed. Once set High, the V

Status bit can only be reset

Low by a Clear Status Register command or a hardware reset. If set High it should be r eset before a new Program or Erase comm and is is su ed, otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program Suspend S t atu s bit indica tes that a Program ope ration has been suspended. When the Program Suspend Status bit is High (s et to ‘1’ ), a Pr og r am/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Pro-

19/55

Page 20

M28W640FCT, M28W640FCB

gram/Erase Controller Status bit is High (Program/ Erase Controller inactive). Bit 2 is set within 5µs of the Program/Erase Susp end command being issued therefore the memory may still complete the operation rather than entering the Suspend mode.

When a Program/Erase Res ume command is issued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Protection Status bi t can be used to ide ntify if a Program or Erase operation has tried to modify the contents of a locked block.

When the Block Protect ion Status bit is Hi gh (set to ‘1’), a Program or Erase operation has been attempted on a locked block.

Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If s et Hi gh it sho uld be reset before a new command is is su ed, otherwise the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register i s reserved. Its value must be masked.

Note: Refer to APPENDIX C., FLOWCHARTS

AND PSEUDO CODES, for using the Status

Table 11. Status Register Bits

Bit Name Logic Level Definition

7 P/E.C. Status

6 Erase Suspend Status

5 Erase Status

4 Program Status

Status

2 Program Suspend Status

1 Block Protection Status

0 Reserved

Note: Logic level '1' is High, '0' is Low.

'1' Ready '0' Busy '1' Suspended '0' In progress or Completed '1' Erase Error '0' Erase Success '1' Program Error '0' Program Success

'1' '0' '1' Suspended '0' In Progress or Completed '1' Program/Erase on protected Block, Abort '0' No operation to protected blocks

Invalid, Abort

20/55

Page 21

M28W640FCT, M28W640FCB

MAXIMUM RATING

Stressing the device above the ra ting l isted in the Absolute Maximum Ratin gs table ma y cause permanent damage to the device. Thes e are stress ratings only and operation of the device at these or any other conditions abo ve those indica ted in the Operating sections of this specification is not im-

Table 12. Absolute Maximum Ratings

Symbol Parameter

BIAS

STG

LEAD

, V

DDQ

Note: 1. Depends on range.

2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assermbly), the ST ECOPACK and the European directive on Restr i ctions on Hazardous Substances (RoHS) 2002/95/EU.

Ambient Operating Temperature Temperature Under Bias – 40 125 °C Storage Tempera tur e – 55 155 °C Lead Temperature during Soldering (2) °C Input or Output Voltage – 0.6 Supply Voltage – 0.6 4.1 V Program Voltage – 0.6 13 V

(1)

plied. Exposu re to Abso lute Max imum Rati ng conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and o ther relevant quality documents.

Min Max

– 40 85 °C

Value

+0.6

DDQ

7191395 specification,

Unit

21/55

Page 22

M28W640FCT, M28W640FCB

DC AND AC PARAMETERS

This section summ arizes the operati ng and measurement conditions , and the D C an d AC charac teristics of the device. The parameters in th e DC and AC characteri stics Tabl es th at follow , are derived from tests performed under the Measure-

Table 13. Operating and AC Measurement Conditions

ment Conditions summarized in Table

13., Operating and AC Measurement Conditi ons.

Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.

M28W640FCT, M28W640FCB

Parameter

70 85 90 10

MinMaxMinMaxMinMaxMinMax

Supply Voltage

Supply Voltage (V

DDQ

VDD)

DDQ

≤

2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V

2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 V

Ambient Operating Temperature –40 85 –40 85 –40 85 –40 85 °C Load Capacitance (C

)

50 50 50 50 pF Input Rise and Fall Times 5 5 5 5 ns Input Pulse Voltages Input and Output Timing Ref.

Voltages

0 to V

DDQ

/2 V

0 to V

DDQ

/2 V

0 to V

DDQ

/2 V

0 to V

DDQ

Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit

DDQ

AI00610

DDQ

25kΩ

Units

DEVICE

UNDER

TEST

0.1µF

CL includes JIG capacitance

Table 14. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

= 0V

6pF

12 pF

OUT

Note: Sampled only, not 100% tested.

Input Capacitance Output Capacitance

22/55

25kΩ

AI00609C

Page 23

M28W640FCT, M28W640FCB

Table 15. DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

I I

DD1

DD2

DD3

DD4

DD5

PP1

PP2

PP3

PP4

PP1

PPH

PPLK

LKO

Input Leakage Current Output Leakage Current Supply Current (Read ) Supply Current (Stand-by or

Automatic Stand-by) Supply Current

(Reset)

Supply Current (Progr am )

Supply Current (Erase )

Supply Current (Program/Erase Su sp en d)

Program Current (Read or Stand-by)

Program Current (Reset)

Program Current (Program)

Program Current (Erase)

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage Program Voltage (Program or

Erase operations) Program Voltage

(Program or Erase operations)

Program Voltage (Program and Erase lock-out)

VDD Supply V ol tage (Progr am and Erase lock-out)

0V≤ V

= VSS, G = VIH, f = 5MHz

≤ V

≤V

OUT

= V

DDQ

± 0.2V,

± 0. 2V

= VSS ± 0.2V

DDQ

Program in progress

VPP = 12V ± 5%

Program in progress

= V

Erase in progress

VPP = 12V ± 5%

Erase in progress

= V

DDQ

± 0.2V,

Erase suspended

> V

≤ V

= VSS ± 0.2V

Program in progress

= 12V ± 5%

Program in progress

= V

Erase in progress

= 12V ± 5%

Erase in progress

= V

≥ 2.7V

DDQ

≥ 2.7V 0.7 V

DDQ

= 100µA, VDD = V

= V

DDQ

= –100µA, VDD = V

DDQ

= V

DDQ

min

min,

±1 µA

±10 µA

918mA

15 50 µ A

510mA

10 20 mA

520mA

10 20 mA

15 50 µ A

400 µA

15µA 15µA 110mA

15µA

310mA

15µA

–0.5 0.4 V –0.5 0.8 V

–0.4 V

DDQ

DDQ DDQ

+0.4 +0.4

0.1 V

–0.1

DDQ

1.65 3.6 V

11.4 12.6 V

V V

23/55

Page 24

M28W640FCT, M28W640FCB

Figure 9. Read AC Waveforms

tAVAV

A0-A21

tAVQV

tELQX

tGLQX

DQ0-DQ15

ADDR. VALID

CHIP ENABLE

Table 16. Read AC Characteristics

Symbol Alt Parameter

AVAV

AVQV

AXQX

EHQX

EHQZ

ELQV

ELQX

GHQX

GHQZ

GLQV

GLQX

Note: 1. Sampled only, not 100% tested.

2. G

Address Valid to Next Address Valid Min 70 85 90 100 ns

Address Valid to Output Valid Max 70 85 90 100 ns

ACC

(1)

(2)

(1)

(2)

(1)

may be delayed by up to t

Address Transition to Output Transition Min 0 0 0 0 ns

Chip Enable High to Outpu t Transition M in 0 0 0 0 ns

Chip Enable High to Outpu t Hi-Z Max 20 20 25 25 ns

Chip Enable Low to Output Valid Max 70 85 90 100 ns

Chip Enable Low to Output Transition Min 0 0 0 0 ns

Output Enable High to Output Transition Min 0 0 0 0 ns

Output Enable High to Output Hi-Z Max 20 20 25 25 ns

Output Enable Low to Output Valid Max 20 20 30 30 ns

Output Enable Low to Output Transition Min 0 0 0 0 ns

OLZ

ELQV

- t

after the falling edge of E without increas i ng t

GLQV

tELQV

tGLQV

OUTPUTS ENABLED

VALID

tEHQX

tEHQZ

tGHQX

tGHQZ

VALID

DATA VALID STANDBY

M28W640FCT, M28W640FCB

70 85 90 10

ELQV

tAXQX

AI04387

Unit

24/55

Page 25

Figure 10. Write AC Waveforms, Write Enable Controlled

M28W640FCT, M28W640FCB

AI04388

tWHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A21

tAVWH

tWHGL

tELQV

tWHEL

tQVWPL

STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

tELWL tWHEH

tVPHWH

SET-UP COMMAND CONFIRM COMMAND

tWPHWH

tWHWL

tWHDX

tWLWH

tDVWH

DQ0-DQ15 COMMAND CMD or DATA

25/55

Page 26

M28W640FCT, M28W640FCB

Table 17. Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

AVAV

AVWH

DVWH

ELWL

ELQV

QVVPL

QVWPL

VPHWH

WHAX

WHDX

WHEH

WHEL

WHGL

WHWL

WLWH

WPHWH

Note: 1. Sampled only, not 100% tested.

2. A p pl i cable if V

(1,2)

(1)

Write Cycle Time M in 7 0 8 5 90 100 ns

Address Valid to Write Enable High Min 45 45 50 50 ns

Data Valid to Write Enable High Min 45 45 50 50 ns

Chip Enable Low to Write Enable Low Min 0 0 0 0 ns

Chip Enable Low to Output Valid Min 70 85 90 100 ns Output Valid to VPP Low

Min 0 0 0 0 ns

Output Valid to Write Protect Low Min 0 0 0 0 ns

VPSVPP

High to Write Enable High

Min 200 200 200 200 ns

Write Enable High to Address Transition Min 0 0 0 0 ns Write Enable High to Data Transition Min 0 0 0 0 ns Write Enable High to Chip Enabl e High Min 0 0 0 0 ns Write Enable High to Chip Enabl e Low M in 2 5 2 5 30 30 ns Write Enable High to Output Ena ble Low Min 20 20 30 30 ns

Write Enable High to Write Enable Low M in 2 5 2 5 30 30 ns

WPH

Write Enable Low to Write Enable High Min 45 45 50 50 ns

Write Protect High to Write Enable High M in 4 5 4 5 50 50 ns

is seen as a logic input (VPP < 3.6V).

M28W640FCT, M28W640FCB

Unit

70 85 90 10

26/55

Page 27

Figure 11. Write AC Waveforms, Chip Enable Controlled

M28W640FCT, M28W640FCB

AI04389

tEHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A21

tAVEH

tEHGL

tELQV

tQVWPL

CMD or DATA STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

CONFIRM COMMAND

tWLEL tEHWH

tVPHEH

POWER-UP AND

SET-UP COMMAND

tWPHEH

tEHEL

tEHDX

tELEH

tDVEH

DQ0-DQ15 COMMAND

27/55

Page 28

M28W640FCT, M28W640FCB

Table 18. Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

AVAV

AVEH

DVEH

EHAX

EHDX

EHEL

EHGL

EHWH

ELEH

ELQV

QVVPL

QVWPL

VPHEH

WLEL

WPHEH

Note: 1. Sampled only, not 100% tested.

2. A p pl i cable if V

(1,2)

(1)

Write Cycle Time Min708590100ns

Address Valid to Chip Enable High Min 45 45 50 50 ns

Data Valid to Chip Enable High Min 45 45 50 50 ns

Chip Enable High to Addre ss

Transition

Chip Enable High to Data Transition M in 0 0 0 0 ns

Chip Enable High to Chip Ena bl e Low Min 25 25 30 30 ns

CPH

Chip Enable High to Outpu t Ena ble Low

Chip Enable High to Write Enable High M in 0 0 0 0 ns

Chip Enable Low to Chip Enable High Min 45 45 50 50 ns

Min0000ns

Min25253030ns

Chip Enable Low to Output Valid Min 70 85 90 100 ns Output Valid to VPP Low

Min0000ns

Data Valid to Write Protect Low Min 0 0 0 0 ns

VPSVPP

High to Chip Enable High

Min 200 200 200 200 ns

Write Enable Low to Chip Enable Low Min 0 0 0 0 ns Write Protect High to Chip Enable High Min 45 45 50 50 ns

is seen as a logic input (VPP < 3.6V).

M28W640FCT, M28W640FCB

Unit

70 85 90 10

28/55

Page 29

Figure 12. Power-Up and Reset AC Waveforms

E, G

tPHWL

tPHEL tPHGL

M28W640FCT, M28W640FCB

tPHWL

tPHEL

tPHGL

tVDHPH

VDD, VDDQ

Power-Up Reset

Table 19. Power-Up and Reset AC Characteristics

Symbol Parameter Test Condition

PHWL

PHEL

PHGL

PLPH

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

Reset High to Write Enable Low, Chip Enable Low, Output Enable Low

(1,2)

Reset Low to Reset High Min 100 100 100 100 ns

(3)

Supply Voltages High to Reset High Min 50 50 50 50 µs

2. Sampled only, not 100% tested.

3. It is important to assert RP

in order to allow proper CPU initialization during power up or reset.

During Pr ogram

and Erase

others Min 30 30 30 30 ns

< 100ns.

PLPH

tPLPH

AI03537b

M28W640FCT, M28W640FCB

Unit

70 85 90 10

Min 50 50 50 50 µ s

29/55

Page 30

M28W640FCT, M28W640FCB

PACKAGE MECHANICAL

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

DIE

LA1 α

Note: Drawing is not to scale.

TSOP-G

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039 D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953 E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276 L1 0.800 0.0315

α 3° 0° 5° 3° 0° 5°

millimeters inches

30/55

Page 31

M28W640FCT, M28W640FCB

Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline

E1E

BALL "A1"

Note: Drawing is not to scale.

ddd

BGA-Z34

Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472 A1 0.260 0.0102 A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.390 6.290 6.490 0.2516 0.2476 0.2555

D1 5.250 – – 0.2067 – –

ddd 0.100 0.0039

E 10.500 10.400 10.600 0.4134 0.4094 0.4173 E1 3.750 – – 0.1476 – –

e 0.750 – – 0.0295 – – FD 0.570 – – 0.0224 – – FE 3.375 – – 0.1329 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – –

millimeters inches

31/55

Page 32

M28W640FCT, M28W640FCB

Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package)

87654321

AI04390

Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package)

87654321

START

POINT

END

POINT

32/55

AI04391

Page 33

M28W640FCT, M28W640FCB

PART NUMBERING

Table 22. Ordering Information Scheme

Example: M28W640FCT 90 N 6 T

Device Type

M28

Operating Voltage

W = VDD = 2.7V to 3.6V; V

Device Function

640FC = 64 Mbit (4 Mb x16), Boot Block, 0.13µm

Array Matrix

T = Top Boot B = Bottom Boot

Speed

70 = 70ns 85 = 85ns 90 = 90ns 10 = 100ns

= 1.65V to 3.6V

DDQ

Package

N = TSOP48: 12 x 20 mm ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

Blank = Standard Package T = Tape & Reel Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing

33/55

Page 34

M28W640FCT, M28W640FCB

Table 23. Daisy Chain Ordering Scheme

Example: M28W640FC -ZB T

Device Type

M28W640FC

Daisy Chain

-ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch

Option

Blank = Standard Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing, 24mm T = Tape & Reel Packing, 24mm

Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.

34/55

Page 35

APPENDIX A. BLOCK ADDRESS TABLE S

M28W640FCT, M28W640FCB

Table 24. Top Boot Block Addresses, M28W640FCT

0 4 3FF000-3FFFFF 1 4 3FE000-3FEFFF 2 4 3FD000-3FDFFF 3 4 3FC000-3FCFFF 4 4 3FB000-3FBFFF 5 4 3FA000-3FAFFF 6 4 3F9000-3F9FFF 7 4 3F8000-3F8FFF 8 32 3F0000-3F7FFF 9 32 3E8000-3EFFFF

10 32 3E0000-3E7FFF

11 32 3D8000-3DFFFF 12 32 3D0000-3D7FFF 13 32 3C8000-3CFFFF 14 32 3C0000-3C7FFF 15 32 3B8000-3BFFFF 16 32 3B0000-3B7FFF 17 32 3A8000-3AFFFF 18 32 3A0000-3A7FFF 19 32 398000-39FFFF 20 32 390000-397FFF 21 32 388000-38FFFF 22 32 380000-387FFF 23 32 378000-37FFFF 24 32 370000-377FFF 25 32 368000-36FFFF 26 32 360000-367FFF 27 32 358000-35FFFF 28 32 350000-357FFF 29 32 348000-34FFFF 30 32 340000-347FFF 31 32 338000-33FFFF 32 32 330000-337FFF 33 32 328000-32FFFF 34 32 320000-327FFF 35 32 318000-31FFFF 36 32 310000-317FFF 37 32 308000-30FFFF 38 32 300000-307FFF 39 32 2F8000-2FFFFF

Size

(KWord)

Address Range

40 32 2F0000-2F7FFF 41 32 2E8000-2EFFFF 42 32 2E0000-2E7FFF 43 32 2D8000-2DFFFF 44 32 2D0000-2D7FFF 45 32 2C8000-2CFFFF 46 32 2C0000-2C7FFF 47 32 2B8000-2BFFFF 48 32 2B0000-2B7FFF 49 32 2A8000-2AFFFF 50 32 2A0000-2A7FFF 51 32 298000-29FFFF 52 32 290000-297FFF 53 32 288000-28FFFF 54 32 280000-287FFF 55 32 278000-27FFFF 56 32 270000-277FFF 57 32 268000-26FFFF 58 32 260000-267FFF 59 32 258000-25FFFF 60 32 250000-257FFF 61 32 248000-24FFFF 62 32 240000-247FFF 63 32 238000-23FFFF 64 32 230000-237FFF 65 32 228000-22FFFF 66 32 220000-227FFF 67 32 218000-21FFFF 68 32 210000-217FFF 69 32 208000-20FFFF 70 32 200000-207FFF 71 32 1F8000-1FFFFF 72 32 1F0000-1F7FFF 73 32 1E8000-1EFFFF 74 32 1E0000-1E7FFF 75 32 1D8000-1DFFFF 76 32 1D0000-1D7FFF 77 32 1C8000-1CFFFF 78 32 1C0000-1C7FFF 79 32 1B8000-1BFFFF 80 32 1B0000-1B7FFF 81 32 1A8000-1AFFFF

Size

(KWord)

Address Range

35/55

Page 36

M28W640FCT, M28W640FCB

82 32 1A0000-1A7FFF 83 32 198000-19FFFF 84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF 92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF 95 32 138000-13FFFF 96 32 130000-137FFF 97 32 128000-12FFFF 98 32 120000-127FFF 99 32 118000-11FFFF

100 32 110000-117FFF 101 32 108000-10FFFF 102 32 100000-107FFF 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF 108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF 110 32 0C0000-0C7FFF

111 32 0B8000-0BFFFF 112 32 0B0000-0B7FFF 113 32 0A8000-0AFFFF 114 32 0A0000-0A7FFF 115 32 098000-09FFFF 116 32 090000-097FFF 117 32 088000-08FFFF 118 32 080000-087FFF 119 32 078000-07FFFF 120 32 070000-077FFF 121 32 068000-06FFFF 122 32 060000-067FFF 123 32 058000-05FFFF 124 32 050000-057FFF 125 32 048000-04FFFF

Size

(KWord)

Address Range

126 32 040000-047FFF 127 32 038000-03FFFF 128 32 030000-037FFF 129 32 028000-02FFFF 130 32 020000-027FFF 131 32 018000-01FFFF 132 32 010000-017FFF 133 32 008000-00FFFF 134 32 000000-007FFF

Size

(KWord)

Address Range

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Page 37

M28W640FCT, M28W640FCB

Table 25. Bottom Boot Block Addresses, M28W640FCB

134 32 3F8000-3FFFFF 133 32 3F0000-3F7FFF 132 32 3E8000-3EFFFF 131 32 3E0000-3E7FFF 130 32 3D8000-3DFFFF 129 32 3D0000-3D7FFF 128 32 3C8000-3CFFFF 127 32 3C0000-3C7FFF 126 32 3B8000-3BFFFF 125 32 3B0000-3B7FFF 124 32 3A8000-3AFFFF 123 32 3A0000-3A7FFF 122 32 398000-39FFFF 121 32 390000-397FFF 120 32 388000-38FFFF 119 32 380000-387FFF 118 32 378000-37FFFF 117 32 370000-377FFF 116 32 368000-36FFFF 115 32 360000-367FFF 114 32 358000-35FFFF 113 32 350000-357FFF 112 32 348000-34FFFF

111 32 340000-347FFF 110 32 338000-33FFFF 109 32 330000-337FFF 108 32 328000-32FFFF 107 32 320000-327FFF 106 32 318000-31FFFF 105 32 310000-317FFF 104 32 308000-30FFFF 103 32 300000-307FFF 102 32 2F8000-2FFFFF 101 32 2F0000-2F7FFF 100 32 2E8000-2EFFFF

99 32 2E0000-2E7FFF 98 32 2D8000-2DFFFF 97 32 2D0000-2D7FFF 96 32 2C8000-2CFFFF 95 32 2C0000-2C7FFF 94 32 2B8000-2BFFFF 93 32 2B0000-2B7FFF

Size

(KWord)

Address Range

92 32 2A8000-2AFFFF 91 32 2A0000-2A7FFF 90 32 298000-29FFFF 89 32 290000-297FFF 88 32 288000-28FFFF 87 32 280000-287FFF 86 32 278000-27FFFF 85 32 270000-277FFF 84 32 268000-26FFFF 83 32 260000-267FFF 82 32 258000-25FFFF 81 32 250000-257FFF 80 32 248000-24FFFF 79 32 240000-247FFF 78 32 238000-23FFFF 77 32 230000-237FFF 76 32 228000-22FFFF 75 32 220000-227FFF 74 32 218000-21FFFF 73 32 210000-217FFF 72 32 208000-20FFFF 71 32 200000-207FFF 70 32 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF 65 32 1D0000-1D7FFF 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 61 32 1B0000-1B7FFF 60 32 1A8000-1AFFFF 59 32 1A0000-1A7FFF 58 32 198000-19FFFF 57 32 190000-197FFF 56 32 188000-18FFFF 55 32 180000-187FFF 54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF 49 32 150000-157FFF

Size

(KWord)

Address Range

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Page 38

M28W640FCT, M28W640FCB

48 32 148000-14FFFF 47 32 140000-147FFF 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF 22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF 17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF

11 32 020000-027FFF

10 32 018000-01FFFF

9 32 010000-017FFF 8 32 008000-00FFFF 7 4 007000-007FFF 6 4 006000-006FFF 5 4 005000-005FFF

Size

(KWord)

Address Range

4 4 004000-004FFF 3 4 003000-003FFF 2 4 002000-002FFF 1 4 001000-001FFF 0 4 000000-000FFF

Size

(KWord)

Address Range

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Page 39

M28W640FCT, M28W640FCB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the de vice to de termine various electrical a nd timing parameters, density information and functions su pported by the mem ory. The system can interface easily with the device, enabling the so ftwar e to u pgr ade it se lf wh en necessary.

When the CFI Query Comma nd (RCFI) is issued the device enters CFI Query mode and the data

Table 26. Query Structure Overview

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information 10h CF I Que ry Ide nt ific atio n String Command set ID and algo rith m data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

Note: Query data are always presented on the lowest order data outputs.

structure is read fro m th e me mor y. T abl es 26, 27,

28, 29, 30 and 31 show the addresses used to re-

trieve the data. The CFI data structure also contains a security

area where a 64 bit unique security number is written (see Table 31., Security Code Area). This area can be accessed onl y in Read mode by the final user. It is imposs ible to chang e the secur ity num ber after it has been written b y ST. Issu e a Read command to return to Read mode.

Additional information specific to the Primary Algorithm (optional)

Additional information specific to the Alternate Algorithm (optional)

Table 27. CFI Query Identification Stri ng

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h

02h-0Fh reserved Reserved

10h 0051h "Q" 11h 0052h Query Unique ASCII String "QRY" "R" 12h 0059h "Y" 13h 0003h 14h 0000h 15h 0035h 16h 0000h 17h 0000h 18h 0000h 19h 0000h

1Ah 0000h

Note: Query data are always presented on the lowes t order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

8848h 8849h

Device Code

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 29.)P = 35h

Alternate Vendor Command Set and Control Interface ID Code second vendor specified algorithm supported (0000h means none exists)

Address for Alternate Algorithm extended Query table (0000h means none exists)

compatible

Top

Bottom

Intel

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Page 40

M28W640FCT, M28W640FCB

Table 28. CFI Query System Interface Information

Offset Data Description Value

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0027h

1Ch 0036h

1Dh 00B4h

1Eh 00C6h

bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV

2.7V

3.6V

11.4V

12.6V

1Fh 0004h 20h 0004h 21h 000Ah 22h 0000h 23h 0005h 24h 0005h 25h 0003h 26h 0000h

Typical time-out per single word program = 2n µs Typical time-out for Double/Quadruple Word Program = 2 Typical time-out per individual block erase = 2 Typical time-out for full chip erase = 2

Maximum time-out for Word program = 2

times typical

Maximum time-out for Double/Quadruple Word Program = 2 Maximum time-out per individual block erase = 2 Maximum time-out for chip erase = 2

times typical

µs

times typical

16µs 16µs

NA 512µs 512µs

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Page 41

Table 29. Device Geometry Definition

Offset Word

Mode

27h 0017h 28h

29h

2Ah 2Bh

2Ch 0002h

2Dh 2Eh

2Fh 30h

31h 32h

M28W640FCT

33h 34h

2Dh 2Eh

2Fh 30h

31h 32h

M28W640FCB

33h 34h

Data Description Value

Device Size = 2

0001h 0000h

0003h 0000h

007Eh 0000h

0000h 0001h

0007h 0000h

0020h 0000h

0007h 0000h

0020h 0000h

007Eh 0000h

0000h 0001h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2 Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous Erase Blocks of the same size.

Region 1 Information Number of identical-size erase block = 007Eh+1

Region 1 Information Block size in Region 1 = 0100h * 256 byte

Region 2 Information Number of identical-size erase block = 0007h+1

Region 2 Information Block size in Region 2 = 0020h * 256 byte

Region 1 Information Number of identical-size erase block = 0007h+1

Region 1 Information Block size in Region 1 = 0020h * 256 byte

Region 2 Information Number of identical-size erase block = 007Eh=1

Region 2 Information Block size in Region 2 = 0100h * 256 byte

in number of bytes

M28W640FCT, M28W640FCB

8 MByte

x16

Async.

127

64 KByte

8 KByte

127

64 KByte

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M28W640FCT, M28W640FCB

Table 30. Primary Algorithm-Specific Extended Query Table

Offset

P = 35h

(1)

(P+0)h = 35h 0050h (P+1)h = 36h 0052h "R" (P+2)h = 37h 0049h "I" (P+3)h = 38h 0031h Major version number, ASCII "1"

(P+4)h = 39h 0030h Minor version number, ASCII "0" (P+5)h = 3Ah 0066h Extended Query table contents for Primary Algorithm. Address (P+5)h (P+6)h = 3Bh 0000h (P+7)h = 3Ch 0000h (P+8)h = 3Dh 0000h

(P+9)h = 3Eh 0001h Su pp ort ed Func tio ns after Susp end

(P+A)h = 3Fh 0003h Block Lock Status (P+B)h = 40h 0000h

(P+C)h = 41h 0030h V

(P+D)h = 42h 00C0h V

(P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space.

(P+F)h = 44h 0080h Protection Field 1: Protection De sc ript ion

(P+10)h = 45h 0000h 00h (P+11)h = 46h 0003h 8 Byte (P+12)h = 47h 0004h 16 Byte

(P+13)h = 48h Reserved

Note: 1. See Table 27., offset 15 for P pointer definition.

Data Description Value

"P"

Primary Algorithm extended Query table unique ASCII string “PRI”

contains less significant by te.

bit 0Chip Erase supported(1 = Yes, 0 = No) bit 1Suspend Erase supported(1 = Yes, 0 = No) bit 2Suspend Program supported(1 = Yes, 0 = No) bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4Queued Erase supported(1 = Yes, 0 = No) bit 5Instant individual block locking supported(1 = Yes, 0 = No) bit 6Protection bits supported(1 = Yes, 0 = No) bit 7Page mode read supported(1 = Yes, 0 = No) bit 8Synchronous read supported(1 = Yes, 0 = No) bit 31 to 9Reserved; undefined bits are ‘0’

No Yes Yes

Read Array, Read Status Register and CFI Query are always supported during Erase or Program oper ati on

bit 0Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1Reserved; undefined bits are ‘0’ Yes

Defines which bits in the Block Status Register section of the Query are implemented. Address (P+A)h contains less significant byte

bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No) bit 1Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

Yes Yes

bit 15 to 2Reserved for future use; undefined bits are ‘0’

Logic Supply Optimum Program/Erase voltage (highest performance)

3V bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV

Supply Optimum Program/Erase voltage

12V bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV

"00h," indicates that 256 protection bytes are available

80h

This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device unique serial numbers. Others are user programmable. Bits 0–15 point to the Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15Lock/bytes JEDEC-plane physical high address bit 16 to 23 "n" such that 2n = factory pre-programmed bytes

bit 24 to 31 "n" such that 2

= user programmable bytes

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Page 43

Table 31. Security Code Area

Offset Data Description

80h 00XX Protection Register Lock 81h XXXX 82h XXXX 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX

89h XXXX 8Ah XXXX 8Bh XXXX 8Ch XXXX

64 bits: unique device number

128 bits: User Programmable OTP

M28W640FCT, M28W640FCB

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M28W640FCT, M28W640FCB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 17. Program Flowchart and Pseudo Code

Start

Write 40h or 10h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

VPP Invalid

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Eras e Controller operations.

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Page 45

Figure 18. Double Word Program Flowchart and Pseudo Code

Start

M28W640FCT, M28W640FCB

Write 30h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

YES

b1 = 0

YES

End

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03539b

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M28W640FCT, M28W640FCB

Figure 19. Quadruple Word Program Flowchart and Pseudo Code

Start

Write 56h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Write Address 3

& Data 3 (3)

Write Address 4

& Data 4 (3)

Read Status

b7 = 1

YES

quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (any_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */

writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */

/*Memory enters read status state after the Program command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

b3 = 0

b4 = 0

b1 = 0

End

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

YES

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI06233

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Page 47

M28W640FCT, M28W640FCB

Figure 20. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

Write B0h

Write 70h

Read Status

writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ;

/* read status register to check if program has already completed */

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

b7 = 1

YES

b2 = 1

YES

Write FFh

Read data from

another address

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } }

AI03540b

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Page 48

M28W640FCT, M28W640FCB

Figure 21. Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block

Address & D0h

erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after

the Erase Command */

Read Status

b7 = 1

YES

b3 = 0

YES

b4, b5 = 1

b5 = 0

YES

b1 = 0

YES

End

YES

VPP Invalid

Error (1)

Command

Sequence Error (1)

Erase Error (1)

Erase to Protected

Block Error (1)

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;

if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations .

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Page 49

Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code

Start

M28W640FCT, M28W640FCB

Write B0h

Write 70h

Read Status

b7 = 1

b6 = 1

Write FFh

Read data from

another block

Program/Protection Program

Block Protect/Unprotect/Lock

or or

Write D0h

Erase Continues

YES

Erase Complete

Write FFh

Read Data

erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }

AI03542b

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Page 50

M28W640FCT, M28W640FCB

Figure 23. Locking Operations Flowchart and Pseudo Code

Start

Write 60h

Write

01h, D0h or 2Fh

Write 90h

Read Block Lock States

Locking change

confirmed?

YES

Write FFh

End

locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ }

AI04364

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M28W640FCT, M28W640FCB

Figure 24. Protection Register Program Flowchart and Pseudo Code

Start

Write C0h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

VPP Invalid

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI04381

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Eras e Controller operations.

51/55

Page 52

M28W640FCT, M28W640FCB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 32. Write State Machine Current/Next, sheet 1 of 2.

Current

State

Read Array “1” Array Read Array Prog.Setup Ers. Setup Read Array Read Sts. Read Array

Read

Status

Read

Elect.Sg.

Read CFI

Query

Lock Setup “1” Status Lock Command Error

Lock Cmd

Error Lock

(complete)

Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog. (complete)

Prog. Setup “1” Status Program

Program

(continue)

Prog. Sus

Status

Prog. Sus

Read Array

Prog. Sus

Read

Elect.Sg.

Prog. Sus Read CFI

Program

(complete)

Erase Setup

Erase

Cmd.Error

Erase

(continue)

Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read

Elect.Sg.

Erase Sus

Read CFI

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program , Prot = Protection, Sus = Suspend.

bit 7

Data

When

Read

“1” Status Read Array

Electronic

“1”

Signature

“1” CFI Read Array

“1” Status Read Array

“1” Status Protectio n R e gi s t er Pr o g ra m

“0” Status Protection Register Program continue

“1” Status Read Array

“0” Status Program (continue)

“1” Status

“1” Array

Electronic

“1”

Signature

“1” CFI

“1” Status Read Array

“1” Status Erase Command Error

“1” Status Read Array

“0” Status Erase (continue)

“1” Status

“1” Array

Electronic

“1”

Signature

“1” CFI

“1” Status Read Array

Read Array (FFh)

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

(10/40h)

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Command Input (and Next State)

Erase Setup

(20h)

Erase Setup

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Setup

Erase

Confirm

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Prog/Ers Suspend

(B0h)

Read Array

Lock Cmd

Error

Read Array

Prog. Sus

Read Sts

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array Read Array

Erase

CmdError

Read Array

Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array Read Array

Prog/Ers

Resume

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Read

Status

(70h)

Read

Status

Read

Status

Read

Status

Lock Command Error

Read

Status

Read

Status

Read

Status

Program (continue)

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Read

Status

Erase Command Error

Read

Status

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Sts

Erase Sus

Read Sts

Erase Sus

Read Sts

Read

Status

Read Array

Read Array Read Array

Read Array

Read Array Read Array

Clear

Status

(50h)

Prog. Sus

Erase Sus

52/55

Page 53

M28W640FCT, M28W640FCB

Table 33. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Current State

Read Array Read Elect.Sg. Read CFI Query Lock Setup

Read Status Read Elect.Sg. Read CFI Query Lock Setup

Read Elect.Sg. Read Elect.Sg. Read CFI Query Lock Setup

Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup

Lock Setup Lock Command Error Lock (complete)

Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup

Lock (complete) Read Elect.Sg. Read CFI Query Lock Setup

Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog. (complete)

Prog. Setup Program

Program

(continue)

Prog. Suspend

Read Status

Prog. Suspend

Read Array

Prog. Suspend Read Elect.Sg.

Prog. Suspend

Read CFI

Program

(complete)

Erase Setup Erase Command Error

Erase

Cmd.Error

Erase (continue) Erase (continue)

Erase Suspend

Read Ststus

Erase Suspend

Read Array

Erase Suspend

Read Elect.Sg.

Erase Suspend

Read CFI Query

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

Read Elect.Sg.

(90h)

Read Elect.Sg. Read CFI Query Lock Setup

Prog. Suspend Read Elect.Sg.

Read Elect.Sg. Read CFIQuery Lock Setup

Read Elect.Sg. Read CFI Query Lock Setup

Erase Suspend Read Elect.Sg.

Read Elect.Sg. Read CFI Query Lock Setup

Read CFI

Query

(98h)

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Lock Setup

(60h)

Protection Register Program

Protection Register Program (continue)

Lock Setup Erase Suspend Read Array

Prot. Prog.

Setup (C0h)

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Program (continue)

Program Suspend Read Array

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Lock Confirm

(01h)

Confirm (2Fh)

Lock Down

Read Array

Unlock

Confirm

(D0h)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

53/55

Page 54

M28W640FCT, M28W640FCB

REVISION HISTORY

Table 34. Document Revision History

Date Version Revision Details

24-May-2004 0.1 First Issue

23-Aug-2004 0.2

08-Apr-2005 1.0

Figure 3., TSOP Connections and Figure 4., TFBGA Connectio ns ( T op v i ew t hr o ug h package) updated .

Datasheet maturity changed to PRELIMINARY DATA. TSOP48 Package Mechanical Data updated in Table 20., TSOP48 - 48 lead Plastic

Thin Small Outline, 12 x 20mm, Package Mechanical Data.

54/55

Page 55

M28W640FCT, M28W640FCB

Information furnished is be lieved to be a ccur ate and reli able. Howe ver, STMicroele ctronic s assu mes no r esponsib ilit y for th e consequences of use of such information nor for any infrin gement of patent s or other rights of third parties which ma y result from it s use. No license is granted

by implication or otherwi se under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication ar e subject

to change without not ice. This pub licat ion su persed es and repl aces all in format ion previou sly su pplie d. STMicroele c tronic s prod ucts ar e no t

authorized for use as critical compone nts in life support devices or systems without express written approval of STMicroele ct ronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics .

All other names are the property of their respective owners

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israe l - It aly - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

STMicroelectronics group of companies

www.st.com

55/55

Datasheet M28W640FCT, M28W640FCB Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES SUMMARY

Figure 1. Packages

SUMMARY DESCRIPTION

Figure 2. Logic Diagram

Table 1. Signal Names

Figure 3. TSOP Connections

Figure 4. TFBGA Connections (Top view through package)

Figure 5. Block Addresses

Figure 6. Protection Register Memory Map

SIGNAL DESCRIPTIONS

ed to this device. Address Inputs (A0-A21). The Address Inputs

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be progra mmed d uring a Write Bus operation.

BUS OPERATIONS

exiting Reset or after power-up. Write. Bus Write oper ations write Commands to

Output Disable. The data outputs are high im­pedance when the Output Enable is at V

Standby. Standby disables most o f the internal circuitry allowing a substantial reduction of the cur­rent consumption. The memory is in stand-by when Chip Enable is at V

vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro-

Reset. During Reset mode w hen Output E nable is Low, V

Table 2. Bus Operations

COMMAND INTERFACE

Read Memory Array Command

Read Status Register Command

Read Electronic Signature Command

Table 3. Command Codes

Read CFI Query Command

Block Erase Command

Program Command

Double Word Program Command

Quadruple Word Program Command

Clear Status Register Command

Program/Erase Suspend Command

Program/Erase Resume Command

Protection Register Program Command

Block Lock Command

Block Unlock Command

Block Lock-Down Command

Table 4. Commands

Table 5. Read Electronic Signature

Table 6. Read Block Lock Signature

Table 7. Read Protection Register and Lock Register

Table 8. Program, Erase Times and Program/Erase Endurance Cycles

BLOCK LOCKING

Reading a Block’s Lock Status

Locked State

Unlocked State

Lock-Dow n St a t e

Locking Operations During Erase Suspend

Table 9. Block Lock Status

Table 10. Protection Status

STATUS REGISTER

Table 11. Status Register Bits

MAXIMUM RATING

Table 12. Absolute Maximum Ratings

DC AND AC PARAMETERS

Table 13. Operating and AC Measurement Conditions

Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit

Table 14. Capacitance

Table 15. DC Characteristics

Figure 9. Read AC Waveforms

Table 16. Read AC Characteristics

Figure 10. Write AC Waveforms, Write Enable Controlled

Table 17. Write AC Characteristics, Write Enable Controlled

Figure 11. Write AC Waveforms, Chip Enable Controlled

Table 18. Write AC Characteristics, Chip Enable Controlled

Figure 12. Power-Up and Reset AC Waveforms

Table 19. Power-Up and Reset AC Characteristics

PACKAGE MECHANICAL

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline

Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data

Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package)

Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package)

PART NUMBERING

Table 22. Ordering Information Scheme

Table 23. Daisy Chain Ordering Scheme

Output Disable. The data outputs are high impedance when the Output Enable is at V

Standby. Standby disables most o f the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at V