ST M28W640FCT, M28W640FCB User Manual
FEATURES SUMMARY
■ SUPPLY VOLTAGE
–V
–V
–V
■ ACCESS TIME: 70, 85, 90,100ns
■ PROGRAMMING TIME:
– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option
■ COMMON FLASH INTERFACE
■ MEMORY BLOCKS
– Parameter Blocks (Top or Bottom
– Main Blocks
■ BLOCK LOCKING
– All blocks locked at Power Up
– Any combination of blocks can be locked
–WP
■ SECURITY
– 128 bit user Programmable OTP cells
– 64 bit unique device identifier
■ AUTOMATIC STAND-BY MODE
■ PROGRAM and ERASE SUSPEND
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M28W640FCT: 8848h
– Bottom Device Code, M28W640FCB:
■ PACKAGES
– Compliant with Lead-Free Soldering
– Lead-Free Versions
= 2.7V to 3.6V Core Power Supply
DD
= 1.65V to 3.6V for Input/Output
DDQ
= 12V for fast Program (optional)
PP
location)
for Block Lock-Down
8849h
Processes
M28W640FCT
M28W640FCB
64 Mbit (4Mb x16, Boot Block)
3V Supply Flash Memory
PRELIMINARY DATA
Figure 1. Packages
FBGA
TFBGA48 (ZB)
6.39 x 10.5mm
TSOP48 (N)
12 x 20mm
April 2005
This is preliminary information on a new product no w in developmen t or undergoi ng evaluatio n. Details are subje ct to chan ge without no tic e.
1/55
M28W640FCT, M28W640FCB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E
Output Enable (G
Write Enable (W
Write Protect (WP
Reset (RP
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DD
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
DDQ
V
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PP
V
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/55
M28W640FCT, M28W640FCB
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 6. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Program, Erase Times and Program/Erase Endurance Cycles
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . 16
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
V
Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PP
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 16. Read AC Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/55
M28W640FCT, M28W640FCB
Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 19. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 30
Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 30
Figure 14.TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline 31
Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 31
Figure 15.TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 32
Figure 16.TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 23. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Top Boot Block Addresses, M28W640FCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 25. Bottom Boot Block Addresses, M28W640FCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 27. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 28. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 30. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 31. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 18.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 19.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 47
Figure 21.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 22.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 23.Locking Operations Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 24.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . . 52
Table 32. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4/55
SUMMARY DESCRIPTION
The M28W640FCT and M28W640FCB are 64
Mbit (4 Mbit x 16) non-volatile Flash memories that
can be erased electricall y at block level and programmed in-system on a Word-by-Word basis using a 2.7V to 3.6V V
a 1.65V to 3.6V V
pins. An optional 12V V
ed to speed up customer programming.
The devices fe ature an asymmetric al blocked architecture. They have an array of 135 blocks: 8
Parameter Blocks of 4 KWord and 127 Main
Blocks of 32 KWord. The M28W640FCT has the
Parameter Blocks at the top of the memory address space while the M28 W640FCB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 5., Block Ad-
dresses.
The M28W640FCT and M28W640FCB feature an
instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant c ode and data protection.
All blocks have three levels of protection. They can
be locked and locked-down individually preventing
any accidental program ming or erasure. There i s
an additional hardware protection against program
and erase. When V
tected against program or erase. All blocks are
locked at Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be susp ended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includ es a 192 bi t Protecti on Registe r
to increase the protection of a system design. The
Protection Register is divided into a 64 bit segment
and a 128 bit segment. Th e 64 bit segment contains a unique device number written by ST, while
the second one is one-time-pr ogrammabl e by the
user. The user programmable segment can be
permanently protected. Figure 6., shows the Protection Register Memory Map.
Program and Erase co mmands are writte n to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation c an be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The memory is offered i n TSOP48 (12 X 20mm)
and TFBGA48 (6.39 x 10.5mm, 0.75mm pitch)
packages and is su pplied with all the bi ts erased
(set to ’1’).
supply for the circuitry and
DD
supply for the Input/Out put
DDQ
power supply is provid-
PP
PP
≤ V
all blocks are pro-
PPLK
M28W640FCT, M28W640FCB
In addition to the standard version, the pac kages
are also available in Lead-free version, in compliance with JEDEC St d J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free soldering processes.
Figure 2. Logic Diagram
V
V
DDQVPP
DD
22
A0-A21
W
E
G
RP
WP
M28W640FCT
M28W640FCB
V
SS
Table 1. Signal Names
A0-A21 Address Inputs
DQ0-DQ15 Data Input/Output
E
G
W
RP
WP
V
DD
V
DDQ
V
PP
V
SS
NC Not Connected Inter na lly
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
Core Power Supply
Power Supply for
Input/Output
Optional Supply Voltage for
Fast Program & Erase
Ground
16
DQ0-DQ15
AI09903
5/55
M28W640FCT, M28W640FCB
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
1
48
A16
V
DDQ
V
SS
DQ15
DQ7
A10 DQ14
A21
A20
RP
V
PP
WP
A19
A18
A17
A9
A8
W
A7
A6
A5
A4
A3
A2
A1
12
M28W640FCT
M28W640FCB
13
24 25
AI09904b
37
36
DQ6
DQ13
DQ5
DQ12
DQ4
V
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SSQ
E
A0
6/55
Figure 4. TFBGA Connections (Top view through package)
M28W640FCT, M28W640FCB
87654321
A
B
C
D
E
F
V
A13
A14
DDQ
SS
DQ15
DQ7V
A8A11
DQ13
PP
RP A18
A21
DQ11
DQ12
DQ4
WP A19
A20
DQ2
DD
A7V
A5A17WA10
DQ0DQ9DQ3DQ6
DQ1DQ10V
V
A4
A2
A1A3A6A9A12A15
A0EDQ8DQ5DQ14A16
SSQ
G
AI04380b
7/55
M28W640FCT, M28W640FCB
Figure 5. Block Addresses
M28W640FCT
Top Boot Block Addresses
3FFFFF
3FF000
3F8FFF
3F8000
3F7FFF
3F0000
00FFFF
008000
007FFF
000000
Note: Also see APPENDIX A., Tables 24 and 25 for a full listing of the Block Addresses.
4 KWords
Total of 8
4 KWord Blocks
4 KWords
32 KWords
Total of 127
32 KWord Blocks
32 KWords
32 KWords
Bottom Boot Block Addresses
3FFFFF
3F8000
3F7FFF
3F0000
00FFFF
008000
007FFF
007000
000FFF
000000
M28W640FCB
32 KWords
32 KWords
Total of 127
32 KWord Blocks
32 KWords
4 KWords
Total of 8
4 KWord Blocks
4 KWords
AI09905
Figure 6. Protection Register Memory Map
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
81h
80h
Unique device number
Protection Register Lock 1 0
AI05520b
8/55
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device. Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be progra mmed d uring a Write Bus operation.
Chip Enable (E
vates the memory control lo gic, input buffers, de coders and sense amplifiers. When Chip Enable is
at V
and Reset is at VIH the device is in active
IL
mode. When Chip Enable i s at V
deselected, the outputs a re high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G
data outputs during the Bus Read operation of the
memory.
Write Enable (W
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip En abl e, E
able, W
, whichever occurs first.
Write Protect (WP
that gives an additional hardware protection for
each block. When Write Protect is at V
Down is enabled and the protection status of the
block cannot be changed. When Write Protect is at
V
, the Lock-Down is disa bled an d the bl ock c an
IH
be locked or unlocked. (refer to Table 7., Read
Protection Register and Lock Register).
Reset (RP
ware reset of the memory. When Re set is at V
the memory is in reset mode: the outputs are high
impedance and the curre nt consumption is minimized. After Reset all blocks are in the Locked
). The Chip Enable input acti-
the memory is
IH
). The Output Enable controls
). The Write Enabl e contro ls the
, or Write En-
). Write Protect is an input
, the Lock-
IL
). The Reset input provides a hard-
IL
M28W640FCT, M28W640FCB
state. When Reset is a t V
operation. Exiting reset mode the device enters
read array mode, but a negative transi tion of Chip
Enable or a change of th e address is require d to
ensure valid data outputs.
V
Supply Voltage. VDD provides the power
DD
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
Supply Voltage. V
DDQ
supply to the I/O pins and enable s all Outputs to
be powered independently from V
tied to V
Program Supply Voltage. VPP is both a
V
PP
or can use a separate supply.
DD
control input and a power supply pin. The two
functions are selected by the voltage range applied to the pin . The Supply Voltage V
Program Supply Voltage V
any order.
If V
is kept in a low voltage range (0V to 3.6V)
PP
V
is seen as a co ntrol inpu t. In th is ca se a v olt-
PP
age lower than V
PPLK
against program or erase, whi le V
ables these function s (see T able 15., DC Charac-
teristics, for the relevant values). V
sampled at the beginning of a program or erase; a
change in its valu e afte r the o per ati on has st ar ted
does not have any effect on Program or Erase,
however for Double or Quadr uple Word Program
the results are uncertain.
If V
is in the range 1 1.4V to 12.6V it acts as a
PP
power supply pin. In this condition V
stable until the Pr ogram/Erase algorithm is com pleted (see Table 17. and Table 18.).
V
Ground. VSS is the reference for al l voltage
SS
measurements.
Note: Each device in a system should have
V
,
DD, VDDQ
pacitor close to the pin. See Figure 8., AC Mea-
and VPP decoupled with a 0.1µF ca-
surement Load Circuit. The PCB track widths
should be sufficient to carry the required V
program and erase currents.
, the device is in normal
IH
provides the power
DDQ
. V
DD
can be applied in
PP
gives an absolute protection
PP
DDQ
and the
DD
> V
is only
PP
must be
PP
can be
en-
PP1
PP
9/55
M28W640FCT, M28W640FCB
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Writ e, Output Disable, Standby, Automatic Standby and Reset. See Table 2., Bus Op erations, for a summary.
Typically glitches of les s th an 5ns on C hip Enab le
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operation s are used to output the contents of the Mem ory Array, the Electr onic Signature, the Status Regi ster and the Common Flash Interface. Both Chip Enable and Output Enable must be at V eration. The Chip E nable inp ut should be used to enable the devi ce. Ou tput E nab le should be us ed to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See
Figure 9., Read AC Waveforms, and Table
16., Read AC Characteristics, for details of wh en
the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up. Write. Bus Write oper ations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at V
V
. Commands, Input Data and Addresses are
IH
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
See Figure 10. and Figure 11., Write AC Wave-
forms, and Table 17. and Table 18., Write AC
in order to perform a read op-
IL
with Output Enable at
IL
Characteristics, for details of the timing requirements.
Output Disable. The data outputs are high impedance when the Output Enable is at V
IH
.
Standby. Standby disables most o f the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at V
and the device is in
IH
read mode. The power consumption is reduced to
the stand-by level and the ou tputs are set to high
impedance, independently from the Output Enable
or Write Enable inpu ts. If Chi p E nab le swi tc hes to
V
during a program or eras e operation, the de-
IH
vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V
current is reduced to I
. The data Inputs/Out-
DD1
, and the supply
IL
puts will st ill ou tp ut dat a if a bus Read ope rati on is
in progress.
Reset. During Reset mode w hen Output E nable is Low, V
, the memory is deselected and the out-
IL
puts are high impedance. The memory is in Reset
mode when Reset is at V
. The power consump-
IL
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enabl e or Write En able inputs. If Reset is pulled to V
during a Pro-
SS
gram or Erase, this operation is aborted and the
memory content is no longer valid.
Table 2. Bus Operations
Operation E G W RP WP
Bus Read
Bus Write
Output Disable
Standby
Reset X X X
Note: X = VIL or VIH, V
10/55
V
V
V
V
= 12V ± 5%.
PPH
IL
IL
IL
IH
V
IL
V
IH
V
IH
XX
V
IH
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
PP
X Don't Care Data Output
V
X
X Don't Care Hi-Z
X Don't Care Hi-Z
X Don't Care Hi-Z
DD
or V
PPH
DQ0-DQ15
Data Input
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program /Erase Control ler handles all timings and veri fies the correct executi on
of the Program and Eras e commands. The Program/Erase Controlle r provides a Status Registe r
whose output may be read at any time dur ing, to
monitor the progress of the operation, or the Pro gram/Erase states. See Table 3., Command
Codes, for a summary of the c ommands and s ee
APPENDIX D., Table 32., Write State Machine
Current/Next, sheet 1 of 2., for a summary of the
Command Interface.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Reset or whenever V
mand sequences must be followed exactly. Any
invalid combination of commands will reset the device to Read mode. Refer to Table 4., Commands,
in conjunction with the text descriptions below.
Read Memory Array Command
The Read command returns the memory to its
Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return
the memory to Read mode. Subseque nt read operations will read t he address ed lo catio n a nd out put the data. When a device Reset occurs, the
memory defaults to Read mode.
Read Status Register Command
The Status Register indicates w hen a prog ram or
erase operation is complete and the success or
failure of the operation itself. Is sue a Read Status
Register command to read the S tatus Register’s
contents. Subseque nt Bus Read operations re ad
the Status Register at a ny address, until anothe r
command is issued . S ee Tabl e 1 1., Status Regi s-
ter Bits, for details on the definitions of the bits.
The Read Status Regist er command may be issued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will auto matically o utput the content of the Status Register.
Read Electronic Signature Command
The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read wil l output
the Manufacturer Code, the Device Code, the
Block Lock and L ock-Dow n Stat us, or the Pro tection and Lock Regi ster. Se e Tab les 5, 6 and 7 for
the valid address.
is lower than V
DD
LKO
. Com-
M28W640FCT, M28W640FCB
Table 3. Command Codes
Hex Code Command
01h
10h Program
20h Erase
2Fh
30h Double Word Program
40h Program
50h Clear Status Register
56h Quadruple Word Program
60h
70h Read Status Register
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend
C0h Protection Registe r Prog ram
D0h
FFh Read Memory Array
Read CFI Query Command
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or applications to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com mand. Once the comm and is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See APPENDIX
B., COMMON FLASH INTERFACE (CFI), Tables
26, 27, 28, 29, 30 and 31 for details on the infor-
mation contained in the Com mon Flash Interface
memory area.
Block Erase Command
The Block Erase command can be used to eras e
a block. It sets all the bits within the selected block
to ’1’. All previous data in the bloc k is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.
Two Bus Write cycles are required to issue the
command.
■ The first bus cycle sets up the Erase
command.
Block Lock confirm
Block Lock-Down confirm
Block Lock, Block Unlock, Block LockDown
Program/Erase Resume, Block Unlock
confirm
11/55
M28W640FCT, M28W640FCB
■ The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Regist er bits b4 and b5 are s et and
the command aborts.
Erase aborts if Reset turns to V
. As data integrity
IL
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memo ry will accept
the Read Status Regis ter command a nd the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are
given in Table 8., Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See APPENDIX C., Figure 21., Erase Flowchart
and Pseudo Code, for a suggested flowc hart for
using the Erase command.
Program Command
The memory array can be programmed word-byword. Two bus write cycles ar e required to issue
the Program Command.
■ The first bus cycle sets up the Program
command.
■ The second latches the Address and the Data
to be written and starts the Program/Erase
Controller.
During Program operations the memory will accept the Read Statu s Register comm and and the
Program/Erase Sus pend command. Typical Program times are given in Tabl e 8., Program , Erase
Times and Program/Erase Endurance Cycles.
Programming aborts if Rese t goes to V
. As data
IL
integrity cannot be gu aranteed wh en the p rogram
operation is aborted, the block containing the
memory location must be erased and reprogrammed.
See APPENDIX C., Figure 17., Program Flow-
chart and Pseudo Code, for the flowchart for using
the Program command.
Double Word Program Command
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two wor ds must differ only for the
address A0. Programm ing shoul d not be attempt ed when V
is not at V
PP
PPH
.
Three bus write cy cles ar e ne ce ss ar y to i ss ue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has s tarted. Program ming aborts if Reset goes to V
. As data integrit y
IL
cannot be guaranteed when the program operation is aborted, the blo ck containing the memory
location must be erased and reprogrammed.
See APPENDIX C., Figure 18., Double Word Pro-
gram Flowchart and Pseudo Code for the flow-
chart for using the Double Word Program
command.
Quadruple Word Program Command
This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The fou r words must differ on ly for the
addresses A0 and A1. Programming should not be
attempted when V
is not at V
PP
PPH
.
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
■ The first bus cycle sets up the Quadruple
Word Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and
the Data of the second word to be written.
■ The fourth bus cycle latches the Address and
the Data of the third word to be written.
■ The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has s tarted. Program ming aborts if Reset goes to V
. As data integrit y
IL
cannot be guaranteed when the program operation is aborted, the blo ck containing the memory
location must be erased and reprogrammed.
See APPENDIX C., Figure 19., Quadruple Word
Program Flowchart and Pseudo Code, for the
flowchart for using the Q uadruple Word Program
command.
Clear Status Register Command
The Clear Status Regist er co mm and ca n be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pause the Program/Erase controller.
12/55
M28W640FCT, M28W640FCB
During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lock, Block Lock-Down or
Protection Program commands will also be accepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/
Erase Resume command is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Enable to V
Reset turns to V
. Program/Erase is aborted if
IH
.
IL
See APPENDIX C., Figure 20., Program Suspend
& Resume Flowchart and Pseudo Cod e, and Figure 22., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/E rase Controller after
a Program/Erase Sus pend operation has paused
it. One Bus Write cycle is required to issue the
command. Once the command is issu ed subsequent Bus Read opera tions read th e Status Register.
See APPENDIX C., Figure 20., Program Suspend
& Resume Flowchart and Pseudo Cod e, and Figure 22., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Resume command.
Protection Register Program Command
The Protection Register Program command is
used to Program the 128 bit u ser One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are re quire d to is su e th e Pr o tec tion Register Program command.
■ The first bus cycle sets up the Protection
Register Program command.
■ The second latches the Address and the Data
to be written to the Protection Register and
starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register (see Figure
6., Protection Register Memory Map). Attem pting
to program a previously protected Protection Reg-
ister will result in a Status Register error. The protection of the Protection Register is not reversible.
The Protection Register Progra m cannot be suspended.
Block Lock Command
The Block Lock comma nd is used to loc k a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bu s Writ e cycl e latc hes t he b lock
address.
The lock status can be mo nitored for each block
using the Read Electronic Signature command.
Table 10. shows the protection status after issuing
a Block Lock command.
The Block Lock bits are vol atile, onc e set th ey re-
main set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.
Block Unlock Command
The Block Unlock c ommand is used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Wr ite cycles are required to issue the Block Unlock command.
■ The first bus cycle sets up the Block Unlock
command.
■ The second Bu s Writ e cycl e latc hes t he b lock
address.
The lock status can be mo nitored for each block
using the Read Electronic Signature command.
Table 10. shows the protection status after issuing
a Block Unlock command. Refer to the section,
Block Locking, for a detailed explanation.
Block Lock-Down Command
A locked block cannot be Programmed or Erased,
or have its protection s tatu s cha nge d whe n W P
low, V
. When WP is high, V
IL
the Lock-Down
IH,
is
function is disabl ed and the locked blocks c an be
individually unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bu s Writ e cycl e latc hes t he b lock
address.
The lock status can be mo nitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
13/55
M28W640FCT, M28W640FCB
locked-down) state when the device is reset on
power-down. Table 10. shows the protection sta-
Refer to the section, Block Loc king, for a deta iled
explanation.
tus after issuing a Block Lock-Down command.
Table 4. Commands
Bus Write Operations
Commands
Read Memory
Array
Read Status
Register
Read Electronic
Signature
Read CFI Query 1+ Wri t e X 98h Read QA QD
Erase 2WriteX 20hWriteBA D0h
Program 2 Write X
Double Word
Program
Quadruple Word
Program
Clear Status
Register
Program/Erase
Suspend
Program/Erase
Resume
Block Lock 2 Write X 60h Write
Block Unlock 2 W ri te X 60h Write
Block Lock-Down 2 Wri te X 60h Write
Protection
Register Program
Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),
(3)
(4)
QA=Query Address, QD=Q uery Data, BA =Block Addr ess, PA=Progr am Addres s, PD=Progra m Data, PRA= Protection Re gister Address, PRD =P r otection Regi ster Data.
2. The signature addresses are listed in Tables 5, 6 and 7.
3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
1+ Write X FFh
1+ Write X 70h Read X SRD
1+ Write X 90h Read
1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle
Cycles
Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data
RA RD
Read
(2)
IDh
SA
40h or
Write PA PD
10h
3 Write X 30h Write PA1 PD1 Write PA2 PD2
5 W rite X 56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4
1Write X 50h
1Write X B0h
1Write X D0h
01h
BA
BA D0h
2Fh
BA
2Write X C0hWrite
PRA
PRD
Table 5. Read Electronic Signature
Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-DQ15
Manufacture
Code
M28W640FCT
Device Code
M28W640FCB
Note: RP = VIH.
14/55
V
V
IL
ILVIHVIL
V
V
IL
ILVIHVIHVIL
V
V
IL
ILVIHVIHVIL
V
IL
0 Don't Care 20h 00h
0 Don't Care 48h 88h
0 Don't Care 49h 88h
M28W640FCT, M28W640FCB
Table 6. Read Block Lock Signature
Block Status E G W A0 A1 A2-A7 A8-A11 A12-A21 DQ0 DQ1 DQ2-DQ15
Locked Block
Unlocked Block
Locked-Down
Block
Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Blo ck Locking section .
Table 7. Read Protection Register and Lock Register
Word E
Lock
Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
OTP 1
OTP 2
OTP 3
OTP 4
OTP 5
OTP 6
OTP 7
V
ILVILVIHVILVIH
V
ILVILVIHVILVIH
V
ILVILVIHVILVIH
0 Don't Care Block Address 1 0 00h
0 Don't Care Block Address 0 0 00h
0 Don't Care Block Address
X
(1)
1 00h
G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15
V
ILVILVIH
V
ILVILVIH
VILVILV
VILVILV
V
ILVILVIH
VILVILV
VILVILV
V
ILVILVIH
VILVILV
VILVILV
VILVILV
V
ILVILVIH
VILVILV
80h Don't Care 0
81h Don't Care ID data ID data ID data ID data ID data
82h Don't Care ID data ID data ID data ID data ID data
IH
83h Don't Care ID data ID data ID data ID data ID data
IH
84h Don't Care ID data ID data ID data ID data ID data
85h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta
IH
86h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta
IH
87h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta
88h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta
IH
89h D on't C are OTP data OTP da ta OTP data OT P data OTP da ta
IH
8Ah Don' t C are OT P data OTP data OTP d ata OTP data OTP d a ta
IH
8Bh Don' t C are OT P data OTP data OTP d ata OTP data OTP d a ta
8Ch D on't C are OTP data O TP data OTP data OT P data OTP da ta
IH
OTP Prot.
data
000h00h
15/55
M28W640FCT, M28W640FCB
Table 8. Program, Erase Times and Program/Erase Endurance Cycles
Parameter Test Conditions
V
Word Pr ogram
Double Word Program
Quadruple Word Program
Main Block Program
Parameter Block Program
Main Block Erase
PP
V
= 12V ±5%
PP
= 12V ±5%
V
PP
= 12V ±5%
V
PP
V
PP
= 12V ±5%
V
PP
V
PP
V
= 12V ±5%
PP
V
PP
= V
= V
= V
= V
DD
DD
DD
DD
VPP = 12V ±5%
Parameter Block Erase
= V
V
PP
DD
Program/Erase Cycles (per Block) 100,000 cycles
Note: 1. Typical time to program a Main or Parameter Block us ing the Doubl e Word Pro gram and t he Q uadruple Word Prog ram comman ds
respectively.
M28W640FCT, M 2 8W 64 0F CB
Min Typ Max
10 200 µ s
10 200 µ s
10 200 µ s
0.16/0.08
(1)
5s
0.32 5 s
0.02/0.01
(1)
4s
0.04 4 s
110s
110s
0.4 10 s
0.4 10 s
Unit
16/55
BLOCK LOCKING
The M28W640FCT and M28W640FCB feature an
instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of
protection.
■ Lock/Unlock - this first level allows software-
only control of block locking.
■ Lock-Down - this second level requires
hardware interaction before locking can be
changed.
■ V
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 10., defines all of the possible protection states (WP
DQ1, DQ0) , and APPENDIX C., Figure 23., shows
a flowchart for the locking operations.
Reading a Block’s Lock Status
The lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6.,
will output the protec tion sta tus of tha t block. T he
lock status is represen ted b y D Q0 and DQ 1. DQ0
indicates the Block Lock/Unlock sta tus and is set
by the Lock command and cleared by the Unl ock
command. It is als o au tom ati ca ll y s et when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked State
The default status of all blo cks on po wer -up o r af ter a hardware reset is Locked (states (0,0,1) o r
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase operations attempted on a locke d block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
Unlocked State
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
PP
≤ V
- the third level offers a complete
PPLK
hardware protection against program and
erase on all blocks.
M28W640FCT, M28W640FCB
software commands. A locked block can be unlocked by issuing the Unlock command.
Lock-Dow n St a t e
Blocks that are Locked-Down (state (0,1,x))are
protected from program an d erase operati ons (as
for Locked blocks) but the ir prote ction stat us can not be changed using so ftware comman ds alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. LockedDown blocks revert to the Lock ed state whe n the
device is reset or powered-down.
The Lock-Down function is depend ent on the W P
input pin. When WP=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When
WP
,
=1 (VIH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be i ndividually unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These bl ocks can th en be reloc ked
(1,1,1) and unlock ed (1,1,0) as desired whi le WP
remains high. When WP is low , blocks that were
previously Locked-Down re turn to the Lock-Down
state (0,1,x) regardless of any changes made
while WP
was high. Device reset or power-down
resets all blocks , including those in Lock-Down, to
the Locked state.
Locking Operations During Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a bl oc k. T his is u se fu l in t h e c a se whe n
another block needs to be updated while an erase
operation is in progress.
To change block loc king during an erase operation, first write the Erase Suspend command, then
check the status register unti l it indicates that the
erase operation h as been suspended. Next write
the desired Lock command s equence to a block
and the lock status will be changed. After completing any desired lock, read, or program operations,
resume the erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immedi ately, but when the er ase
is resumed, the erase operation will complete.
Locking operations cann ot be perfor med during a
program suspend. Re fer to APPENDIX D., Command Interface and Program/Erase Controller
State, for detailed information on which commands are valid during erase suspend.
17/55
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