M27C800
8 Mbit (1Mb x8 or 512Kb x16) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 50ns
■ BYTE-WIDE or WORD-WIDE
CONFIGURABLE
■ 8 Mbit MASK ROM REPLACEMENT
■ LOW POWER CONSUMPTION
– Active Current 70mA at 8MHz
– Stand-by Current 50µA
■ PROGRAMMING VOLTAGE: 12.5V ± 0.25V
■ PROGRAMMING TIME: 50µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: B2h
42
1
FDIP42W (F) PDIP42 (B)
42
1
44
1
SO44 (M)PLCC44 (K)
DESCRIPTION
The M27C800 is an 8 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for microprocessor systems requiringlargedataorprogram
storage. It is organised as either 1 Mwords of 8 bit
or 512 Kwords of 16 bit. The pin-out is compatible
with the most common 8 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chip to ultraviolet lightto erase the bit pattern.
A new patterncanthenbewrittenrapidlytothedevice by following the programming procedure.
For applications where the contentis programmed
only one time and erasure is not required, the
M27C800 is offered in PDIP42, PLCC44 and
SO44 packages.
Figure 1. Logic Diagram
V
CC
19
A0-A18
BYTEV
E
G
PP
M27C800
V
SS
Q15A–1
15
Q0-Q14
AI01593
1/17January 2000
M27C800
Figure 2A. DIP Connections
1
A18 NC
2
3
A7
A6
4
A5
5
6
A4
7
A3
8
A2
9
A1
10
A0
V
SS
Q0
Q8
Q1
Q9
Q10
Q3
Q11
M27C800
11
E
12
13
G
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
AI01594
A8A17
A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V
SS
Q15A–1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V
CC
PP
Figure 2B. LCC Connections
SS
A18
A5
A6
A4
A3
A2
A1 A15
A0
E
12
V
SS
Q0
Q8
Q1
Q9
Q2
Q10
V
1
M27C800
23
Q3
NC
Q11
44
V
CC
A17A8NC
A7
Q4
A9
Q12
A10
Q5
A11
34
Q13
A12
A13
A14
A16
BYTEV
V
SS
Q15A–1G
Q7
Q14
Q6
AI02042
PP
Figure 2C. SO Connections
1
NC NC
2
A17 A8
V
Q10
Q11
A7
A6
A5
A4
A3
A2
A1
A0
SS
Q0
Q8
Q9
Q3
3
4
5
6
7
8
9
10
11
M27C800
12
E
13
14
G
15
16
17Q1
18
19
20
21
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322
AI01595
NCA18
A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V
SS
Q15A–1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V
CC
PP
Table 1. Signal Names
A0-A18 Address Inputs
Q0-Q7 Data Outputs
Q8-Q14 Data Outputs
Q15A–1 Data Output / Address Input
E Chip Enable
G Output Enable
BYTEV
PP
V
CC
V
SS
NC Not Connected Internally
Byte Mode / Program Supply
Supply Voltage
Ground
2/17
M27C800
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or anyother conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extendedperiods may affect device reliability. Referalso to theSTMicroelectronics SURE Program andotherrelevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E G
Read Word-wide
Read Byte-wide Upper V
Read Byte-wide Lower
Output Disable V
Program
V
IL
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
V
IL
IL
Pulse V
V
IH
V
IH
V
IH
V
IL
V
V
V
V
V
V
V
BYTEV
IL
IL
IL
IH
IH
IL
IH
V
IH
V
IL
V
IL
X X Hi-Z Hi-Z Hi-Z
V
PP
V
PP
V
PP
A9 Q15A–1 Q14-Q8 Q7-Q0
PP
X Data Out Data Out Data Out
XVIHHi-Z Data Out
X
V
IL
Hi-Z Data Out
X Data In Data In Data In
X Data Out Data Out Data Out
X Hi-Z Hi-Z Hi-Z
X X X Hi-Z Hi-Z Hi-Z
IL
V
IH
V
ID
Code Codes Codes
Table 4. Electronic Signature
Identifier A0
Manufacturer’s Code
Device Code
V
IL
V
IH
Q15
and
Q7
Q14
and
Q6
Q13
and
Q5
Q12
and
Q4
Q11
and
Q3
Q10
and
Q2
Q9
and
Q1
Q8
andQ0Hex Data
00100000 20h
10110010 B2h
3/17
M27C800
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and FallTimes ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
2.0V
0.8V
AI01822
DEVICE OPERATION
The operatingmodes of the M27C800 are listed in
the OperatingModes Table.A singlepowersupply
is required in the read mode. All inputs are TTL
compatible except for VPPand 12V on A9 for the
Electronic Signature.
Read Mode
The M27C800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEVPPpin. When BYTEV
PP
is at VIHthe Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When theBYTEVPPpin is at VILthe Byte-wide organisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at VILthe
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL= 30pFfor High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
C
L
OUT
AI01823B
lower 8 bits of the 16 bit data are selected andwith
A–1 at VIHthe upper 8 bits of the 16 bit data are
selected.
The M27C800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is thepowercontrolandshouldbe
used for device selection. Output Enable (G)is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the address access time (t
from E to output (t
ELQV
output after a delay of t
) is equal to the delay
AVQV
). Data is available at the
from the falling edge
GLQV
of G, assuming that E has been low and the addresses have been stable forat least t
AVQV-tGLQV
.
4/17
M27C800
Table 6. Capacitance
(1)
(TA=25°C, f = 1 MHz)
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only,not 100% tested.
Input Capacitance (BYTEV
Output Capacitance
)V
PP
Table 7. Read Mode DC Characteristics
Input Capacitance (except BYTEVPP)V
(1)
=0V
IN
= 0V 120 pF
IN
V
=0V
OUT
10 pF
12 pF
(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
LO
0V ≤ V
0V ≤ V
E=V
I
Supply Current
OUT
E=V
I
OUT
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
Output High Voltage TTL
OH
2. Maximum DC voltage on Output is V
CC
+ 0.5V.
E>V
I
OH
≤ V
IN
CC
≤ V
OUT
IL
CC
,G=VIL,
= 0mA, f = 8MHz
,G=VIL,
IL
= 0mA, f = 5MHz
E=V
IH
– 0.2V
CC
V
PP=VCC
I
= 2.1mA
OL
= –400µA
2.4 V
±1 µA
±10 µA
70 mA
50 mA
1mA
50 µA
10 µA
V
+1
CC
0.4 V
V
Standby Mode
The M27C800 has astandbymode which reduces
the supply current from 50mA to 100µA. The
M27C800 is placedin the standby mode by applying aCMOS high signal to the Einput. When in the
standby mode, the outputs are in a high impedance state, independent of the G input.
5/17
M27C800
Table 8A. Read Mode AC Characteristics
(1)
(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)
M27C800
Symbol Alt Parameter TestCondition
t
AVQV
t
BHQV
t
ELQV
t
GLQV
(2)
t
BLQZ
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
t
BLQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after V
2. Sampled only,not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Address Validto Output
t
ACC
Valid
BYTE High to Output
t
ST
Valid
Chip Enable Low to
t
CE
Output Valid
Output Enable Low to
t
OE
Output Valid
t
BYTE Low to Output Hi-Z
STD
Chip Enable High to
t
DF
Output Hi-Z
Output Enable High to
t
DF
Output Hi-Z
Address Transition to
t
OH
Output Transition
BYTE Low to Output
t
OH
Transition
E=V
E=V
E=V
E=V
E=V
,G=V
IL
,G=V
IL
G=V
E=V
,G=V
IL
G=V
E=V
,G=V
IL
,G=V
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
(3)
-50
Min Max Min Max Min Max
50 70 90 ns
50 70 90 ns
50 70 90 ns
30 35 45 ns
30 30 30 ns
030030030ns
030030030ns
555ns
555ns
-70 -90
PP.
Unit
Table 8B. Read Mode AC Characteristics
(1)
(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)
Symbol Alt Parameter Test Condition
t
t
AVQV
t
BHQV
t
ELQV
t
GLQV
(2)
t
BLQZ
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
t
BLQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after V
2. Sampled only,not 100% tested.
Address Valid to Output Valid E= VIL,G=V
ACC
t
BYTE High to Output Valid
ST
t
Chip Enable Low to Output Valid
CE
t
Output Enable Low to Output Valid
OE
t
BYTE Low to Output Hi-Z
STD
t
Chip Enable High to Output Hi-Z
DF
t
Output Enable High to Output Hi-Z
DF
t
Address Transitionto Output Transition E = VIL,G=V
OH
t
BYTE Low to Output Transition
OH
E=V
E=V
E=V
,G=V
IL
G=V
E=V
,G=V
IL
G=V
E=V
,G=V
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
M27C800
Unit-100 -120/150
Min Max Min Max
100 120 ns
100 120 ns
100 120 ns
50 60 ns
40 50 ns
0 40 0 50 ns
0 40 0 50 ns
55ns
55ns
PP.
6/17
Figure 5. Word-Wide Read Mode AC Waveforms
M27C800
A0-A18
E
G
Q0-Q15
Note: BYTEVPP=VIH.
VALID
tAVQV
tGLQV
tELQV
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2-line control function which accommodates the use of multiple memory connection. The two-line control
function allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselected memorydevices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI01596B
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I
CC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E.
The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading
of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control andby properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor is used on every
device between VCCand VSS.
This should be a high frequency type of low inherent inductance and should be placed as close as
possible to the device. In addition, a4.7µF electrolytic capacitor should be used between VCCand
VSSfor every eight devices. This capacitor should
be mounted near the power supply connection
point. The purpose of this capacitor is to overcome
the voltage drop causedby the inductive effects of
PCB traces.
7/17
M27C800
Figure 6. Byte-Wide Read Mode AC Waveforms
A–1,A0-A18
E
G
Q0-Q7
Note: BYTEVPP=V
IL.
VALID
tAVQV
tGLQV
tELQV
Figure 7. BYTE Transition ACWaveforms
A0-A18
A–1
VALID
VALID
tAXQX
VALID
tEHQZ
tGHQZ
Hi-Z
AI01597B
tAVQV
BYTEV
PP
Q0-Q7
tBLQX
Q8-Q15
tBLQZ
Note: Chip Enable (E) and Output Enable (G) = VIL.
Hi-Z
tAXQX
tBHQV
DATA OUT
DATA OUT
AI01598C
8/17
M27C800
Table 9. Programming Mode DC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.5V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
V
V
OL
V
OH
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V
IL
Input High Voltage 2.4 VCC+ 0.5 V
IH
Output Low Voltage
Output High Voltage TTL IOH= –2.5mA 3.5 V
A9 Voltage 11.5 12.5 V
ID
Table 10. Programming Mode AC Characteristics
0 ≤ V
I
OL
(1)
≤ V
IN
E=V
= 2.1mA
CC
IL
±1 µA
50 mA
0.4 V
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.5V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
AVEL
t
QVEL
t
VPHAV
t
VCHAV
t
ELEH
t
EHQX
t
QXGL
t
GLQV
(2)
t
GHQZ
t
GHAX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only,not 100% tested.
t
t
t
VPS
t
VCS
t
PW
t
t
OES
t
t
DFP
t
Address Validto Chip Enable Low 2 µs
AS
Input Valid to Chip Enable Low 2 µs
DS
VPPHigh to Address Valid
VCCHigh to Address Valid
2 µs
2 µs
Chip Enable Program Pulse Width 45 55 µs
Chip Enable High to Input Transition 2 µs
DH
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 120 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address
AH
Transition
0ns
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27C800 are in the ’1’
state. Data is introduced by selectively programming ’0’s into the desired bit locations. Although
only ’0’swill be programmed, both ’1’s and ’0’scan
be present in the data word. The only way to
change a ’0’ to a ’1’is by dieexposition to ultraviolet light (UVEPROM). The M27C800 is in the programming mode when VPPinput is at 12.5V, G is
at VIHand E is pulsed to VIL. The data to be programmedis applied to 16 bits in parallelto the data
output pins. The levels required for the address
and data inputs are TTL. VCCis specified to be
6.25V ± 0.25V.
9/17
M27C800
Figure 8. Programming and Verify Modes AC Waveforms
A0-A18
Q0-Q15
BYTEV
PP
tVPHAV
V
CC
tVCHAV
E
G
Figure 9. Programming Flowchart
VCC= 6.25V, VPP= 12.5V
n=0
E=50µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL WORDS
BYTEVPP=V
1st: VCC=6V
2nd: VCC= 4.2V
IH
++ Addr
YES
++n
=25
FAIL
VALID
tAVEL
DATA IN DATA OUT
tQVEL
tELEH
PROGRAM VERIFY
tEHQX
tQXGL
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaranteed margin in a typical time of 26 seconds. Programming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 9). During
programing and verify operation a MARGIN
MODE circuit is automatically activated to guarantee that each cell is programed with enough margin. No overprogram pulse is applied since the
verify in MARGIN MODE provides the necessary
margin to each programmed cell.
Program Inhibit
Programming of multiple M27C800s in parallel
with different data is also easily accomplished. Except for E,all like inputs including G of theparallel
M27C800 may be common. A TTL low level pulse
applied to a M27C800’s E input and VPPat 12.5V,
will program that M27C800.A high level Einput inhibits the other M27C800s from being programmed.
Program Verify
A verify (read) should be performed on the pro-
AI01044B
grammed bits to determine that theywere correctly programmed. The verify is accomplished with E
at VIHand G at VIL,VPPat 12.5V and VCCat
6.25V.
tGLQV
tGHQZ
tGHAX
AI01599
10/17
M27C800
On-Board Programming
The M27C800 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code froman EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperaturerange that is required when programming the M27C800. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C800, with VPP=VCC= 5V. Two identifier
bytes may then besequenced from the device outputs by toggling address lineA0 from VILtoVIH. All
other address lines must be held at VILduring
Electronic Signature mode.
Byte 0 (A0 = VIL) represents the manufacturer
code and byte 1 (A0 = VIH) the device identifier
code. Forthe STMicroelectronics M27C800, these
two identifier bytes aregiven inTable 4 andcan be
read-out on outputs Q7 to Q0.
ERASURE OPERATION(applies to UV EPROM)
The erasure characteristics of the M27C800 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27C800 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C800 is to be exposed to these
types oflighting conditions forextended periods of
time, itis suggestedthat opaque labels beput over
the M27C800 window to prevent unintentional erasure. The recommended erasure procedure for
M27C800 is exposure to short wave ultraviolet
light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 30 W-sec/cm2.
The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with
12000 µW/cm2power rating. The M27C800
should be placed within 2.5cm(1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.
11/17
M27C800
Table 11. Ordering Information Scheme
Example: M27C800 -50 X M 1 TR
Device Type
M27
Supply Voltage
C=5V
Device Function
800 = 8 Mbit (1Mb x8 or 512Kb x16)
Speed
(1)
=50ns
-50
-70 = 70 ns
-90 = 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
Tolerance
V
CC
blank = ± 10%
X=±5%
Package
F = FDIP40W
B = PDIP40
K = PLCC44
M = SO44
Temperature Range
1=0to70°C
6=–40to85°C
Options
TR = Tape& Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest toyou.
Table 1. Revision History
Date Revision Details
March 1999 First Issue
01/25/00
12/17
50ns speed class addes (Tables8A and 11)
Electronic Signature change (Table4)
FDIP42W Package Dimension, L Max added (Table 12)
M27C800
Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 54.41 54.86 2.142 2.160
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 14.50 14.90 0.571 0.587
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
K 9.40 – – 0.370 – –
K1 11.43 – – 0.450 – –
α 4° 11° 4° 11°
N42 42
Typ Min Max Typ Min Max
mm inches
Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
B1 B e1
A3A1A
L
α
C
eA
D2
eB
D
S
N
E1 E
K
1
Drawing is not to scale.
K1
FDIPW-b
13/17
M27C800
Table 13. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.25 – 0.010 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.53 0.015 0.021
B1 1.27 1.65 0.050 0.065
C 0.20 0.36 0.008 0.014
D 52.20 52.71 2.055 2.075
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 0.86 1.37 0.034 0.054
α 0° 10° 0° 10°
N42 42
mm inches
Figure 11. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline
A2A1A
L
B1 B e1
D2
α
eA
eB
D
S
N
E1 E
1
Drawing is not to scale.
C
PDIP
14/17
Table 14. PLCC44 - 44lead Plastic Leaded Chip Carrier, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 4.20 4.70 0.165 0.185
A1 2.29 3.04 0.090 0.120
A2 – 0.51 – 0.020
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 17.40 17.65 0.685 0.695
D1 16.51 16.66 0.650 0.656
D2 14.99 16.00 0.590 0.630
E 17.40 17.65 0.685 0.695
E1 16.51 16.66 0.650 0.656
E2 14.99 16.00 0.590 0.630
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
M27C800
N44 44
CP 0.10 0.004
Figure 12. PLCC44 - 44 lead Plastic Leaded ChipCarrier, Package Outline
D
D1
1N
Ne E1 E
A2
F
D2/E2
A1
B
0.51 (.020)
1.14 (.045)
PLCC
Nd
R
CP
A
B1
e
Drawing is not to scale.
15/17
M27C800
Table 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 2.42 2.62 0.095 0.103
A1 0.22 0.23 0.009 0.010
A2 2.25 2.35 0.089 0.093
B 0.50 0.020
C 0.10 0.25 0.004 0.010
D 28.10 28.30 1.106 1.114
E 13.20 13.40 0.520 0.528
e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634
L 0.80 – – 0.031 – –
α 3° ––3°––
N44 44
CP 0.10 0.004
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
B
e
CP
D
N
E
H
1
LA1 α
SO-b
Drawing is not to scale.
16/17
M27C800
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of use ofsuch information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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