ST M27C800 User Manual

M27C800-100B1TR

M27C800

8 Mbit (1Mb x8 or 512Kb x16) UV EPROM and OTP EPROM

■5V ± 10% SUPPLY VOLTAGE in READ OPERATION

■ACCESS TIME: 50ns

■BYTE-WIDE or WORD-WIDE CONFIGURABLE

■8 Mbit MASK ROM REPLACEMENT

■LOW POWER CONSUMPTION

–Active Current 70mA at 8MHz

–Stand-by Current 50µA

■PROGRAMMING VOLTAGE: 12.5V ± 0.25V

■PROGRAMMING TIME: 50µs/word

■ELECTRONIC SIGNATURE

–Manufacturer Code: 20h

–Device Code: B2h

DESCRIPTION

The M27C800 is an 8 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage. It is organised as either 1 Mwords of 8 bit or 512 Kwords of 16 bit. The pin-out is compatible with the most common 8 Mbit Mask ROM.

The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern.

A new pattern can then be written rapidly to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27C800 is offered in PDIP42, PLCC44 and SO44 packages.

42	42
1	1
FDIP42W (F)	PDIP42 (B)
	44
	1
PLCC44 (K)	SO44 (M)

Figure 1. Logic Diagram

		VCC
		19
	A0-A18	Q15A–1
	A0-A18	15
		15
	E	Q0-Q14
	E	M27C800
		M27C800
	G
	BYTEVPP
		VSS
		AI01593

December 2001

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M27C800

Figure 2A. DIP Connections

A18		1				42	NC
A17		2				41	A8
A7		3				40	A9
A6			4			39	A10

A5				5		38	A11

A4		6				37	A12
A3		7				36	A13
A2		8				35	A14
A1		9				34	A15
A0		10			M27C800	33	A16

	E	11				32	BYTEVPP
VSS		12				31	VSS
G		13				30	Q15A–1
Q0		14				29	Q7
Q8		15				28	Q14
Q1		16				27	Q6
Q9		17				26	Q13
Q2		18				25	Q5
Q10				19		24	Q12

Q3		20				23	Q4
Q11		21				22	VCC
					AI01594

Figure 2C. SO Connections


NC		1		44	NC
A18		2		43	NC
A17		3		42	A8
A7		4		41	A9
A6		5		40	A10
A5		6		39	A11
A4		7		38	A12
A3		8		37	A13
A2		9		36	A14
A1		10		35	A15
A0		11	M27C800	34	A16
				33
	E	12			BYTEVPP
VSS		13		32	VSS
G		14		31	Q15A–1
Q0		15		30	Q7
Q8		16		29	Q14
Q1		17		28	Q6
Q9		18		27	Q13
Q2		19		26	Q5
Q10		20		25	Q12
Q3		21		24	Q4
Q11		22		23	VCC
			AI01595

Figure 2B. LCC Connections

A17

A18

A10

A11

A12

A13

A14

A15

A16

M27C800

BYTEVPP

VSS

Q15A–1

Q14

Q10

Q11

Q12

Q13

AI02042

Table 1. Signal Names

A0-A18		Address Inputs

Q0-Q7		Data Outputs

Q8-Q14		Data Outputs

Q15A–1		Data Output / Address Input

		Chip Enable
E		Chip Enable

		Output Enable
G		Output Enable

	PP
BYTEV	PP	Byte Mode / Program Supply

VCC		Supply Voltage
VSS		Ground
NC		Not Connected Internally

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			M27C800
Table 2. Absolute Maximum Ratings (1)
Symbol	Parameter	Value		Unit

TA	Ambient Operating Temperature (3)	–40 to 125		°C
TBIAS	Temperature Under Bias	–50 to 125		°C

TSTG	Storage Temperature	–65 to 150		°C
VIO (2)	Input or Output Voltage (except A9)	–2 to 7		V
VCC	Supply Voltage	–2 to 7		V

VA9 (2)	A9 Voltage	–2 to 13.5		V
VPP	Program Supply Voltage	–2 to 14		V

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3.Depends on range.

Table 3. Operating Modes

Mode

BYTEVPP

Q15A–1

Q14-Q8

Q7-Q0

Read Word-wide

VIL

VIH

Data Out

Read Byte-wide Upper

VIL

VIH

Hi-Z

Data Out

Read Byte-wide Lower

VIL

Hi-Z

Data Out

Output Disable

VIL

VIH

Hi-Z

Program

VIL Pulse

VIH

VPP

Data In

Verify

VIH

VIL

VPP

Data Out

Program Inhibit

VIH

VPP

Hi-Z

Standby

VIH

Hi-Z

Electronic Signature

VIL

VIH

VID

Code

Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

		Q15	Q14	Q13	Q12	Q11	Q10	Q9	Q8
Identifier	A0	and	and	and	and	and	and	and	and	Hex Data
		Q7	Q6	Q5	Q4	Q3	Q2	Q1	Q0

Manufacturer’s Code	VIL	0	0	1	0	0	0	0	0	20h

Device Code	VIH	1	0	1	1	0	0	1	0	B2h

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M27C800

Table 5. AC Measurement Conditions

	High Speed	Standard

Input Rise and Fall Times	≤ 10ns	≤ 20ns

Input Pulse Voltages	0 to 3V	0.4V to 2.4V

Input and Output Timing Ref. Voltages	1.5V	0.8V and 2V

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

1.3V

High Speed

1N914

1.5V

3.3kΩ

DEVICE

Standard

UNDER

OUT

TEST

2.4V

2.0V

0.4V

0.8V

AI01822

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

AI01823B

DEVICE OPERATION

The operating modes of the M27C800 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for VPP and 12V on A9 for the Electronic Signature.

Read Mode

The M27C800 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTEVPP pin. When BYTEVPP is at VIH the Word-wide organisation is selected and the Q15A–1 pin is used for Q15 Data Output. When the BYTEVPP pin is at VIL the Byte-wide organisation is selected and the Q15A–1 pin is used for the Address Input A–1. When the memory is logically regarded as 16 bit wide, but read in the Byte-wide organisation, then with A–1 at VIL the

lower 8 bits of the 16 bit data are selected and with A–1 at VIH the upper 8 bits of the 16 bit data are selected.

The M27C800 has two control functions, both of which must be logically active in order to obtain data at the outputs. In addition the Word-wide or Bytewide organisation must be selected.

Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins independent of device selection. Assuming that the addresses are stable, the ad-

dress access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the ad-

dresses have been stable for at least tAVQV-tGLQV.

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							M27C800
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol	Parameter			Test Condition	Min	Max		Unit

	Input Capacitance (except		PP)	VIN = 0V
CIN	Input Capacitance (except	BYTEV	PP)	VIN = 0V		10		pF


	Input Capacitance (BYTEVPP)			VIN = 0V		120		pF
	Input Capacitance (BYTEVPP)			VIN = 0V		120		pF
COUT	Output Capacitance			VOUT = 0V		12		pF

Note: 1. Sampled only, not 100% tested.

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; V CC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol

Parameter

Test Condition

Min

Max

Unit

ILI

Input Leakage Current

0V ≤ VIN ≤ VCC

±1

µA

ILO

Output Leakage Current

0V ≤ VOUT ≤ VCC

±10

µA

= VIL,

IOUT = 0mA, f = 8MHz

ICC

Supply Current

E = VIL, G = VIL,

IOUT = 0mA, f = 5MHz

ICC1

= VIH

Supply Current (Standby) TTL

ICC2

> VCC – 0.2V

Supply Current (Standby) CMOS

µA

IPP

Program Current

VPP = VCC

µA

VIL

Input Low Voltage

–0.3

0.8

VIH (2)

Input High Voltage

VCC + 1

VOL

Output Low Voltage

IOL = 2.1mA

0.4

VOH

Output High Voltage TTL

IOH = –400µA

2.4

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC + 0.5V.

Standby Mode

The M27C800 has a standby mode which reduces the supply current from 50mA to 100µA. The

M27C800 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

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M27C800

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; V CC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C800

Symbol

Alt

Parameter

Test Condition

-50 (3)

-70

-90

Unit

Min

Max

Min

Max

Min

Max

Address Valid to Output

tAVQV

tACC

E = VIL, G = VIL

Valid

BYTE High to Output

tBHQV

tST

E = VIL, G = VIL

Valid

Chip Enable Low to

tELQV

tCE

G = VIL

Output Valid

Output Enable Low to

tGLQV

tOE

E = VIL

Output Valid

tBLQZ (2)

tSTD

BYTE Low to Output Hi-Z

E = VIL, G = VIL

tEHQZ (2)

Chip Enable High to

tDF

G = VIL

Output Hi-Z

tGHQZ (2)

Output Enable High to

tDF

E = VIL

Output Hi-Z

Address Transition to

tAXQX

tOH

E = VIL, G = VIL

Output Transition

BYTE Low to Output

tBLQX

tOH

E = VIL, G = VIL

Transition

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2.Sampled only, not 100% tested.

3.Speed obtained with High Speed AC measurement conditions.

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; V CC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C800

Symbol

Alt

Parameter

Test Condition

-100

-120/150

Unit

Min

Max

Min

Max

tAVQV

tACC

= VIL,

= VIL

Address Valid to Output Valid

100

120

tBHQV

tST

BYTE High to Output Valid

E = VIL, G = VIL

100

120

tELQV

tCE

= VIL

Chip Enable Low to Output Valid

100

120

tGLQV

tOE

= VIL

Output Enable Low to Output Valid

(2)

tSTD

BYTE Low to Output Hi-Z

E = VIL, G = VIL

tBLQZ

(2)

tDF

Chip Enable High to Output Hi-Z

G = VIL

tEHQZ

(2)

tDF

Output Enable High to Output Hi-Z

E = VIL

tGHQZ

tAXQX

tOH

= VIL,

= VIL

Address Transition to Output Transition

tBLQX

tOH

BYTE Low to Output Transition

E = VIL, G = VIL

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.

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