ST M25P80 User Manual

8 Mbit, Low Voltage, Serial Flash Memory

FEAT URES SUMMARY

■ 8 Mbit of Flash M emor y

■ Page Program (up to 256 Bytes) in 1.4ms

(typical)

■ Sector Erase (512 Kbit) in 1s (typical)

■ Bulk Erase (8 Mbit) in 10s (typical)

■ 2.7 to 3.6V Single Supply Voltage

■ SPI Bus Compatible Serial Interface

■ 40MHz Clock Rate (maximum)

■ Deep Power-down Mode 1µA (typical)

■ Electronic Signature (13h)

M25P80

With 40MHz SPI Bus Interface

Figure 1. Packages

VDFPN8 (MP)

(MLP8)

SO16 (MF)

300 mil width

8

1

SO8 (MW)

200 mil width

1/41August 2004

M25P80

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. VDFPN and SO8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. SO16 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Active Power, Stand-by Power and Deep Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Protected Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/41

M25P80

Figure 9. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 15

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Write Status Register (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. P rote ction Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 18

Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Se­quence 19

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 17.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 18.Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Rele ase fr om Deep Power - down an d R e a d Electronic Signature ( R ES) . . . . . . . . . . . . . . . . . 24

Figure 19.Release from Deep Power-down and Read Electronic Signature (RES) Instruction Se­quence and Data-Out Sequence24

Figure 20.Release from Deep Power-down (RES) Instruction Sequence. . . . . . . . . . . . . . . . . . . . 25

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 21.Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7. Power-Up Timing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 10. Data Retention and Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9

Table 12. DC Characteristics (Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 13. DC Characteristics (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3/41

M25P80

Table 14. Instruction Times (Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. Instruction Times (Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. AC Measurement Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 22.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17. AC Characteristics (25MHz Operation, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . 32

Table 18. AC Characteristics (40MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 23.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 24.Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . 34

Figure 25.Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 26.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 27.VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package Outline. . . . . . 36

Table 19. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package Mechanical Data
36

Figure 28.SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline. . . . 37

Table 20. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data. . . . 37

Figure 29.SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline. . . . . . 38

Table 21. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechan ical Data
38

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 22.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 23. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4/41

SUMMARY DESCRIPT ION

The M25P80 is a 8 Mbit (1M x 8) Serial Flash
Memory, with advanced write protection mecha­nisms, accessed by a high spee d SPI-compatible
bus.

The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.

The memory is organized as 16 sectors, each con­taining 256 pages. Each page is 256 byt es wide.
Thus, the whole memory can be viewed as con­sisting of 4096 pages, or 1,048,576 bytes.

The whole memory can b e erased using t he Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.

Figure 2. Logic Diagram

V

CC

Figure 3. VD FP N a nd SO8 C onnections

M25P80

SV

1
2

W

3
4

SS

8
7
6
5

AI04965B

CC

HOLDQ
C
DV

M25P80

D
C
S

M25P80

W

HOLD

V

SS

Table 1. Signal Names

C Serial Clock
D Serial Data Input
Q Serial Data Output

S

Write Protect

W
HOLD

Hold

Chip Select

Q

Note: 1. There is an expose d die paddle on the unde rside of th e

MLP8 package. This is pulled, internally, to V
must not be allowed to be connected to any other voltage
or signal line on the PCB.

2. See PACKAGE MECHANICAL section for package di­mensions, and how to identify pi n-1.

SS

, and

Figure 4. SO16 Connec tions

AI04964

HOLD

V

CC

DU
DU
DU

M25P80

C

16

1
2
3
4
5
6

S

7
8

AI09712

15
14
13
12
11
10

D
DUDU
DU
DU
DU
V

SS

WQ

9

V

CC

V

SS

Supply Voltage
Ground

Note: 1. DU = Don’t Us e

2. See PACKAGE MECHANICAL section for package di­mensions, and how to identify pi n-1.

5/41

M25P80

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).

Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in­structions, addresses, and the data to be pro­grammed. Values are latched on the rising edge of
Serial Clock (C).

Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address­es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).

Chip Select (S

the device is des elected and Serial Data Ou tput
(Q) is at high impedance. Unless an internal Pro­gram, Erase or Write Status Register cycle is in
progress, the device w ill be in the S tandby mode

). When this input signal is High,

(this is not the Deep Power-down mode). Driving
Chip Selec t ( S
in the active power mode.

After Power-up, a falling edge on Chip Select (S
is required prior to the start of any instruction.

Hold (HOLD

pause any serial communications with the device
without deselecting the device.

During the Hold condition, the Serial Data Output
(Q) is high impedanc e, and Serial D ata Input (D)
and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be se­lected, wit h Ch ip Select (S

Write Protect (W

put signal is to freeze the size of the area of mem­ory that is protected against program or erase
instructions (as specified by the values in the BP2,
BP1 and BP0 bits of the Status Register).

) Low enables the device, placing it

). The Hold (HOLD) signal is used to

) driven Low.

). The main purpose of this in-

)

6/41

SPI MODES

These devices can be drive n by a microcont roller
with its SPI peripheral running in either of the two
following modes:

– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latc hed in on

the rising edge of Serial Clock (C), and output data

Figure 5. Bus Master and Memory Devices on the SPI Bus

is avai lable from t he falling edge of S erial Clock
(C).

The difference between the two modes, as shown
in Figure 6., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:

– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)

M25P80

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

Bus Master

(ST6, ST7, ST9,

ST10, Others)

CS3 CS2 CS1

Note: The Write Protect (W) and Hold (HOLD) signals sh oul d be driven, High or Low as appropriate.

SDO
SDI
SCK

CQD

SPI Memory

Device

S

CQD

SPI Memory

Device

HOLD

W

S

W

Figure 6. SPI Mo de s S upported

CPHA

CPOL

HOLD

CQD

SPI Memory

Device

S

W

AI03746D

HOLD

0

0

1

1

C

C

D

Q

MSB

MSB

AI01438B

7/41

M25P80

OPERATING FEAT URES

Page Prog ram m i ng

To program one data byte, two instructions are re­quired: Write Enable (WREN), which is one by te,
and a Page Program (PP) sequence, which con­sists of four bytes plus data. This is followed by the
internal Program cycle (of duration t

To spread this overhead, the Page P rogram (PP)
instruction allows up to 256 bytes to be pro­grammed at a time (changing bits from 1 to 0), pro­vided that they lie in consecutive addresses on the
same page of memory.

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to hav e been erased to a ll
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration t

or tBE).

SE

The Erase instruction must be preceded by a Write
Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by n ot waiting for the worst
case delay (t

, tPP, tSE, or tBE). The Write In

W

Progress (WIP) bit is provided in the Status Regis­ter so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is com­plete.

Active Power , Sta nd - by Power and Deep Power-Down Modes

When Chip Select (S

) is Low, the device is en-

abled, and in the Active Power mode.
When Chip Select (S

) is High, the device is dis­abled, but could remain in the Active Power mode
until all internal cycles have completed (Program,

PP

).

Erase, Write Status Register). The device then
goes in to the S tand-by Power m ode. The device
consumption drops to I

CC1

.

The Deep Power-down mode is entered when the
specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device
consumption drops further to I

. The device re-

CC2

mains in this mode until another specific instruc­tion (the Release from Deep Power-down Mode
and Read Electro nic Signature (RE S) instruction)
is executed.

All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mecha nism,
when the device is not in active use, to protect the
device from inadvertent Write, Pr ogram or Erase
instructions.

Status Register

The Status Register contains a number of status
and control bits that can be read or set (as appro­priate) by specific instructions.

WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle.

WEL bit. The Write Enable Latch (WEL) bit i ndi­cates the status of the internal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Program and Erase instructions.

SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W

) signal. The Status Register
Write Disable (SRWD) bit an d Write Protect (W
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0)
become read-only bits.

)

8/41

M25P80

Protectio n Modes

The environments where non-volatile memory de­vices are used can be very noisy. No SPI dev ice
can operate correctly in the presence of excessive
noise. To help combat this, the M25P80 boasts the
following data protection mechanisms:

■ Power-On Reset and an internal timer (t

PUW

can provide protection against inadvertant
changes while the power supply is outside the
operating specification.

■ Program, Erase and Write Status Register

instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.

■ All instructions that modify data must be

preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit . This bit is returned to its reset state
by the following events:

– Power-up
– Write Disable (WRDI) instruction

)

– Write Status Register (WRSR) instruction

completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion

■ The Block Prote ct (BP2, BP1, BP0 ) b its allow

part of the memory to be configured as read­only. This is the Software Protected Mode
(SPM).

■ The Write Protect (W) signal allows the Block

Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be
protected. This is the Hardware Protected
Mode (HPM).

■ In addition to the low power consumption

feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power­down instruction).

completion

Table 2. Protected Area Sizes

Status Register

Content

BP2

Bit

BP1

Bit

0 0 0 none
0 0 1 Upper sixteenth (Sector 15) Lower fifteen-sixteenths (fifteen sectors: 0 to 14)

BP0

Bit

Protected Area Unprotected Area

Memory Content

All sectors

1

(sixteen sectors: 0 to 15)

0 1 0 Upper eighth (two sectors: 14 and 15) Lower seven-eighths (fourteen sectors: 0 to 13)
0 1 1 Upper quarter (four sectors: 12 to 15) Lower three-quarters (twelve sectors: 0 to 11)
1 0 0 Upper half (eight sectors: 8 to 15) Lower half (eight sectors: 0 to 7)
1 0 1 All sectors (sixteen sectors: 0 to 15) none
1 1 0 All sectors (sixteen sectors: 0 to 15) none
1 1 1 All sectors (sixteen sectors: 0 to 15) none

Note: 1. The device is ready to accept a Bulk Erase inst ruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.

9/41

M25P80

Hold Condition

The Hold (HOLD

) signal is used to pause any se­rial communications with the device without reset­ting the clocking sequence. Howev er, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.

To enter the Hold condition, the device must be
selecte d, with Chip Selec t (S

) Low.

The Hold condition starts on the falling edge of the
Hold (HOLD

) signal, provided that t his coincides
with Serial Clock (C) being Low (as shown i n Fig-

ure 7.).

The Hold condition ends on the rising edge of the
Hold (HOLD

) signal, provided that t his coincides
with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts af­ter Serial Clock (C) next goes Low. Similarly, if the

Figure 7. Hold Condition Activation

C

rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (This is shown in Figure

7.).

During the Hold condition, the Serial Data Output
(Q) is high impedanc e, and Serial D ata Input (D)
and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip
Select (S

) driven Low, for the whole duration of the
Hold condition. This is to en sure that the state of
the internal logic remains unchanged from the mo­ment of entering the Hold condition.

If Chip Select (S

) goes High while the d ev ice is in
the Hold condition, this has the ef fect of resett ing
the internal logic of the device. To restart commu­nication with the device, it is necessary to drive
Hold (HOLD

) Low. This prevents the device from going back

(S

) High, and then to drive Chip Select

to the Hold condition.

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

AI02029D

10/41

MEMOR Y ORGANIZATION

The memory is organized as:

■ 1,048,576 bytes (8 bits each)

■ 16 sectors (512 Kbits, 65536 bytes each)

■ 4096 pages (256 bytes each).

Table 3. Memory Organization

Sector Address Range

15 F0000h FFFFFh
14 E0000h EFFFFh
13 D0000h DFFFFh
12 C0000h CFFFFh
11 B0000h BFFFFh
10 A0000h AFFFFh

9 90000h 9FFFFh
8 80000h 8FFFFh
7 70000h 7FFFFh
6 60000h 6FFFFh
5 50000h 5FFFFh

M25P80

Each page can be individually pro grammed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.

4 40000h 4FFFFh
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh

11/41

M25P80

Figure 8. Block Diagram

HOLD

W

S

C

D

Q

Control Logic

Address Register

and Counter

Y Decoder

High Voltage

Generator

I/O Shift Register

256 Byte

Data Buffer

Status

Register

FFFFFh

Size of the

read-only

memory area

12/41

00000h

000FFh

256 Bytes (Page Size)

X Decoder

AI04987

INSTRUCTIONS

All instructions, addresses and data are shifted in
and out of the device, most significant bit first.

Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S

) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).

The instruction set is listed in Tab le 4..
Every instruction sequence starts with a one-byte

instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR) or Release from Deep
Power-down, and Read Electronic Signature
(RES) instruction, the shifted-in instruction se-

Table 4. Instruction Set

Instruction Description One-byte Instruction Code

WREN Write Enable 0000 0110 06h 0 0 0

quence is followed by a data-out sequ ence. Chip
Selec t (S

) can be driven High after any bit of the

data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase

(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Sele ct (S

) must be driven High exactly at a
byte boundary, otherwise the instruction is reject­ed, and is not executed. That is, Chip Select (S
must driven High when the number of clock pulses
after Chip Select (S

) being driven Low is an exact

multiple of eight.
All attempts to access the memory array during a

Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy­cle continues unaffected.

Address

Bytes

Dummy

Bytes

M25P80

)

Data

Bytes

WRDI Write Disable 0000 0100 04h 0 0 0

RDSR Read Status Register 0000 0101 05h 0 0 1 to

WRSR Write Status Register 0000 0001 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0

RES

Release from Deep Power-down,
and Read Electronic Signature

Release from Deep Power-down 0 0 0

1010 1011 ABh

0 3 1 to

∞

∞

∞

13/41