ST M24C64-A125 User Manual

M24C64-A125

Automotive 64-Kbit serial I²C bus EEPROM with 1 MHz clock

Features

■Compatible with all I2C bus modes

–1 MHz

–400 kHz

–100 kHz

■Memory array

–64 Kbit (8 Kbytes) of EEPROM

–Page size: 32 bytes

–Additional Write lockable page (Identification page)

■Extended temperature and voltage ranges

–-40 °C to 125 °C; 1.8 V to 5.5 V

■Schmitt trigger inputs for noise filtering

■Short Write cycle time

–Byte Write within 4 ms

–Page Write within 4 ms

■Write cycle endurance

–4 million Write cycles at 25 °C

–1.2 million Write cycles at 85 °C

–600 k Write cycles at 125 °C

■Data retention

–40 years at 55 °C

–100 years at 25 °C

■ESD Protection (Human Body Model)

–4000 V

■Packages

–RoHS compliant and halogen-free (ECOPACK®)

Datasheet − preliminary data

TSSOP8 (DW) 169 mil width

SO8 (MN) 150 mil width

UFDFPN8 (MC) 2 x 3 mm

July 2012

Doc ID 023023 Rev 2

1/37

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to	www.st.com
change without notice.

Contents	M24C64-A125

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				. 6
2	Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				8
	2.1	Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			8
	2.2	Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			8
	2.3	Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			8
	2.4	Write Control			8
			(WC)
	2.5	VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			9
	2.6	Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			9
3	Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				10
	3.1	Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			11
	3.2	Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			11
	3.3	Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			11
	3.4	Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			11
	3.5	Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			12
	3.6	Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			13
4	Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				15
	4.1	Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			15

4.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.4 Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.5 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.4 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/37	Doc ID 023023 Rev 2

M24C64-A125		Contents
5	Application design recommendations . . . . . . . . . . . . . . . . . . . . .	. . . . 23
	5.1 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 23

5.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 24

6	Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
7	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
8	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
10	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36

Doc ID 023023 Rev 2

3/37

List of tables	M24C64-A125

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Device identification bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32 Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 33 Table 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/37	Doc ID 023023 Rev 2

M24C64-A125	List of figures

List of figures

Figure 1.	Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 2.	8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 3.	Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
Figure 4.	I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 5.	Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 6.	Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 7.	Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 8.	Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 9.	AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 10.	Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
	bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 11.	Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C
	bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 12.	AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 13.	TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 14.	SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . .	33
Figure 15.	UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . .	34

Doc ID 023023 Rev 2

5/37

Description	M24C64-A125

1 Description

The M24C64-A125 is a 64-Kbit serial EEPROM Automotive grade device operating up to 125 °C. The M24C64-A125 is compliant with the very high level of reliability defined by the Automotive standard AEC-Q100 grade 1.

The device is accessed by a simple serial I2C compatible interface running up to 1 MHz.

The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M24C64-A125 is a byte-alterable memory (8192 × 8 bits) organized as 256 pages of 32 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic.

The M24C64-A125 offers an additional Identification Page (32 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

Figure 1. Logic diagram

7#
%				#ONTROLTLOGIC				(IGH VOLTAGE
%								GENERATOR
%

3#,
3$!	) / SHIFTSREGISTER

!DDRESSRREGISTER	$ATA
ANDNCOUNTER	REGISTER
99DECODER
	PAGE
	)DENTIFICATION PAGE
	88DECODER

-3 6

6/37	Doc ID 023023 Rev 2

M24C64-A125

Description

Table 1.

Signal names

Signal name

Function

Direction

E2, E1, E0

Chip Enable

Input

SDA

Serial Data

I/O

SCL

Serial Clock

Input

Write Control

Input

WC

VCC

Supply voltage

VSS

Ground

Figure 2.

8-pin package connections

%

6##

%

7#

%

3#,

633

3$!

!) F

1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.

Doc ID 023023 Rev 2

7/37

Signal description	M24C64-A125

2 Signal description

2.1Serial Clock (SCL)

The signal applied on this input is used to strobe the data available on SDA(in) and to output the data on SDA(out).

2.2Serial Data (SDA)

SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected between SDA and VCC (Figure 10 indicates how to calculate the value of the pull-up resistor).

2.3Chip Enable (E2, E1, E0)

(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs are read as low (0).

Figure 3. Device select code

VCC

VCC

M24xxx M24xxx

Ei							Ei
VSS							VSS

Ai12806

2.4Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating.

When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged.

8/37	Doc ID 023023 Rev 2

M24C64-A125	Signal description

2.5VSS (ground)

VSS is the reference for the VCC supply voltage.

2.6Supply voltage (VCC)

VCC is the supply voltage pin.

Doc ID 023023 Rev 2

9/37

Device operation	M24C64-A125

3 Device operation

The device supports the I2C protocol (see Figure 4).

The I2C bus is controlled by the bus master and the device is always a slave in all communications.

The device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data.

Figure 4. I2C bus protocol
SCL
SDA
	START		SDA	SDA		STOP
			Input	Change
	Condition					Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
	START
	Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
						STOP
						Condition
						AI00792B

10/37

Doc ID 023023 Rev 2

M24C64-A125	Device operation

3.1Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.

3.2Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master.

A Stop condition at the end of a Write instruction triggers the internal Write cycle.

3.3Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.

3.4Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.

Doc ID 023023 Rev 2

11/37

Device operation	M24C64-A125

3.5Device addressing

To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, as shown in Table 2.

The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable address (E2, E1, E0). A device select code handling any value other than 1010b (to select the memory) or 1011b (to select the Identification page) is not acknowledged by the memory device.

Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is received, the memory device only responds if the Chip Enable Address is the same as the value decoded on the E2, E1, E0 inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

Table 2.

Device select code

Device type identifier(1)

Chip Enable address(2)

RW

b7

b6

b5

b4

b3

b2

b1

b0

When accessing

1

0

1

0

E2

E1

E0

RW

the memory

When accessing

the Identification

1

0

1

1

E2

E1

E0

RW

page

1.The most significant bit, b7, is sent first.

2.E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2.

If a match occurs on the device select code, the corresponding memory device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not match the device select code, it deselects itself from the bus, and goes into Standby mode.

Once the memory device has acknowledged the device select code (Table 2), the memory device waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The memory device responds to each address byte with an acknowledge bit.

12/37

Doc ID 023023 Rev 2