Automotive 64-Kbit serial I²C bus EEPROM with 1 MHz clock
TSSOP8 (DW)
SO8 (MN)
169 mil width
150 mil width
UFDFPN8 (MC)
2 x 3 mm
Features
®
)
2
C bus modes
■ Compatible with all I
–1MHz
– 400 kHz
– 100 kHz
■ Memory array
– 64 Kbit (8 Kbytes) of EEPROM
– Page size: 32 bytes
– Additional Write lockable page
(Identification page)
■ Extended temperature and voltage ranges
– -40 °C to 125 °C; 1.8 V to 5.5 V
■ Schmitt trigger inputs for noise filtering
■ Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
■ Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
■ Data retention
– 40 years at 55 °C
– 100 years at 25 °C
■ ESD Protection (Human Body Model)
– 4000 V
■ Packages
– RoHS compliant and halogen-free
(ECOPACK
M24C64-A125
Datasheet − preliminary data
July 2012 Doc ID 023023 Rev 2 1/37
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents M24C64-A125
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC
2.5 V
(ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
2.6 Supply voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.3 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.4 Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.5 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.4 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.5 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.6 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/37 Doc ID 023023 Rev 2
M24C64-A125 Contents
5 Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Operating supply voltage V
5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 023023 Rev 2 3/37
List of tables M24C64-A125
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Device identification bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32
Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 33
Table 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4/37 Doc ID 023023 Rev 2
M24C64-A125 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. I
Figure 5. Write mode sequences with WC
Figure 6. Write mode sequences with WC
Figure 7. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Maximum R
Figure 11. Maximum R
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 33
Figure 15. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . 34
2
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
= 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
= 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
value versus bus parasitic capacitance (C
bus
bus at maximum frequency f
value versus bus parasitic capacitance C
bus
bus at maximum frequency f
= 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
C
= 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
C
) for an I2C
bus
) for an I2C
bus
Doc ID 023023 Rev 2 5/37
Description M24C64-A125
-36
7#
#ONTROLLOGIC
(IGHVOLTAGE
GENERATOR
)/SHIFTREGISTER
!DDRESSREGISTER
ANDCOUNTER
$ATA
REGISTER
PAGE
8DECODER
9DECODER
)DENTIFICATIONPAGE
%
%
%
3#,
3$!
1 Description
The M24C64-A125 is a 64-Kbit serial EEPROM Automotive grade device operating up to
125 °C. The M24C64-A125 is compliant with the very high level of reliability defined by the
Automotive standard AEC-Q100 grade 1.
The device is accessed by a simple serial I
The memory array is based on advanced true EEPROM technology (Electrically Erasable
PROgrammable Memory). The M24C64-A125 is a byte-alterable memory (8192 × 8 bits)
organized as 256 pages of 32 bytes in which the data integrity is significantly improved with
an embedded Error Correction Code logic.
The M24C64-A125 offers an additional Identification Page (32 bytes) in which the ST device
identification can be read. This page can also be used to store sensitive application
parameters which can be later permanently locked in read-only mode.
Figure 1. Logic diagram
2
C compatible interface running up to 1 MHz.
6/37 Doc ID 023023 Rev 2
M24C64-A125 Description
3$!6
33
3#,
7#%
% 6
##
%
!)F
Table 1. Signal names
Signal name Function Direction
E2, E1, E0 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC Write Control Input
V
CC
V
SS
Supply voltage
Ground
Figure 2. 8-pin package connections
1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Doc ID 023023 Rev 2 7/37
Signal description M24C64-A125
Ai12806
V
CC
M24xxx
V
SS
E
i
V
CC
M24xxx
V
SS
E
i
2 Signal description
2.1 Serial Clock (SCL)
The signal applied on this input is used to strobe the data available on SDA(in) and to output
the data on SDA(out).
2.2 Serial Data (SDA)
SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull up resistor must be connected between SDA and V
to calculate the value of the pull-up resistor).
2.3 Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Ta bl e 2 ). These inputs must
be tied to V
are read as low (0).
or VSS, as shown in Figure 3. When not connected (left floating), these inputs
CC
(Figure 10 indicates how
CC
Figure 3. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC
driven low or left floating.
When Write Control (WC
acknowledged, Data bytes are not acknowledged.
) is driven high. Write operations are enabled when Write Control (WC) is either
) is driven high, device select and address bytes are
8/37 Doc ID 023023 Rev 2
M24C64-A125 Signal description
2.5 VSS (ground)
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
VCC is the supply voltage pin.
Doc ID 023023 Rev 2 9/37
Device operation M24C64-A125
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1 23 7 89
MSB
ACK
START
Condition
SCL
1 23 7 89
MSB ACK
STOP
Condition
3 Device operation
The device supports the I2C protocol (see Figure 4).
2
The I
C bus is controlled by the bus master and the device is always a slave in all
communications.
The device (bus master or a slave) that sends data on to the bus is defined as a transmitter;
the device (bus master or a slave) is defined as a receiver when reading the data.
Figure 4. I
2
C bus protocol
10/37 Doc ID 023023 Rev 2
M24C64-A125 Device operation
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
3.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
3.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.
th
clock pulse period, the receiver pulls Serial Data (SDA) low to
Doc ID 023023 Rev 2 11/37
Device operation M24C64-A125
3.5 Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Ta bl e 2 .
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
address (E2, E1, E0). A device select code handling any value other than 1010b (to select
the memory) or 1011b (to select the Identification page) is not acknowledged by the memory
device.
Up to eight memory devices can be connected on a single I
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the memory device only responds if the Chip Enable Address is the same as the
value decoded on the E2, E1, E0 inputs.
th
The 8
Table 2. Device select code
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2.
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
(1)
When accessing
the memory
When accessing
the Identification
page
Device type identifier
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 E2 E1 E0 RW
1 0 1 1 E2 E1 E0 RW
2
C bus. Each one is given a
Chip Enable address
(2)
RW
If a match occurs on the device select code, the corresponding memory device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the memory device does not
match the device select code, it deselects itself from the bus, and goes into Standby mode.
Once the memory device has acknowledged the device select code (Ta b le 2 ), the memory
device waits for the master to send two address bytes (most significant address byte sent
first, followed by the least significant address byte (Tab le 3 ). The memory device responds
to each address byte with an acknowledge bit.
12/37 Doc ID 023023 Rev 2
M24C64-A125 Device operation
Table 3. Significant bits within the two address bytes
Most significant
Least significant
Memory
(Device type identifier =
1010b)
Random
Address
Read
b15 X X X X X X
b14 X X X X X X
b13 X X X X X X
b12 A12 A12 X X X X
b11 A11 A11 X X X X
address byte
b10 A10 A10 X010
b9 A9 A9 X X X X
b8 A8 A8 X X X X
b7 A7 A7 X X X X
b6 A6 A6 X X X X
b5 A5 A5 X X X X
b4 A4 A4 A4 A4 X X
b3 A3 A3 A3 A3 X X
address byte
b2 A2 A2 A2 A2 X X
b1 A1 A1 A1 A1 X X
b0 A0 A0 A0 A0 XX
Write
Read
Identification
page
Identification page
(Device type identifier = 1011b)
Write
Identification
page
Lock
Identification
page
Read
lock
status
1. A: significant address bit.
2. X: bit is Don’t Care.
3.6 Identification page
The M24C64-A125 offers an Identification Page (32 bytes) in addition to the 64 Kbit
memory. This page can be used for several purposes:
● Device identification: the three first bytes of the Identification page are programmed by
STMicroelectronics with the Device identification code, as shown in Tab le 4 .
● Storage of specific parameters: each byte in the Identification page can be written if the
Identification page is not permanently locked in Read-only mode.
● Write protection: once the application-specific parameters are written in the
Identification page, the whole Identification page can be permanently locked in read
only mode.
Read, write and lock Identification Page are detailed in Section 4: Instructions.
Doc ID 023023 Rev 2 13/37
Device operation M24C64-A125
Table 4. Device identification bytes
Address in
Identification page
00h ST manufacturer code 20h
01h I
02h Memory density code 0
Content Value
2
C family code E0h
Dh (64 Kbit)
14/37 Doc ID 023023 Rev 2
M24C64-A125 Instructions
4 Instructions
4.1 Write operations
For a Write operation, the bus master sends a Start condition followed by a device select
code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and
waits for the master to send two address bytes (most significant address byte sent first,
followed by the least significant address byte (Tab l e 3 ). The device responds to each
address byte with an acknowledge bit, and then waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
cycle t
internal Write cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
After the successful completion of an internal Write cycle (t
counter is automatically incremented to point to the next byte after the last modified byte.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 6.
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
is then triggered. A Stop condition at any other time slot does not trigger the
W
), the device internal address
W
Doc ID 023023 Rev 2 15/37
Instructions M24C64-A125
Stop
Start
Byte Write Dev sel Byte addr
Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01106d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
4.1.1 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC
device replies with NoAck, and the location is not modified (see Figure 6). If, instead, the
addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in Figure 5.
) being driven high, the
Figure 5. Write mode sequences with WC
= 0 (data write enabled)
16/37 Doc ID 023023 Rev 2
M24C64-A125 Instructions
Stop
Start
Byte Write Dev sel Byte addr Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01120d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
4.1.2 Page Write
The Page Write mode allows up to N
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
The bus master sends from 1 to N
device if Write Control (WC
) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte received by the device is
not acknowledged, as shown in Figure 6. After each byte is transferred, the internal byte
address counter is incremented. The transfer is terminated by the bus master generating a
Stop condition.
(a)
bytes to be written in a single Write cycle, provided
(a)
bytes of data, each of which is acknowledged by the
Figure 6. Write mode sequences with WC
= 1 (data write inhibited)
a. N is the number of bytes in a page.
Doc ID 023023 Rev 2 17/37
Instructions M24C64-A125
4.1.3 Write Identification Page
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
● Device type identifier = 1011b
● Most significant address bits A15/A5 are don't care, except for address bit A10 which
must be “0”. Least significant address bits A4/A0 define the byte location inside the
Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
4.1.4 Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
● Device type identifier = 1011b
● Address bit A10 must be ‘1’; all other address bits are don't care
● The data byte must be equal to the binary value xxxx xx1x, where x is don't care
18/37 Doc ID 023023 Rev 2
M24C64-A125 Instructions
Write cycle
in progress
AI
d
AI01847e
Next
Operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write cperation
Device select
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO
StartCondition
Continue the
Write operation
Continue the
Random Read operation
4.1.5 Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 7, is:
● Initial condition: a Write cycle is in progress.
● Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
● Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 7. Write cycle polling flowchart using ACK
01847
Doc ID 023023 Rev 2 19/37
Instructions M24C64-A125
3TART
$EVSEL "YTEADDR "YTEADDR
3TART
$EVSEL $ATAOUT
!)E
$ATAOUT.
3TOP
3TART
#URRENT
!DDRESS
2EAD
$EVSEL $ATAOUT
2ANDOM
!DDRESS
2EAD
3TOP
3TART
$EVSEL $ATAOUT
3EQUENTIAL
#URRENT
2EAD
3TOP
$ATAOUT.
3TART
$EVSEL "YTEADDR "YTEADDR
3EQUENTIAL
2ANDOM
2EAD
3TART
$EVSEL $ATAOUT
3TOP
!#+
27
./!#+
!#+
27
!#+ !#+ !#+
27
!#+ !#+ !#+ ./!#+
27
./!#+
!#+ !#+ !#+
27
!#+ !#+
27
!#+ ./!#+
4.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
Figure 8. Read mode sequences
4.2.1 Random Address Read
The Random Address Read is a sequence composed of a truncated Write sequence (to
define a new address pointer value, see Ta b le 3 ) followed by a current Read.
The Random Address Read sequence is therefore the sum of [Start + Device Select code
with RW=0 + two address bytes] (without Stop condition, as shown in Figure 8)] and [Start
condition + Device Select code with RW=1]. The memory device acknowledges the
sequence and then outputs the contents of the addressed byte. To terminate the data
transfer, the bus master does not acknowledge the last data byte and then issues a Stop
condition.
20/37 Doc ID 023023 Rev 2
M24C64-A125 Instructions
4.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W
outputs the byte pointed by the internal address counter. The counter is then incremented.
The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without
acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the Identification page byte location, when accessing the memory, it is
safer to always use the Random Address Read instruction (this instruction loads the
address counter with the byte location to read in the memory) instead of the Current
Address Read instruction.
bit set to 1. The device acknowledges this, and
4.2.3 Sequential Read
A sequential Read can be used after a Current Address Read or a Random Address Read.
After a Read instruction, the device can continue to output the next byte(s) in sequence if
the bus master sends additional clock pulses and if the bus master does acknowledge each
transmitted data byte. To terminate the stream of bytes, the bus master must not
acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8.
The sequential read is controlled with the device internal address counter which is
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
4.2.4 Read Identification Page
The Identification Page can be read by issuing a Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The most significant address bits A15/A5
are don't care and the least significant address bits A4/A0 define the byte location inside the
Identification page. The number of bytes to read in the ID page must not exceed the page
boundary.
4.2.5 Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit after the data byte if the Identification page is
unlocked, otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
● Start: the truncated command is not executed because the Start condition resets the
device internal logic,
● Stop: the device is then set back into Standby mode by the Stop condition.
Doc ID 023023 Rev 2 21/37
Instructions M24C64-A125
4.2.6 Acknowledge in Read mode
For all Read instructions, the device waits, after each byte sent out, for an acknowledgment
during the 9th bit time. If the bus master does not send the Acknowledge (the master drives
SDA high during the 9th bit time), the device terminates the data transfer and enters its
Standby mode.
22/37 Doc ID 023023 Rev 2
M24C64-A125 Application design recommendations
5 Application design recommendations
5.1 Supply voltage
5.1.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Tab l e 7 ).
CC
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal Write cycle (t
secure a stable DC supply voltage, it is recommended to decouple the V
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
pins.
5.1.2 Power-up conditions
When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up to
the minimum V
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V
threshold voltage (this threshold is defined in the DC characteristic Ta bl e 1 0 as V
When V
● in the Standby power mode
● deselected
passes over the POR threshold, the device is reset and in the following state:
CC
As soon as the V
range (defined in Tab le 7 ), the device is ready for operation.
operating voltage defined in Ta bl e 7 .
CC
voltage has reached a stable value within the [VCC(min), VCC(max)]
CC
CC
). In order to
W
line with a
CC
CC/VSS
reaches the internal
CC
package
RES
).
5.1.3 Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
V
operating voltage defined in Ta bl e 7 ), the device must be in Standby power mode (that
CC
is after a STOP condition or after the completion of the Write cycle t
cycle is in progress).
if an internal Write
W
Doc ID 023023 Rev 2 23/37
Application design recommendations M24C64-A125
5.2 Cycling with Error Correction Code (ECC)
The Error Correction Code (ECC) is an internal logic function which is transparent for the
2
I
C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group
(b)
. As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Tab le 6 .
Example 1: maximum cycling limit reached with 1 million cycles per byte
Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group
cycling budget is 4 million cycles.
Example 2: maximum cycling limit reached with unequal byte cycling
(b)
. Inside a group, if a
Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times,
byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million
cycles.
b. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
24/37 Doc ID 023023 Rev 2
M24C64-A125 Delivery state
6 Delivery state
The device is delivered with:
● the memory array set to all 1s (each byte = FFh),
● Identification page:
– the first three bytes define the device identification (value defined in Ta bl e 4 )
– the 29 following bytes set to FFh.
7 Maximum rating
Stressing the device outside the ratings listed in Ta bl e 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
T
STG
T
LEAD
V
IO
I
OL
V
CC
V
ESD
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω)
Storage temperature –65 150 °C
Lead temperature during soldering see note
(1)
Input or output range –0.50 6.5 V
DC output current (SDA = 0) - 5 mA
Supply voltage –0.50 6.5 V
Electrostatic pulse (Human Body model)
(2)
-4000V
°C
Doc ID 023023 Rev 2 25/37
DC and AC parameters M24C64-A125
-36
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
4IMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
8 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6. Cycling performance by groups of four bytes
Symbol Parameter Test condition Min. Max. Unit
Ncycle Write cycle endurance
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where
N is an integer, or for the status register byte (refer also to Section 5.2: Cycling with Error Correction Code (ECC)). The
Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or a Lock Identification Page
instruction is decoded. When using those Write instructions, refer also to Section 5.2: Cycling with Error Correction Code
(ECC).
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V 4,000,000
(1)
TA = 85 °C, 1.8 V < VCC < 5.5 V 1,200,000
TA = 125 °C, 1.8 V < V
Table 7. Operating conditions (voltage range R)
< 5.5 V 600,000
CC
Symbol Parameter Min. Max. Unit
Write
cycle
(2)
V
CC
T
Table 8. AC measurement conditions
Supply voltage 1.8 5.5 V
Ambient operating temperature –40 125 °C
A
Symbol Parameter Min. Max. Unit
C
bus
Load capacitance 100 pF
SCL input rise/fall time, SDA input fall time 50 ns
Input levels 0.2 V
Input and output timing reference levels 0.3 V
to 0.8 V
CC
to 0.7 V
CC
CC
CC
Figure 9. AC measurement I/O waveform
V
V
26/37 Doc ID 023023 Rev 2
M24C64-A125 DC and AC parameters
Table 9. Input parameters
Symbol Parameter
(1)
Test condition Min. Max. Unit
C
C
Z
Z
1. Characterized only, not tested in production.
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).
Table 10. DC characteristics
Symbol Parameter
I
LI
I
LO
I
CC
I
CC0
I
CC1
V
IL
Input capacitance (SDA) 8 pF
IN
Input capacitance (other pins) 6 pF
IN
L
Input impedance (E2, E1, E0, WC)
H
(2)
VIN < 0.3 V
VIN > 0.7 V
CC
CC
Test conditions (in addition to those
in Table 7 and Table 8)
Input leakage current
(SCL, SDA, E2, E1,
E0)
Output leakage
current
V
= VSS or V
IN
CC
device in Standby mode
SDA in Hi-Z, external voltage applied
on SDA: VSS or V
CC
Supply current (Read) 2 mA
Supply current (Write) During t
Standby supply
current
Device not selected
V
W
= VSS or V
IN
CC
(1)
,
Input low voltage
(SCL, SDA, WC
)
Input high voltage
(SCL, SDA)
V
IH
Input high voltage
(WC, E2, E1, E0)
= 2.1 mA, VCC = 2.5 V or
I
OL
= 3 mA, VCC = 5.5 V
I
V
Output low voltage
OL
OL
I
= 1 mA, VCC = 1.8 V 0.3 V
OL
30 kΩ
500 kΩ
Min. Max. Unit
± 2 µA
± 2 µA
2mA
10 µA
–0.45 0.3 V
0.7 V
CC
0.7 V
CCVCC
CC
6.5 V
+0.6 V
0.4 V
V
Internal reset
(1)
V
RES
1. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
threshold voltage
completion of the internal write cycle t
(tW is triggered by the correct decoding of a Write instruction).
W
0.5 1.3 V
Doc ID 023023 Rev 2 27/37
DC and AC parameters M24C64-A125
Table 11. 400 kHz AC characteristics
Symbol Alt. Parameter
(1)
Min. Max. Unit
t
CHCL
t
CLCH
t
QL1QL2
t
XH1XH2
t
XL1XL2
t
DXCX
t
CLDX
t
CLQX
t
CLQV
t
CHDL
t
DLCL
t
CHDH
t
DHDL
t
WLDL
t
DHWH
t
NS
f
t
W
C
(7)(2)
(8)(2)
(2)
(5)
(6)
(2)
f
SCL
t
HIGH
t
LOW
t
F
t
R
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
SU:WC
t
HD:WC
t
WR
Clock frequency - 400 kHz
Clock pulse width high 600 - ns
Clock pulse width low 1300 - ns
SDA (out) fall time
Input signal rise time
Input signal fall time
(3)
20 120 ns
(4)
(4) (4)
(4)
ns
ns
Data in set up time 100 - ns
Data in hold time 0 - ns
Data out hold time 100 - ns
Clock low to next data valid (access time) - 900 ns
Start condition setup time 600 - ns
Start condition hold time 600 - ns
Stop condition set up time 600 - ns
Time between Stop condition and next Start
condition
1300 - ns
WC set up time (before the Start condition) 0 - µs
WC hold time (after the Stop condition) 1 - µs
Write time - 4 ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-80ns
1. Test conditions (in addition to those in Table 7 and Table 8).
2. Characterized value, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
< 400 kHz.
C
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. t
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
CLQV
0.7V
, assuming that R
CC
bus
× C
time constant is within the values specified in Figure 10.
bus
28/37 Doc ID 023023 Rev 2
M24C64-A125 DC and AC parameters
Table 12. 1 MHz AC characteristics
Symbol Alt. Parameter
(1)
Min. Max. Unit
t
CHCL
t
CLCH
t
XH1XH2
t
XL1XL2
t
QL1QL2
t
DXCX
t
CLDX
t
CLQX
t
CLQV
t
CHDL
t
DLCL
t
CHDH
t
DHDL
t
WLDL
t
DHWH
t
NS
f
C
t
W
(3)
(4)
(5)
(6) (3)
(7) (3)
(3)
f
SCL
t
HIGH
t
LOW
t
R
t
F
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
SU:WC
t
HD:WC
t
WR
Clock frequency 0 1 MHz
Clock pulse width high 260 - ns
Clock pulse width low 400 - ns
Input signal rise time
Input signal fall time
(2)
(2) (2)
(2)
ns
ns
SDA (out) fall time - 120 ns
Data in setup time 50 - ns
Data in hold time 0 - ns
Data out hold time 100 - ns
Clock low to next data valid (access time) - 450 ns
Start condition setup time 250 - ns
Start condition hold time 250 - ns
Stop condition setup time 250 - ns
Time between Stop condition and next Start
condition
500 - ns
WC set up time (before the Start condition) 0 - µs
WC hold time (after the Stop condition) 1 - µs
Write time - 4 ms
Pulse width ignored (input filter on SCL and
SDA)
-80ns
1. Test conditions (in addition to those in Table 7 and Table 8).
2. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
f
<1MHz.
C
3. Characterized only, not tested in production.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. t
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
CLQV
0.7 V
, assuming that the Rbus × Cbus time constant is within the values specified in Figure 11.
CC
Doc ID 023023 Rev 2 29/37
DC and AC parameters M24C64-A125
AIB
"USLINECAPACITORP&
"USLINEPULLUPRESISTOR
K
)£#BUS
MASTER
-XXX
2
BUS
6
##
#
BUS
3#,
3$!
2
BUS
§#
BUS
NS
(ERE2
BUS
§#
BUS
NS
K½
P&
4HE2X#TIMECONSTANT
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
BUS
BUS
Figure 10. Maximum R
bus at maximum frequency f
Figure 11. Maximum R
bus at maximum frequency f
value versus bus parasitic capacitance (C
bus
value versus bus parasitic capacitance C
bus
= 400 kHz
C
= 1MHz
C
) for an I2C
bus
) for an I2C
bus
6
##
2
BU
§
S
#
BU
NS
"USLINEPULLUPRESISTORK
S
§
(ERE
NS
#
2
BUS
BUS
"USLINECAPACITORP&
4HE2
§#
TIMECONSTANT
BUS
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
BUS
)£#BUS
MASTER
3#,
3$!
2
BUS
#
-XXX
BUS
-36
30/37 Doc ID 023023 Rev 2
M24C64-A125 DC and AC parameters
3#,
3$!/UT
3#,
3$!)N
$ATAVALID
T#,16 T#,18
T#($(
3TOP
CONDITION
T#($,
3TART
CONDITION
7RITECYCLE
T7
!)G
$ATAVALID
T1,1,
3$!)N
T#($,
3TART
CONDITION
T$8#(T#,$8
3$!
)NPUT
3$!
#HANGE
T#($( T$($,
3TOP
CONDITION
3TART
CONDITION
T8(8(
3#,
T#(#,
T$,#,
T#,#(
T8(8(
T8,8,
T8,8,
7#
T7,$,
T$(7(
Figure 12. AC waveforms
Doc ID 023023 Rev 2 31/37
Package mechanical data M24C64-A125
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
(1)
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
1. Values in inches are converted from mm and rounded to four decimal digits.
32/37 Doc ID 023023 Rev 2
M24C64-A125 Package mechanical data
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
ccc 0.100 0.0039
D 4.900 4.800 5.000 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 0.0500
h 0.250 0.500 0.0098 0.0197
k 0°8° 0°8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
(1)
Doc ID 023023 Rev 2 33/37
Package mechanical data M24C64-A125
$
%
:7?-%E6
!
!
EEE
,
E B
$
,
%
,
0IN
+
Figure 15. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to V
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
. It must not be
SS
2 x 3 mm, data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MC) 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
(2)
eee
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
34/37 Doc ID 023023 Rev 2
M24C64-A125 Part numbering
10 Part numbering
Table 16. Ordering information scheme
Example: M24C64-D R MN 3 T P /K
Device type
2
M24 = I
C serial access EEPROM
Device function
C64-D = 64 Kbit (8192 x 8) plus identification page
Operating voltage
R = V
= 1.8 V to 5.5 V
CC
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
(1)
(1)
MC = MLP8 (2 × 3 mm)
Device grade
3 = -40 to 125 °C. Device tested with high reliability certified flow
(2)
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P = ECOPACK® (RoHS compliant)
Process
/K = Manufacturing technology code
1. RoHS-compliant and halogen-free (ECOPACK2®)
2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest
ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
Doc ID 023023 Rev 2 35/37
Revision history M24C64-A125
11 Revision history
Table 17. Document revision history
Date Revision Changes
23-Apr-2012 1 Initial release.
Updated Features (modes), Section 3.5: Device addressing,
Section 4.1.3: Write Identification Page, Section 4.1.4: Lock
Identification Page, Section 4.2.1: Random Address Read,
30-Jul-2012 2
Section 4.2.2: Current Address Read and Section 4.2.4: Read
Identification Page.
Added Table 3: Significant bits within the two address bytes.
Deleted Table 4: Most significant address byte and Table 5: Least
significant address byte.
36/37 Doc ID 023023 Rev 2
M24C64-A125
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