查询M24164-WBN1供应商
with 1 Inverting and 2 Non-Inverting Chip Enable Lines
M24164
16 Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■ Two Wire I
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24164
– 2.5V to 5.5V for M24164-W
■ Write Control Input
■ BYTE and PAGE WRITE (up to 16 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Tim e d P rogramming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
2
C Serial Interface
Figure 1. Packages
8
1
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
1/21October 2001
M24164
SUMMARY DESCRIPTION
The M24164 is a 16 Kbit (2048 x 8) electrically
erasable programmable memory (EEPROM ) accessed by an I
Figure 2. Logic Diagram
2
C-compatible bus .
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of t he data b yte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
V
CC
3
E0-E2 SDA
SCL
WC
M24164
V
SS
Table 1. Signal Names
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V
CC
V
SS
Write Control
Supply Voltage
Ground
AI02264
Figure 3. DIP Connections
M24164
1
E0 V
2
3
E2
4
SS
AI02265B
Figure 4. SO Connection s
M24164
E0 V
E2
SS
1
2
3
4
AI02266B
8
CC
7
WCE1
6
SCL
5
SDAV
8
CC
7
WCE1
6
SCL
5
SDAV
These devices are com pat ible with a two-wire serial interface that uses a bi-directional data bus
and serial clock. By setting the three chip enables
(E0, E1
vices can be attached to the s ame I
, E2) appropriately, up to eigh t 16 K bit de-
2
C bus, and
selected individually.
These devices behave as sla ve devices, with all
memory operations synchronized by the serial
clock. Read and Write operations are initiated by a
Start condition, generated by the bus master. The
Start condition is followed by a Device Select
Code and RW
bit (as described in Table 2), termi-
nated by an acknowledge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
2/21
th
bit time,
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
has reached the POR
CC
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
drops from the operating
CC
voltage, below the POR threshold value, all operations are disabled and the device will not respond
to any command. A stable and valid V
must be
CC
applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V
. (Figure 4
CC
indicates how the value of the pull-up resist or can
be calculated). In most applications, thoug h, this
method of synchronization is no t employed, and
so the pull-up resistor is not necessary, provided
that the bus maste r has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
. (Fig-
M24164
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1
These input signals are used to set the value that
is to be looked for on three bits (b6, b5, b4) of the
7-bit Device Select Code. These inputs must be
tied to V
or VSS, to establish the Device Select
CC
Code.
Write Control (WC
This input signal is useful for protecting the entire
contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC
driven High. When unconnected, the signal is internally read as V
lowed.
When Write Control (WC
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
, E2)
)
, and Write operations are al-
IL
) is driven High, Device
) is
Figure 5. Maximum R
20
16
12
8
Maximum RP value (kΩ)
4
0
10 1000
Value versus Bus Capacitance (C
L
fc = 100kHz
fc = 400kHz
100
C
(pF)
BUS
) for an I2C Bus
BUS
MASTER
V
CC
R
SDA
SCL
R
C
BUS
L
C
BUS
AI01665
L
3/21
M24164
DEVICE OPERATION
2
The device supports the I
C proto col. This is su m marized in Figure 2. Any device that sends data on
to the bus is defined to be a transmitter, a nd any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, w h ic h will als o provid e t h e s e r i a l c lo c k f or
synchronization. The M24164 d evice is always a
slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The devi ce continuously
monitors (except duri ng a Write cycle ) Se ri a l Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is give n.
Stop Condition
Stop is identified by a rising edg e of Serial Data
(SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condi tion to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EEPROM Wr ite cyc le.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
th
clock pulse period, the receiver pulls Serial
9
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change
only
when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication betwee n the bus master
and the slave device, the bus mas ter mus t initiate
a Start condition. Following this, t he bus master
sends eight bits, on Serial Data (SDA), most significant bit first. These consist of the 7-bit Device Select Code, and the Read/Write
bit (RW), as shown
in Table 2. This last bi t is set to 1 for Read, and 0
for Write operations.
The Device Select Code contains the three most
significant bits of the address within the memory
(A10, A9, A8), and a 3-bit Chip Ena ble “Add ress”
(E2, E1, E0).
When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip
Enable Address is the same as the value on the
Chip Enable (E0, E2, and the inverse of E1
) inputs. Up to eight devices can be connected on the
same bus, giving a total memory capacity of
128 K bi ts, 16 KBytes.
If a match occurs on the Device Select code , the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Standby mode.
Table 2. Device Select Code
Device
Type
Identifier
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 E2 E1 E 0 A10 A9 A8 RW
Note: 1. The most si gnifican t bit, b7, is se nt first.
4/21
1
Chip Enable Address Most Significant Address Bits RW
Figure 6. I2C Bus Protocol
SCL
SDA
M24164
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 789
MSB
1 23 789
MSB ACK
SDA
Input
SDA
Change
STOP
Condition
ACK
STOP
Condition
AI00792B
Table 3. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
0X
Random Address Read
1 X reSTART, Device Select, RW
Sequential Read 1 X
Byte Write 0 V
Page Write 0 V
Note: 1. X = V
IH
or V
.
IL
WC
1
Bytes Initial Sequence
START, Device Select, RW
1
1 Similar to Current or Random Address Read
≥
IL
IL
1 START, Device Select, RW = 0
16 START, Device Select, RW
≤
= 1
= 0, Address
= 1
= 0
5/21
M24164
Figure 7. Wri te M ode Sequences with WC=1 (data wri te inhib ite d)
WC
ACK ACK NO ACK
Byte Write DEV SEL BYTE ADDR DATA IN
R/W
START
WC
ACK ACK NO ACK NO ACK
Page Write DEV SEL BYTE ADDR
R/W
START
WC (cont'd)
NO ACK NO ACK
Page Write
(cont'd)
DATA IN N
STOP
STOP
DATA IN 1 DATA IN 2
DATA IN 3
AI02803C
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW
bit rese t to 0 .
The device acknowledges this, as shown in Figure
8, and waits for an address byte. The de vice responds to the address byte with an acknowle dge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC
with Write Control (WC
) is driven High. Any Write instruction
) driven High (during a period of time from the Start condition until the end of
the address byte) will not modify the memory contents, and the accompanying d ata bytes are
not
acknowledged, as shown in Figure 7.
When the bus mast er generates a Stop con dition
immediately after the Ack bi t (in t he “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
6/21
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Da ta (SDA)
is disabled internally, and the devi ce does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC
) being driven High, the device replies with
NoAck, and the location is not modified. If, instead,
the addressed location is not Write-protected, the
device replies with Ack. The bus master terminates the transfer by generating a Stop condit ion,
as shown in Figure 8.
Page Write
The Page Write mode allows u p to 16 by tes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
M24164
that is, the most significant m emory address bits
are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘rollover’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends fr om 1 to 16 bytes of data,
each of which is acknowledged by the device if
Figure 8. Wri te Mo de S e qu e nces with WC
WC
BYTE WRITE DEV SEL BYTE ADDR DATA IN
R/W
START
WC
=0 (data write enabled)
ACK
ACK ACK ACK ACK
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory location are not modified, and each dat a byte is followed by a NoAck. After each byt e is transferred,
the internal byte address counte r (the 4 least s ignificant address bits only) is incremented. The
transfer is terminated by the bus master generating a Stop condition.
ACK ACK
STOP
PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
R/W
START
WC (cont'd)
ACKACK
PAGE WRITE
(cont'd)
DATA IN N
STOP
DATA IN 3
AI02804
7/21
M24164
Figure 9. Wri te Cy cle Pol l in g Fl owchart usin g A C K
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
NO
Returned
First byte of instruction
with RW = 0 already
decoded by the device
ReSTART
STOP
YES
Next
Operation is
Addressing the
Memory
DATA for the
WRITE Operation
Continue the
WRITE Operation
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
) is shown in Tables
w
11 and 12, but the typical time is shorter. To make
use of this, a polling sequence can be used by the
bus master.
The sequence, as shown in Figure 9, is:
– Initial condition: a Write cycle is in progress.
YESNO
Send Address
and Receive ACK
START
Condition
YESNO
DEVICE SELECT
with RW = 1
Continue the
Random READ Operation
AI01847C
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
8/21
Figure 10. Read Mode Sequences
M24164
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
DEV SEL DATA OUT
R/W
START
ACK
DEV SEL * BYTE ADDR
R/W
START
ACK ACK ACK NO ACK
DEV SEL DATA OUT 1
R/W
START
ACK ACK
DEV SEL * BYTE ADDR
NO ACK
STOP
ACK ACK
DEV SEL * DATA OUT
START
DEV SEL * DATA OUT 1
NO ACK
R/W
DATA OUT N
ACK ACK
STOP
STOP
R/W
START
ACK NO ACK
DATA OUT N
STOP
Note: 1. The sev en m ost significant bits o f the Device Sel ect Code of a Random Read (in the 1st and 3rd bytes) must be identic al .
Read Operations
Read operations are performed independently of
the state of the Write Control (WC
) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as s hown in Figure 10 )
but
without
sending a Stop condition. Then, the
bus master sends another Start condition, and repeats the Device Select Code, with the RW
bit set
to 1. The device acknowledges this, and outputs
START
ter must
not
the transfer with a Stop condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device Select Code with the RW
knowledges this, an d outpu ts the byt e address ed
by the internal address counter. The counter is
then incremented. The bus master t erm inates t he
R/W
AI01942
acknowledge the byte, and terminates
bit set to 1. The device ac-
the contents of the addressed byte. The bus mas-
9/21
M24164
transfer with a Stop condition, a s shown i n Figure
10,
without
acknowledging the byte.
Sequenti a l Rea d
This operation can be used after a Current Address Read or a Random Address Read. The bus
does
master
acknowledge the data byte output,
and sends additional clock pulses so that the device continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must
not
acknowledge the last byte, and
must
generate a Stop condition, as shown in Figure 10.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
th
9
bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device terminates the data transfer and s witches to its St andby mode.
10/21
MAXI MUM RATI N G
Stressing the device ab ove the rating listed in t he
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions ab ove those i ndicated in t he
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and ot her relevant quality documents.
Operating sections of this specificat ion is not im-
Table 4. Absolute Maximum Ratings
Symbol Parameter Min. Max. Unit
T
STG
T
LEAD
V
IO
V
CC
V
ESD Electrostatic Discharge Voltage (Human Body model)
Note: 1. IPC/JEDEC J-STD-020 A
2. JE DEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Storage Temperature –65 150 °C
Lead Temperature during Soldering
PDIP: 10 seconds
SO: 20 seconds (max)
1
260
235
Input or Output range –0.6 6.5 V
Supply Voltage –0.3 6.5 V
2
–4000 4000 V
M24164
°C
11/21
M24164
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, and the DC and AC characteristics of the device. The parameters in t he DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
Table 5. Operating Conditions (M24164)
Symbol Parameter Min. Max. Unit
ment Conditions summarized in the relevant
tables. Designers should chec k th at the o perat ing
conditions in their circuit matc h the meas urement
conditions when relying on the quoted parameters.
V
CC
T
A
Supply Voltage 4.5 5.5 V
Ambient Operating Temperature 0 70 °C
Table 6. Operating Conditions (M24164-W)
Symbol Parameter Min. Max. Unit
V
CC
T
A
Supply Voltage 2.5 5.5 V
Ambient Operating Temperature 0 70 °C
Table 7. AC Measurement Conditions
Symbol Parameter Min. Max. Unit
C
L
Load Capacitance 30 pF
Input Rise and Fall Times 50 ns
to 0.8V
Input Pulse Voltages
Input and Output Timing Reference Voltages
Note: 1. Output H i- Z i s defined as the poi nt where data out is no lon ger driven .
0.2V
0.3V
CC
to 0.7V
CC
CC
CC
Figure 11. AC Measurement I/O Waveform
V
V
0.8V
0.2V
12/21
CC
CC
0.7V
0.3V
AI00825
CC
CC
Table 8. Capacitance
Symbol
C
IN
C
IN
t
NS
Note: 1. TA = 25 °C, f = 400 kHz
2. Sampled only, not 100% tested.
Input Capacitanc e (SDA) 8 pF
Input Capacitance (other pins) 6 pF
Pulse width ignored
(Input Filter on SCL and SDA)
Parameter
1,2
Table 9. DC Characteristics (M24164)
Symbol Parameter
Input Leakage Curren t
I
LI
(SCL, SDA)
Test Condition Min. Max. Unit
Single glitch 100 ns
(in addition to those in Table 5)
Test Condition
= VSS or V
V
IN
CC
Min. Max. Unit
± 2 µA
M24164
I
I
I
CC1
V
V
V
V
V
Output Leakage Current 0 V ≤ V
LO
CC
Supply Current
V
Stand-by Supply Current
Input Low Voltage
IL
IH
IL
IH
OL
1, E2, SCL, SDA)
(E0, E
Input High Voltage
, E2, SCL, SDA)
(E0, E1
Input Low Voltage (WC) – 0.3 0.5 V
Input High Voltage (WC) 0.7V
Output Low Voltage IOL = 3 mA, 4.5 V ≤ VCC ≤ 5.5 V 0.4 V
Table 10. DC Characteristics (M24164-W)
Symbol Parameter
Input Leakage Current
I
LI
(SCL, SDA)
I
I
I
CC1
V
Output Leakage Current 0 V ≤ V
LO
Supply Current
CC
Stand-by Supply Current
Input Low Voltage
IL
(E0, E
1, E2, SCL, SDA)
V
≤ V
OUT
=5V, fc=400kHz (ris e/fall time < 30ns)
CC
V
= VSS or V
IN
SDA in Hi-Z ± 2 µA
CC,
, VCC = 5 V
CC
Test Condition
(in addition to those in Table 6)
= VSS or V
V
IN
≤ V
OUT
=2.5V, fc=400kHz (rise/fall time < 30ns)
CC
V
= VSS or V
IN
CC
SDA in Hi-Z ± 2 µA
CC,
, VCC = 5 V
CC
2mA
20 µA
– 0.3 0.3V
0.7V
CC
CC
CC
VCC+1 V
VCC+1 V
Min. Max. Unit
± 2 µA
1mA
1µA
– 0.3 0.3V
CC
V
V
V
V
V
V
Input High Voltage
IH
(E0, E1
, E2, SCL, SDA)
Input Low Voltage (WC) – 0.3 0.5 V
IL
Input High Voltage (WC) 0.7V
IH
Output Low Voltage IOL = 2.1 mA, 2.5 V ≤ VCC ≤ 5.5 V 0.4 V
OL
0.7V
CC
CC
VCC+1 V
VCC+1 V
13/21
M24164
Table 11. AC Characteristics (M24164)
Test conditions specified in Table 7 and Table 5
Symbol Alt. Parameter Min. Max. Unit
f
C
t
CH1CH2
t
CL1CL2
t
CHCL
t
CLCH
2
t
DH1DH2
2
t
DL1DL2
t
DXCX
t
CLDX
t
CLQX
3
t
CLQV
1
t
CHDX
t
DLCL
t
CHDH
t
DHDL
t
W
Note: 1. For a reS T A RT conditio n, or following a Write cy cle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
f
SCL
t
t
t
HIGH
t
LOW
t
t
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency 400 kHz
R
F
Clock Rise Time 20 300 ns
Clock Fall Time 20 300 ns
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
R
F
SDA Rise Time 20 300 ns
SDA Fall Time 20 300 ns
Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
Clock Low to Next Data Valid (Access Time) 200 900 ns
Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start
Condition
1300 ns
Write Time 5 ms
14/21
Table 12. AC Characteristics (M24164-W)
Test conditions specified in Table 7 and Table 6
Symbol Alt. Parameter Min. Max. Unit
M24164
f
C
t
CH1CH2
t
CL1CL2
t
CHCL
t
CLCH
2
t
DH1DH2
2
t
DL1DL2
t
DXCX
t
CLDX
t
CLQX
3
t
CLQV
1
t
CHDX
t
DLCL
t
CHDH
t
DHDL
t
W
Note: 1. For a reS T A RT conditio n, or following a Write cy cle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
f
SCL
t
t
t
HIGH
t
LOW
t
t
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency 400 kHz
R
F
Clock Rise Time 20 300 ns
Clock Fall Time 20 300 ns
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
R
F
SDA Rise Time 20 300 ns
SDA Fall Time 20 300 ns
Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
Clock Low to Next Data Valid (Access Time) 200 900 ns
Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start
Condition
1300 ns
Write Time 10 ms
15/21
M24164
Figure 12. AC Waveforms
SCL
SDA In
SCL
SDA In
SCL
tCHCL
tDLCL
tCHDX
START
Condition
tCHDH
STOP
Condition
tCLQV tCLQX
SDA
Input
tCLCH
SDA
Change
tW
Write Cycle
tDXCXtCLDX
tCHDH tDHDL
tCHDX
START
Condition
STOP
Condition
START
Condition
SDA Out
Data Valid
AI00795C
16/21
PACKAGE MECHANICAL
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
M24164
b2
A2
A1AL
be
D
8
E1
1
Notes: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
E
c
eA
eB
PDIP-B
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1 .52 1.14 1 .78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
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M24164
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45˚
A
B
e
D
N
1
SO-a
Note: Drawing is not to scale.
CP
E
H
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
Symb.
Typ. Min. Max. Typ. Min. Max.
mm inches
C
LA1 α
18/21
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α
0° 8° 0° 8°
N8 8
CP 0.10 0.004
PART NUMBERING
Table 13. Ordering Information Scheme
Example: M24164 –WMN1T
Device Type
2
M24 = I
Device Function
164 = 16 Kbit (2048 x 8)
Operating Voltage
blank = V
W = V
Package
BN = PDIP8 (0.25 mm frame)
MN = SO8 (150 mil width)
Temperature Range
1 = 0 to 70 °C
C serial access EEPROM
= 4.5 to 5.5V
CC
= 2.5 to 5.5V
CC
M24164
Option
T = Tape & Reel Packing
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales O ffice.
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M24164
REVISION HIST ORY
Table 14. Document Revision History
Date Rev. Description of Revision
Jan-1999 1.0 Document written
23-Oct-2001 2.0
Document reformatted.
-R voltage range taken out
20/21
M24164
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ght s of STMi croelectr oni cs. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroe l ectronics.
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All other names are the propert y of their resp ective owne rs
© 2001 STMicroelectronics - All Rights Reserved
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