ST M24164 User Manual

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with 1 Inverting and 2 Non-Inverting Chip Enable Lines

M24164

16 Kbit Serial I²C Bus EEPROM

FEATURES SUMMARY

■ Two Wire I

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24164
– 2.5V to 5.5V for M24164-W

■ Write Control Input

■ BYTE and PAGE WRITE (up to 16 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim e d P rogramming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 1 Million Erase/Write Cycles

■ More than 40 Year Data Retention

2

C Serial Interface

Figure 1. Packages

8

1

PDIP8 (BN)

0.25 mm frame

8

1

SO8 (MN)

150 mil width

1/21October 2001

M24164

SUMMARY DESCRIPTION

The M24164 is a 16 Kbit (2048 x 8) electrically
erasable programmable memory (EEPROM ) ac­cessed by an I

Figure 2. Logic Diagram

2

C-compatible bus .

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of t he data b yte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.

V

CC

3

E0-E2 SDA

SCL

WC

M24164

V

SS

Table 1. Signal Names

E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V

CC

V

SS

Write Control
Supply Voltage
Ground

AI02264

Figure 3. DIP Connections

M24164

1

E0 V

2
3

E2

4

SS

AI02265B

Figure 4. SO Connection s

M24164

E0 V

E2

SS

1
2
3
4

AI02266B

8

CC

7

WCE1

6

SCL

5

SDAV

8

CC

7

WCE1

6

SCL

5

SDAV

These devices are com pat ible with a two-wire se­rial interface that uses a bi-directional data bus
and serial clock. By setting the three chip enables
(E0, E1
vices can be attached to the s ame I

, E2) appropriately, up to eigh t 16 K bit de-

2

C bus, and

selected individually.
These devices behave as sla ve devices, with all

memory operations synchronized by the serial
clock. Read and Write operations are initiated by a
Start condition, generated by the bus master. The
Start condition is followed by a Device Select
Code and RW

bit (as described in Table 2), termi-

nated by an acknowledge bit.
When writing data to the memory, the device in-

serts an acknowledge bit during the 9

2/21

th

bit time,

Power On Reset: V

Lock-Out Write Protect

CC

In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V

has reached the POR

CC

threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V

drops from the operating

CC

voltage, below the POR threshold value, all oper­ations are disabled and the device will not respond
to any command. A stable and valid V

must be

CC

applied before applying any logic signal.

SIGNAL DESCRIPTION
Serial Clock (SCL)

This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con­nected from Serial Clock (SCL) to V

. (Figure 4

CC

indicates how the value of the pull-up resist or can
be calculated). In most applications, thoug h, this
method of synchronization is no t employed, and
so the pull-up resistor is not necessary, provided
that the bus maste r has a push-pull (rather than
open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V

CC

. (Fig-

M24164

ure 4 indicates how the value of the pull-up resistor
can be calculated).

Chip Enable (E0, E1

These input signals are used to set the value that
is to be looked for on three bits (b6, b5, b4) of the
7-bit Device Select Code. These inputs must be
tied to V

or VSS, to establish the Device Select

CC

Code.

Write Control (WC

This input signal is useful for protecting the entire
contents of the memory from inadvertent write op­erations. Write operations are disabled to the en­tire memory array when Write Control (WC
driven High. When unconnected, the signal is in­ternally read as V
lowed.

When Write Control (WC
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.

, E2)

)

, and Write operations are al-

IL

) is driven High, Device

) is

Figure 5. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

Value versus Bus Capacitance (C

L

fc = 100kHz

fc = 400kHz

100

C

(pF)

BUS

) for an I2C Bus

BUS

MASTER

V

CC

R

SDA

SCL

R

C

BUS

L

C

BUS

AI01665

L

3/21

M24164

DEVICE OPERATION

2

The device supports the I

C proto col. This is su m ­marized in Figure 2. Any device that sends data on
to the bus is defined to be a transmitter, a nd any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, w h ic h will als o provid e t h e s e r i a l c lo c k f or
synchronization. The M24164 d evice is always a
slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The devi ce continuously
monitors (except duri ng a Write cycle ) Se ri a l Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is give n.

Stop Condition

Stop is identified by a rising edg e of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv­en High. A Stop condition terminates communica­tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condi tion to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE­PROM Wr ite cyc le.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success­ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the

th

clock pulse period, the receiver pulls Serial

9
Data (SDA) Low to acknowledge the receipt of the
eight data bits.

Data Input

During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change

only

when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication betwee n the bus master
and the slave device, the bus mas ter mus t initiate
a Start condition. Following this, t he bus master
sends eight bits, on Serial Data (SDA), most signif­icant bit first. These consist of the 7-bit Device Se­lect Code, and the Read/Write

bit (RW), as shown
in Table 2. This last bi t is set to 1 for Read, and 0
for Write operations.

The Device Select Code contains the three most
significant bits of the address within the memory

(A10, A9, A8), and a 3-bit Chip Ena ble “Add ress”
(E2, E1, E0).

When the Device Select Code is received on Seri­al Data (SDA), the device only responds if the Chip
Enable Address is the same as the value on the
Chip Enable (E0, E2, and the inverse of E1

) in­puts. Up to eight devices can be connected on the
same bus, giving a total memory capacity of
128 K bi ts, 16 KBytes.

If a match occurs on the Device Select code , the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9

th

bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand­by mode.

Table 2. Device Select Code

Device

Type

Identifier

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 E2 E1 E 0 A10 A9 A8 RW

Note: 1. The most si gnifican t bit, b7, is se nt first.

4/21

1

Chip Enable Address Most Significant Address Bits RW

Figure 6. I2C Bus Protocol

SCL

SDA

M24164

SCL

SDA

SCL

SDA

START

Condition

START

Condition

1 23 789

MSB

1 23 789

MSB ACK

SDA

Input

SDA

Change

STOP

Condition

ACK

STOP

Condition

AI00792B

Table 3. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

0X

Random Address Read

1 X reSTART, Device Select, RW
Sequential Read 1 X
Byte Write 0 V
Page Write 0 V

Note: 1. X = V

IH

or V

.

IL

WC

1

Bytes Initial Sequence

START, Device Select, RW

1

1 Similar to Current or Random Address Read

≥

IL

IL

1 START, Device Select, RW = 0

16 START, Device Select, RW

≤

= 1
= 0, Address

= 1

= 0

5/21

M24164

Figure 7. Wri te M ode Sequences with WC=1 (data wri te inhib ite d)

WC

ACK ACK NO ACK

Byte Write DEV SEL BYTE ADDR DATA IN

R/W

START

WC

ACK ACK NO ACK NO ACK

Page Write DEV SEL BYTE ADDR

R/W

START

WC (cont'd)

NO ACK NO ACK

Page Write
(cont'd)

DATA IN N

STOP

STOP

DATA IN 1 DATA IN 2

DATA IN 3

AI02803C

Write Operations

Following a Start condition the bus master sends
a Device Select Code with the RW

bit rese t to 0 .
The device acknowledges this, as shown in Figure
8, and waits for an address byte. The de vice re­sponds to the address byte with an acknowle dge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if Write
Control (WC
with Write Control (WC

) is driven High. Any Write instruction

) driven High (during a pe­riod of time from the Start condition until the end of
the address byte) will not modify the memory con­tents, and the accompanying d ata bytes are

not

acknowledged, as shown in Figure 7.
When the bus mast er generates a Stop con dition

immediately after the Ack bi t (in t he “10

th

bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.

6/21

A Stop condition at any other time slot does not
trigger the internal Write cycle.

During the internal Write cycle, Serial Da ta (SDA)
is disabled internally, and the devi ce does not re­spond to any requests.

Byte Write

After the Device Select code and the address byte,
the bus master sends one data byte. If the ad­dressed location is Write-protected, by Write Con­trol (WC

) being driven High, the device replies with
NoAck, and the location is not modified. If, instead,
the addressed location is not Write-protected, the
device replies with Ack. The bus master termi­nates the transfer by generating a Stop condit ion,
as shown in Figure 8.

Page Write

The Page Write mode allows u p to 16 by tes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:

M24164

that is, the most significant m emory address bits
are the same. If more bytes are sent than will fit up

to the end of the row, a condition known as ‘roll­over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.

The bus master sends fr om 1 to 16 bytes of data,
each of which is acknowledged by the device if

Figure 8. Wri te Mo de S e qu e nces with WC

WC

BYTE WRITE DEV SEL BYTE ADDR DATA IN

R/W

START

WC

=0 (data write enabled)

ACK

ACK ACK ACK ACK

Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca­tion are not modified, and each dat a byte is fol­lowed by a NoAck. After each byt e is transferred,
the internal byte address counte r (the 4 least s ig­nificant address bits only) is incremented. The
transfer is terminated by the bus master generat­ing a Stop condition.

ACK ACK

STOP

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

R/W

START

WC (cont'd)

ACKACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

DATA IN 3

AI02804

7/21