ST M24128-BW, M24128-BR, M24256-BW, M24256-BR User Manual
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M24128-BW, M24128-BR
M24256-BW, M24256-BR
256Kbit and 128Kbit Serial I²C Bus EEPROM
With Three Chip Enable Lines
FEATURES SUMMARY
■ Compatible with I
■ Two-Wire I
Supports 400kHz Protocol
■ Single Supply Voltage:
– 2.5 to 5.5V for M24128-BW, M24256-BW
– 1.8 to 5.5V for M24128-BR, M24256-BR
■ Hardware Write Control
■ BYTE and PAGE WRITE (up to 64 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incr em ent ing
■ Enhanced ESD/Latch-Up Protection
■ More than 1 Million Erase/Write Cycles
■ More than 40-Year Data Retention
Table 1. Product List
Reference Part Number
128 Kbits
256 Kbits
2
2
C Extended Addressing
C Serial Interface
M24128-BW
M24128-BR
M24256-BW
M24256-BR
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
TSSOP8 (DW)
169 mil width
1/25June 2005
M24128-BW, M24128-BR, M24256-BW, M24256-BR
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Operating Conditions (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Operating Conditions (M24128-BR, M24256-BR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. DC Characteristics (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. DC Characteristics (M24128-BR, M24256-BR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. AC Characteristics ( M24128-BW, M24256-BW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. AC Characteristics (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 19
Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 19
Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 20
Table 17. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
20
Figure 14.SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline. . . . . . 21
Table 18. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
21
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 22
Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32K x 8 bits (M24256-BW and M24256BR) and 16K x 8 bits (M24128-BW and M24128BR).
Figure 2. Logic Diagram
V
CC
3
E0-E2
SCL
WC
M24256-B
M24128-B
V
SS
Table 2. Signal Names
SDA
AI02809
ter. The Start condition is followed by a Device
Select Code and Read/Write
bit (RW) (as described in Table 3.), terminated by an acknowledge bit.
When writing data to the memory , the device inserts an acknowled ge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledge s the rec eipt o f the d ata byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset
In order to prevent inadvertent Write operations
during Power Up, a Power On Reset (POR) circ uit
is implemented.
At Power Up, the device will not respond to any instruction until V
voltage (this thresho ld i s lo wer tha n th e V
has reached the POR threshold
CC
CC
minimum operating voltage defined in Table 8. and Ta-
ble 9.). In the same wa y, as soon as V
CC
drops
from the normal operating voltage, below the POR
threshold voltage, all th e operations are disabled
and the device will not respond to any instruction.
Prior to selecting and issuing instructions to the
memory, a valid and s table V
voltage must be
CC
applied. This voltage must remain stable and valid
until the end of the transmissi on of the instruc tion
and, for a Write instruction, until the completion of
the internal write cycle (t
).
W
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V
CC
V
SS
2
C uses a two-wire serial interf ace, comprisi ng a
I
Write Control
Supply Voltage
Ground
bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
The device behaves as a slave in the I
2
C bus definition.
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiated by a Start condition, generated by the bus mas-
Figure 3. DIP, SO and TSSOP Connections
M24256-B
M24128-B
E0 V
1
2
E2
3
4
SS
Note: See PACKAGE MECHA NICAL section for package dimen-
sions, and how to identify pin-1.
8
7
6
5
AI02810B
CC
WCE1
SCL
SDAV
4/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applications where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to V
value of the pull- up resi stor can be calc ulate d). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, pro vided that the bus maste r
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or ope n collector signals on the
bus. A pull up resistor must be connected from Serial Data (SDA) to V
the value of the pull-up resistor can be calculated).
. (Figure 4. indicates how the
CC
. (Figure 4. indicates how
CC
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7bit Device Select Code. These inputs must be tied
to V
or VSS, to establish the Device Select
CC
Code. When not connected (left floating), these inputs are read as Low (0,0,0).
Write Control (WC
). This input signal is useful
for protecting the entire content s of the memory
from inadvertent write operations. Write operations are disabled to the entire memory array when
Write Control (WC
nected, the signal is internally read as V
) is driven High. When uncon-
, and
IL
Write operations are allowed.
When Write Contr ol (WC
) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 4. Maximum R
20
16
12
8
Maximum RP value (kΩ)
4
0
10
Value versus Bus Parasitic Capacitance (C) for an I2C Bus
P
V
CC
SDA
fc = 400kHz
100
C (pF)
fc = 100kHz
MASTER
1000
SCL
R
R
P
P
C
C
AI01665b
5/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 5. I2C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 7 89
MSB
1 23 7 89
MSB
SDA
Input
SDA
Change
STOP
Condition
ACK
ACK
STOP
Condition
AI00792B
Table 3. Device Select Code
Device Type Identifier
1
Chip Enable Address
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code1010E2E1E0RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective ex ternal pins on the memory device.
2
RW
Table 4. Most Significant Byte Table 5. Least Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
6/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DEVICE OPERATION
The device supports the I2C protocol. This is summarized in Figure 5.. Any device that sends d ata
on to the bus is defined to be a transmitter, and
any device that reads the data to be a rec eiver.
The device that controls the data transfer is known
as the bus master, an d th e other a s the s lave device. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24xxx-B device is always a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command . The device continuou sly
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Cloc k (S CL) is s tab le a nd d ri ven High. A Stop condition t ermi nate s co mm uni ca tion between the device and the bus master. A
Read command that is follow ed by NoA ck can be
followed by a Sto p condition to force the device
into the Stand-by mode. A S top condition at the
end of a Write comm and trig gers the i nternal EE PROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be
bus master or sl ave device, releas es Serial Data
(SDA) after sending ei ght bits of da ta. During the
th
9
clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change
only
when Serial Cl ock ( SCL ) i s dr iv-
en Low.
Memory Addressing
To start communica tion between the bus master
and the slave device, the b us mas ter m u st ini ti ate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I
2
C bus. Each one is gi ven a un ique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the device only respond s if the Chip Enabl e Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.
th
The 8
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) du ring the 9
th
bit time. If the
device does not match the Devic e Select code, it
deselects itself from the bus, and goes into Standby mode.
Table 6. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
Random Address Read
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0
Page Write 0
Note: 1. X = V
IH
or V
.
IL
0X
1 X reSTART, Device Select, RW
WC
V
V
1
IL
IL
Bytes Initial Sequence
= 1
1
START, Device Select, RW
1 START, Device Select, RW = 0
≤ 64 START, Device Select, RW = 0
= 0, Address
= 1
7/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK ACK ACK NO ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
R/W
START
WC
ACK ACK ACK NO ACK
PAGE WRITE DEV SEL BYTE ADDR
R/W
START
WC (cont'd)
NO ACK NO ACK
PAGE WRITE
(cont'd)
DATA IN N
STOP
BYTE ADDR DATA IN 1
STOP
DATA IN 2
AI01120C
Write Operations
Following a Start co ndition the bus mas ter sends
a Device Select Code with the R/W
bit (RW) reset
to 0. The device ack nowledges this , as shown in
Figure 7., and waits for two address bytes. The de-
vice responds to each address byte with an acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC
with Write Control (WC
) is driven Hi gh. Any W rite instruction
) driven High (duri ng a pe riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not
acknowledged, as shown in Figure 6..
Each data byte in the memory ha s a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4.) is sent first, foll owed by the Least Signifi-
cant Byte (Table 5.). Bits b15 to b0 form the
address of the byte in memory.
8/25
When the bus master gener ates a Stop conditi on
immediately after t he Ac k bi t (i n th e “1 0
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any othe r time slot does not
trigger the internal Write cycle.
After the Stop condition, the delay t
, and the suc-
W
cessful completion of a Write operation, the device’s internal address counter is incremented
automatically, to point to the next byte address after the last one that was modified.
During the internal Write cycl e, Serial Data (SDA)
is disabled intern ally, a nd the devic e does n ot respond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus mas ter sends one d ata byte. If the
addressed location is Write-protected, by Write
Control (WC
) being driven High, the device replies
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