ST M24128-BW, M24128-BR, M24256-BW, M24256-BR User Manual

M24128-BRBN6

M24128-BW, M24128-BR

M24256-BW, M24256-BR

256Kbit and 128Kbit Serial I²C Bus EEPROM With Three Chip Enable Lines

FEATURES SUMMARY

Compatible with I2C Extended Addressing

Two-Wire I2C Serial Interface Supports 400kHz Protocol

Single Supply Voltage:

2.5 to 5.5V for M24128-BW, M24256-BW

1.8 to 5.5V for M24128-BR, M24256-BR

Hardware Write Control

BYTE and PAGE WRITE (up to 64 Bytes)

RANDOM and SEQUENTIAL READ Modes

Self-Timed Programming Cycle

Automatic Address Incrementing

Enhanced ESD/Latch-Up Protection

More than 1 Million Erase/Write Cycles

More than 40-Year Data Retention

Table 1. Product List

Reference

Part Number

M24128-BW

128 Kbits

M24128-BR

M24256-BW

256 Kbits

M24256-BR

Figure 1. Packages

8

1

PDIP8 (BN)

8

1

SO8 (MN) 150 mil width

8

1

SO8 (MW) 200 mil width

TSSOP8 (DW) 169 mil width

June 2005

1/25

M24128-BW, M24128-BR, M24256-BW, M24256-BR

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . 5 Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2/25

M24128-BW, M24128-BR, M24256-BW, M24256-BR

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. Operating Conditions (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Operating Conditions (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 11. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 12. DC Characteristics (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13. DC Characteristics (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 14. AC Characteristics ( M24128-BW, M24256-BW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 15. AC Characteristics (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 19 Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 19 Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 20 Table 17. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 20

Figure 14.SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline . . . . . . 21 Table 18. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data 21

Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 22 Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 22

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3/25

M24128-BW, M24128-BR, M24256-BW, M24256-BR

SUMMARY DESCRIPTION

These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32K x 8 bits (M24256-BW and M24256BR) and 16K x 8 bits (M24128-BW and M24128BR).

Figure 2. Logic Diagram

VCC

3

E0-E2

SDA

 

M24256-B

SCL M24128-B

WC

VSS

AI02809

Table 2. Signal Names

 

E0, E1, E2

Chip Enable

 

 

 

 

SDA

Serial Data

 

 

 

 

SCL

Serial Clock

 

 

 

 

 

 

Write Control

 

WC

 

 

 

 

 

VCC

Supply Voltage

 

VSS

Ground

I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus mas-

4/25

ter. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as described in Table 3.), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Power On Reset

In order to prevent inadvertent Write operations during Power Up, a Power On Reset (POR) circuit is implemented.

At Power Up, the device will not respond to any instruction until VCC has reached the POR threshold voltage (this threshold is lower than the VCC minimum operating voltage defined in Table 8. and Table 9.). In the same way, as soon as VCC drops from the normal operating voltage, below the POR threshold voltage, all the operations are disabled and the device will not respond to any instruction.

Prior to selecting and issuing instructions to the memory, a valid and stable VCC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).

Figure 3. DIP, SO and TSSOP Connections

M24256-B

M24128-B

E0

1

8

VCC

E1

2

7

WC

 

E2

3

6

SCL

VSS

4

5

SDA

 

 

AI02810B

 

 

Note: See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.

ST M24128-BW, M24128-BR, M24256-BW, M24256-BR User Manual

M24128-BW, M24128-BR, M24256-BW, M24256-BR

SIGNAL DESCRIPTION

Serial Clock (SCL). This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

Serial Data (SDA). This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4. indicates how the value of the pull-up resistor can be calculated).

Chip Enable (E0, E1, E2). These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7- bit Device Select Code. These inputs must be tied to VCC or VSS, to establish the Device Select Code. When not connected (left floating), these inputs are read as Low (0,0,0).

Write Control (WC). This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed.

When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.

Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus

Maximum RP value (kΩ)

20

16

12

8

4

0

10

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RP

 

 

RP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MASTER

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fc = 100kHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fc = 400kHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

100

 

 

1000

 

 

 

 

 

 

 

 

 

 

 

C (pF)

AI01665b

5/25

M24128-BW, M24128-BR, M24256-BW, M24256-BR

Figure 5. I2C Bus Protocol

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

START

 

 

 

SDA

 

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

STOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Condition

 

 

 

 

 

 

 

 

 

 

 

Condition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL

 

 

 

 

1

 

2

 

3

 

 

 

 

 

 

 

7

8

 

9

 

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACK

 

 

 

 

 

 

 

 

 

 

 

 

 

START

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Condition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL

 

 

 

 

1

 

 

2

 

 

3

 

 

 

 

 

 

 

 

7

8

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Condition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AI00792B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3. Device Select Code

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device Type Identifier1

 

 

 

 

 

 

 

 

Chip Enable Address2

 

 

RW

 

 

 

 

 

 

b7

b6

 

 

 

b5

 

 

b4

 

 

 

b3

b2

 

 

 

b1

 

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device Select Code

1

 

 

 

0

 

 

1

 

 

 

 

0

 

 

 

E2

 

 

E1

 

 

 

E0

 

 

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: 1. The most significant bit, b7, is sent first.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

 

 

 

 

 

 

 

 

 

 

 

 

Table 4. Most Significant Byte

 

 

 

 

 

 

 

 

 

 

 

Table 5. Least Significant Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b15

 

b14

 

b13

 

b12

 

b11

 

b10

b9

 

b8

 

 

 

 

 

b7

 

 

b6

 

b5

 

b4

b3

 

b2

 

b1

 

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6/25

M24128-BW, M24128-BR, M24256-BW, M24256-BR

DEVICE OPERATION

The device supports the I2C protocol. This is summarized in Figure 5.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24xxx-B device is always a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial

Table 6. Operating Modes

Data (SDA) Low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.

Memory Addressing

To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3. (on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4- bit Device Type Identifier is 1010b.

Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode

RW bit

 

WC 1

Bytes

Initial Sequence

Current Address Read

1

 

X

1

 

 

 

= 1

 

START, Device Select, RW

 

 

 

 

 

 

 

 

 

 

 

 

0

 

X

 

 

 

 

 

= 0, Address

Random Address Read

 

1

START, Device Select, RW

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

X

 

 

 

 

 

 

 

 

 

reSTART, Device Select, RW

= 1

 

 

 

 

 

 

 

 

Sequential Read

1

 

X

1

Similar to Current or Random Address Read

 

 

 

 

 

 

 

 

Byte Write

0

 

VIL

1

 

 

 

 

= 0

 

START, Device Select, RW

 

 

 

 

 

 

 

 

Page Write

0

 

VIL

64

 

 

 

 

= 0

 

START, Device Select, RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: 1. X = VIH or VIL.

7/25

M24128-BW, M24128-BR, M24256-BW, M24256-BR

Figure 6. Write Mode Sequences with WC=1 (data write inhibited)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACK

ACK

ACK

NO ACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BYTE WRITE

DEV SEL

 

 

BYTE ADDR BYTE ADDR

 

 

DATA IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

START

WC

R/W

STOP

 

 

ACK

ACK

ACK

NO ACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PAGE WRITE

DEV SEL

 

 

BYTE ADDR

 

BYTE ADDR

 

 

DATA IN 1

 

 

 

 

DATA IN 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

START

WC (cont'd)

PAGE WRITE (cont'd)

R/W

NO ACK

NO ACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA IN N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STOP

AI01120C

Write Operations

Following a Start condition the bus master sends a Device Select Code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7., and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 6..

Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4.) is sent first, followed by the Least Significant Byte (Table 5.). Bits b15 to b0 form the address of the byte in memory.

When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.

After the Stop condition, the delay tW, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.

Byte Write

After the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies

8/25

Loading...
+ 17 hidden pages