Datasheet M24256-B, M24128-B Datasheet (ST)

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M24256-B M24128-B

256Kbit and 128Kbit Serial I²C Bus EEPROM

With Three Chip En able Lines

FEATURES SUMMARY

■ Compat ib le with I

■ Two Wire I

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24xxx-B – 2.5V to 3.6V for M24xxx-BV – 2.5V to 5.5V for M24xxx-BW – 1.8V to 5.5V for M24xxx-BR – 1.8V to 3.6V for M24xxx-BS

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 64 Byte s)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Timed Progr a m ming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behav ior

■ More than 100,000 Erase/Write Cycles

– More than 1 Million Erase/Write cycles for the

products specified in Table 22

■ More than 40 Year Data Retention

C Extended Addressing

C Serial Interface

Figure 1. Packages

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

1/25November 2002

M24256-B, M24128-B

SUMMARY DESCRIPTION

These I

C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32K x 8 bits (M24256-B) and 16K x 8 bits (M24128-B).

Figure 2. Logi c Diagram

E0-E2

SCL

M24256-B M24128-B

SDA

AI02809

Table 1. Signal Names

E0, E1, E2 Chip Enable SDA Serial Data SCL Serial Clock

following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until V

has reached the POR thresh-

old value, and all operations are disabled – the device will not respond to any command. In the same way, when V

drops from the operating voltage,

below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V

must be applied

before applying any logic signal. When the power supply is turned on, V

from V

to VCC(min), passing through a value V

rises

in between. The -V and -S versions of the dev i ce, the M24xxx-BV and M24xxx-BS, i gnore all instructions until a time delay of t moment that V

rises above the Vth threshold.

has elapsed after the

However, the correct operation of the device is not guaranteed if, by this time, V V

(min). No instructions should be s ent until the

is still below

later of:

afte r VCC passed the Vth threshold

–t

passed the VCC(min) lev e l

–V

These values are specified in Table 14.

WC V

These devices are compatible with the I

Write Control Supply Voltage Ground

C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I

C bus defini-

tion. The device behaves as a slave in the I

C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW

bit (as described in Table 2),

terminated by an acknowledge bit. When writing data to the memory, the device in-

serts an acknowledge bit during the 9

2/25

bit time,

Figure 3. DIP, SO and TSSOP Connections

M24256-B M24128-B

E0 V

2 3

Note: 1. See page 19 (onwards) for package dimensions, and how

to identify pin-1.

8 7 6 5

AI02810B

WCE1 SCL SDAV

SIGNAL DESCRIPTION Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V

. (Figure 4

indicates how the value of the pull-up resistor c an be calculated). In most applications, thoug h, this method of synchronization is no t employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other op en drai n or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V

. (Figure 4 indicates how the value of the pull-up resistor can be calculated).

M24256-B, M24128-B

Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V Device Select Code.

Write Control (WC

This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC driven High. When unconnected, the signal is internally read as V

lowed. When Write Control (WC

Select and Address bytes are acknowledged, Data bytes are not acknowledged.

or VSS, to establish the

)

) is

, and Write operations are al-

) is driven High, Device

Figure 4. Maximum R

Maximum RP value (kΩ)

10 1000

Value versus Bus Capacitance (C

fc = 100kHz

fc = 400kHz

100

(pF)

BUS

) for an I2C Bus

BUS

MASTER

SDA

SCL

BUS

AI01665

3/25

M24256-B, M24128-B

Figure 5. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

Condition

START

Condition

1 23 789

MSB

1 23 789

MSB ACK

SDA

Input

SDA

Change

STOP

Condition

ACK

STOP

Condition

AI00792B

Table 2. Device Select Code

Device Type Identifier

Chip Enable Address

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E0 RW

Note: 1. The most significant bit, b7, is sent first.

2. E0 , E 1 and E2 are comp ared against the respective ext ernal pins on the memory device.

Table 3. Most Significant Byte Table 4. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

4/25

M24256-B, M24128-B

DEVICE OPERATION

The device supports the I

C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, a nd any device that reads the data to be a receiver. The device that controls the data transfer is kn own as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, w h ic h will also provide t he s er ial clock for synchronization. The M24xxx-B d evice i s a lways a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The devi ce continuously monitors (except duri ng a Write cycle ) Se rial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is give n.

Stop Condition

Stop is identified by a rising edg e of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Wr ite cycle .

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the

clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal

only

must change

when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication betwee n the bus master and the slave device, the bus mas ter mus t initiate a Start condition. Following this, the bu s master sends the Device Select Code, shown in Tabl e 2 (on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b.

Up to eight memory devices can be connected on a single I

C bus. Each one is given a uniq ue 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs.

The 8

bit is the Read/Write bit (RW). This bit is

set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment on Serial Data (SDA) during the 9

bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.

Table 5. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

Random Address Read

Sequential Read 1 X Byte Write 0 V Page Write 0 V

Note: 1. X = V

or V

0X 1 X reSTART, Device Select, RW

Bytes Initial Sequence

1 Similar to Current or Random Address Read

≥

1 START, Device Select, RW = 0

64 START, Device Select, RW

≤

START, Device Select, RW

= 1 = 0, Address

= 1

= 0

5/25

M24256-B, M24128-B

Figure 6. Wri te Mo de S e qu e nces with WC=1 (data wri te inhibi ted)

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

NO ACK NO ACK

PAGE WRITE (cont'd)

DATA IN N

STOP

slot), either at the end of a Byte Write or a Page

Write Operations

Following a Start condition the bus mast er sends a Device Select Code with the RW

bit rese t to 0 . The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if Write Control (WC with Write Control (WC

) is driven High. Any Write instruction

) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are

not

acknowledged, as shown in Figure 6.

Each data byte in the m emory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 3) is sent first, followed by t he Least Significant Byte (Table 4). Bits b15 to b0 form t he add ress of the byte in memory.

When the bus mast er generate s a Stop con dition immediately after the Ack bi t (in t he “10

bit” time

Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the devi ce does not respond to any requests.

Byte Write

After the Device Select code and the address bytes, the bus master sends one dat a byte. If the addressed location is Write-protected, by Write Control (WC with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus ma ster terminates the transfer by generating a S top condition, as shown in Figure 7.

Page Write

The Page Write mode allows u p to 64 by tes to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant m emory address bits

STOP

DATA IN 2

AI01120C

) being driven High, the device replies

6/25

M24256-B, M24128-B

(b14-b6 for M24256-B, and b13-b6 for M24128-B) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘rollover’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way.

The bus master sends fr om 1 to 64 bytes of data, each of which is acknowledged by the device if

Figure 7. Wri te Mo de S e qu e nces with W

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

C=0 (data write enabled)

ACK

R/W

ACK ACK ACK ACK

Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each dat a byte is followed by a NoAck. After each by te is transferred, the internal byte address counte r (the 6 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.

ACK ACK ACK

STOP

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

ACKACK

PAGE WRITE (cont'd)

DATA IN N

STOP

DATA IN 2

AI01106C

7/25

M24256-B, M24128-B

Figure 8. Wri te Cy cle Pol l in g Fl owchart usin g AC K

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

First byte of instruction with RW = 0 already decoded by the device

ReSTART

STOP

YES

Operation is

Addressing the

Memory

DATA for the

WRITE Operation

Continue the

WRITE Operation

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t

) is shown in Tables

20 and 21, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.

The sequence, as shown in Figure 8, is: – Initial condition: a Write cycle is in progress.

YESNO

Send Address

and Receive ACK

START

Condition

YESNO

DEVICE SELECT

with RW = 1

Continue the

Random READ Operation

AI01847C

– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first byte of the new instruction).

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).

8/25

Figure 9. Read Mode Sequences

M24256-B, M24128-B

CURRENT ADDRESS READ

RANDOM ADDRESS READ

SEQUENTIAL CURRENT READ

SEQUENTIAL RANDOM READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK ACK

DEV SEL * BYTE ADDR BYTE ADDR

NO ACK

STOP

ACK ACK ACK

DEV SEL * DATA OUT

R/W

START

DATA OUT N

STOP

ACK ACK

DEV SEL * DATA OUT 1

NO ACK

STOP

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note: 1. The sev en m ost signific ant bits of the D evice Select Code of a Rando m Read (in the 1st and 4th bytes) must be ide n tical .

START

R/W

AI01105C

Current Address Read

Read Operations

Read operations are performed independently of the state of the Write Control (WC

) signal.

Random Address Read

A dummy Write is performed to load the address into the address counter (as shown in Figure 9) but

without

sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with t he RW

bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must

not

acknowledge the byte, and terminates

the transfer with a Stop condition.

The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW

bit set to 1. The device acknowledges this, an d outputs the byt e address ed by the internal address counter. The counter is then incremented. The bus master term inates t he transfer with a Stop condition, as shown i n Figure 9,

without

acknowledging the byte.

Sequenti a l Read

This operation can be used after a Current Address Read or a Random Address Read. The bus

9/25

M24256-B, M24128-B

master

does

acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must

not

acknowledge the last byte, and

must

generate a Stop condition, as shown in Figure 9. The output data comes from consecutive address-

es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after each byte read, for an acknowledgment during the

bit time. If the bus master does not drive Serial

9 Data (SDA) Low during this time, the device terminates the data transfer and s witches to its St andby mode.

10/25

M24256-B, M24128-B

MAXI MUM RATIN G

Stressing the device above the rating listed in t he Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at t hese or any other conditions ab ove those i ndicated in t he Operating sections of this specificat ion is not im-

Table 6. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit

STG

LEAD

Storage Temperature –65 150 °C

Lead Temperature during Soldering

PDIP: 10 seconds SO: 20 seconds (max) TSSOP: 20 seconds (max)

plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

260 235 235

°C

ESD Electrostatic Discharge Voltage (Human Body model)

Note: 1. IPC/JEDEC J-STD-020A

2. JEDEC Std JE SD22-A114A (C1=100 pF, R1=15 00

Input or Output range

Supply Voltage

-V voltage range all other voltage ranges

Ω, R2=500 Ω)

–0.6 –0.6

–0.3 –0.3

4.2

6.5

4.2

6.5

–3000 3000 V

11/25

M24256-B, M24128-B

DC AND AC PARAMETERS

This section summarizes the operat ing and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure-

Table 7. Operating Conditions (M24xxx-B)

Symbol Parameter Min. Max. Unit

ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit matc h the measurem ent conditions when relying on the quoted parameters.

Supply Voltage 4.5 5.5 V Ambient Operating Temperature –40 8 5 °C

Table 8. Operating Conditions (M24xxx-BV)