64 Kbit EEPROM tag IC at 13.56 MHz with 64-bit UID and
password based on ISO/IEC 15693 and ISO/IEC 18000-3 Mode 1
Features
■ Based on ISO/IEC 15693 and
ISO/IEC 18000-3 mode 1 standards
■ 13.56 MHz ±7 kHz carrier frequency
■ To tag: 10% or 100% ASK modulation using
1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse
position coding
■ From tag: load modulation using Manchester
coding with 423 kHz and 484 kHz subcarriers
in low (6.6 Kbit/s) or high (26 Kbit/s) data rate
mode. Supports the 53 Kbit/s data rate with
Fast commands
■ Internal tuning capacitor (27.5 pF)
■ More than 1 million write cycles
■ More than 40-year data retention
■ 64 Kbit EEPROM organized into 2048 blocks of
32 bits
■ 64-bit unique identifier (UID)
■ Multipassword protection
■ Read Block & Write (32-bit blocks)
■ Write time: 5.75 ms including the internal verify
The LRIS64K is a contactless memory powered by the received carrier electromagnetic
wave, which follows the ISO/IEC 15693 and ISO/IEC 18000-3 mode 1 recommendation for
radio-frequency power and signal interface. It is a 64 Kbit electrically erasable
programmable memory (EEPROM). The memory is organized as 64 sectors divided into 32
blocks of 32 bits.
The LRIS64K is accessed via the 13.56 MHz carrier electromagnetic wave, on which
incoming data are demodulated from the received signal amplitude modulation (ASK:
amplitude shift keying). The received ASK wave is 10% or 100% modulated with a data rate
of 1.6 Kbit/s using the 1/256 pulse coding mode, or a data rate of 26 Kbit/s using the 1/4
pulse coding mode. Outgoing data are generated by the LRIS64K load variation using
Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data
are transferred from the LRIS64K at 6.6 Kbit/s in low data rate mode and 26 Kbit/s in high
data rate mode. The LRIS64K supports the 53 Kbit/s data rate in high data rate mode with a
single subcarrier frequency of 423 kHz.
The LRIS64K also features a unique 32-bit multi-password protection scheme.
The LRIS64K is divided into 64 sectors of 32 blocks of 32 bits as shown in Tab l e 2 . Figure 2
shows the memory sector organization. Each sector can be individually read- and/or writeprotected using a specific password command. Read and write operations are possible if
the addressed data are not in a protected sector.
The LRIS64K also has a 64-bit block that is used to store the 64-bit unique identifier (UID).
The UID is compliant with the ISO/IEC 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user and its value is
written by ST on the production line.
The LRIS64K includes an AFI register that stores the application family identifier, and a
DSFID register that stores the data storage family identifier used in the anticollision
algorithm.
The LRIS64K has three additional 32-bit blocks that store the RF password codes.
Figure 2.Memory sector organization
Sector details
The LRIS64K user memory is divided into 64 sectors. Each sector contains 1024 bits. The
protection scheme is described in Section 3: System memory area.
A sector provides 32 blocks of 32 bits. Each read and write access are done by block. Read
and write block accesses are controlled by a Sector Security Status byte that defines the
access rights to all the 32 blocks contained in the sector. If the sector is not protected, a
Write command updates the complete 32 bits of the selected block.
Doc ID 15336 Rev 1111/100
User memory organizationLRIS64K
Table 2.Sector details
Sector
number
0
RF block
address
Bits [31:24]Bits [23:16]Bits [15:8]Bits [7:0]
0useruseruseruser
1useruseruseruser
2useruseruseruser
3useruseruseruser
4useruseruseruser
5useruseruseruser
6useruseruseruser
7useruseruseruser
8useruseruseruser
9useruseruseruser
10useruseruseruser
11useruseruseruser
12useruseruseruser
13useruseruseruser
14useruseruseruser
15useruseruseruser
16useruseruseruser
17useruseruseruser
18useruseruseruser
19useruseruseruser
20useruseruseruser
21useruseruseruser
22useruseruseruser
23useruseruseruser
24useruseruseruser
25useruseruseruser
26useruseruseruser
27useruseruseruser
28useruseruseruser
29useruseruseruser
30useruseruseruser
31useruseruseruser
12/100Doc ID 15336 Rev 11
LRIS64KUser memory organization
Table 2.Sector details (continued)
Sector
number
1
..................
RF block
address
32useruseruseruser
33useruseruseruser
34useruseruseruser
35useruseruseruser
36useruseruseruser
37useruseruseruser
38useruseruseruser
39useruseruseruser
...............
2016useruseruseruser
2017useruseruseruser
2018useruseruseruser
2019useruseruseruser
2020useruseruseruser
2021useruseruseruser
2022useruseruseruser
Bits [31:24]Bits [23:16]Bits [15:8]Bits [7:0]
63
2023useruseruseruser
2024useruseruseruser
2025useruseruseruser
2026useruseruseruser
2027useruseruseruser
2028useruseruseruser
2029useruseruseruser
2030useruseruseruser
2031useruseruseruser
2032useruseruseruser
2033useruseruseruser
2034useruseruseruser
2035useruseruseruser
2036useruseruseruser
2037useruseruseruser
2038useruseruseruser
2039useruseruseruser
Doc ID 15336 Rev 1113/100
User memory organizationLRIS64K
Table 2.Sector details (continued)
Sector
number
63 continued
RF block
address
2040useruseruseruser
2041useruseruseruser
2042useruseruseruser
2043useruseruseruser
2044useruseruseruser
2045useruseruseruser
2046useruseruseruser
2047useruseruseruser
Bits [31:24]Bits [23:16]Bits [15:8]Bits [7:0]
14/100Doc ID 15336 Rev 11
LRIS64KSystem memory area
3 System memory area
3.1 LRIS64K RF block security
The LRIS64K provides a special protection mechanism based on passwords. Each memory
sector of the LRIS64K can be individually protected by one out of three available passwords,
and each sector can also have Read/Write access conditions set.
Each memory sector of the LRIS64K is assigned with a Sector security status byte including
a Sector Lock bit, two Password Control bits and two Read/Write protection bits as shown in
Ta bl e 4 . Ta b le 3 describes the organization of the Sector security status byte which can be
read using the Read Single Block and Read Multiple Block commands with the Option_flag
set to ‘1’.
On delivery, the default value of the SSS bytes is reset to 00h.
When the Sector Lock bit is set to ‘1’, for instance by issuing a Lock-sector Password
command, the 2 Read/Write protection bits (b
, b2) are used to set the Read/Write access of
1
the sector as described in Ta b l e 5 .
Table 5.Read / Write protection bit setting
Sector
Lock
, b
b
2
Sector access when password
1
presented
Sector access when password not
presented
0xxReadWriteReadWrite
100ReadWriteReadNo Write
101ReadWriteReadWrite
110ReadWriteNo ReadNo Write
111ReadNo WriteNo ReadNo Write
The next 2 bits of the Sector security status byte (b3, b4) are the Password Control bits. The
value these two bits is used to link a password to the sector as defined in Ta b le 6 .
Table 6.Password Control bits
b4, b
3
Password
00The sector is not protected by a Password
01The sector is protected by the Password 1
10The sector is protected by the Password 2
11The sector is protected by the Password 3
The LRIS64K password protection is organized around a dedicated set of commands plus a
system area of three password blocks where the password values are stored. This system
area is described in Ta b le 7 .
Table 7.Password system area
Add07 815 16232431
1Password 1
2Password 2
3Password 3
The dedicated password commands are:
●Write-sector Password
The Write-sector Password command is used to write a 32-bit block into the password
system area. This command must be used to update password values. After the write
cycle, the new password value is automatically activated. It is possible to modify a
password value after issuing a valid Present-sector Password command.
On delivery, the three default password values are set to 0000 0000h and are activated.
●Lock-sector Password
The Lock-sector Password command is used to set the Sector security status byte of
the selected sector. Bits b
16/100Doc ID 15336 Rev 11
to b1 of the Sector security status byte are affected by the
4
LRIS64KSystem memory area
Lock-sector Password command. The Sector Lock bit, b0, is set to ‘1’ automatically.
After issuing a Lock-sector Password command, the protection settings of the selected
sector are activated. The protection of a locked block cannot be changed. A Locksector Password command sent to a locked sector returns an error code.
●Present-sector Password
The Present-sector Password command is used to present one of the three passwords
to the LRIS64K in order to modify the access rights of all the memory sectors linked to
that password (Tab l e 5 ) including the password itself. If the presented password is
correct, the access rights remain activated until the tag is powered off or until a new
Present-sector Password command is issued. If the presented password value is not
correct, all the access rights of all the memory sectors are deactivated.
3.2 Example of the LRIS64K security protection
Ta bl e 8 and Ta ble 9 show the sector security protections before and after a valid Present-
sector Password command. Ta bl e 8 shows the sector access rights of an LRIS64K after
power-up. After a valid Present-sector Password command with password 1, the memory
sector access is changed as shown in Ta b le 9 .
Table 8.Sector security protection after power-up
Sector
address
0 Protection: Standard ReadNo Writexxx 00001
1 Protection: Pswd 1ReadNo Writexxx 01001
2 Protection: Pswd 1ReadWritexxx 01011
3 Protection: Pswd 1No ReadNo Writexxx 01101
4 Protection: Pswd 1No ReadNo Writexxx 01111
Table 9.Sector security protection after a valid presentation of password 1
Sector
address
0Protection: StandardReadNo Writexxx00001
1Protection: Pswd 1ReadWritexxx01001
2Protection: Pswd 1ReadWritexxx01011
3Protection: Pswd 1ReadWritexxx01101
4Protection: Pswd 1ReadNo Writexxx01111
Sector security status byte
b
7b6b5b4b3b2b1b0
Sector security status byte
b
7b6b5b4b3b2b1b0
Doc ID 15336 Rev 1117/100
Initial delivery stateLRIS64K
4 Initial delivery state
The device is delivered with the following factory settings:
●All bits in the memory array are set to 1 (each byte contains FFh).
●The default value of the SSS bytes is reset to 00h.
●The three default password values are set to 0000 0000h and are activated.
System parameters are set to:
●(E0 02 xx xx xx xx xx xx )h for UID
●(03 07 FF)h for Memory Size
●00h for AFI
●00h for DSFID
18/100Doc ID 15336 Rev 11
LRIS64KCommands
5 Commands
The LRIS64K supports the following commands:
●Inventory, used to perform the anticollision sequence.
●Stay Quiet, used to put the LRIS64K in quiet mode, where it does not respond to any
inventory command.
●Select, used to select the LRIS64K. After this command, the LRIS64K processes all
Read/Write commands with Select_flag set.
●Reset To Ready, used to put the LRIS64K in the ready state.
●Read Block, used to output the 32 bits of the selected block and its locking status.
●Write Block, used to write the 32-bit value in the selected block, provided that it is not
locked.
●Read Multiple Blocks, used to read the selected blocks and send back their value.
●Write AFI, used to write the 8-bit value in the AFI register.
●Lock AFI, used to lock the AFI register.
●Write DSFID, used to write the 8-bit value in the DSFID register.
●Lock DSFID, used to lock the DSFID register.
●Get System Info, used to provide the system information value
●Get Multiple Block Security Status, used to send the security status of the selected
block.
●Initiate, used to trigger the tag response to the Inventory Initiated sequence.
●Inventory Initiated, used to perform the anticollision sequence triggered by the Initiate
command.
●Write-sector Password, used to write the 32 bits of the selected password.
●Lock-sector Password, used to write the Sector security status bits of the selected
sector.
●Present-sector Password, enables the user to present a password to unprotect the
user blocks linked to this password.
●Fast Initiate, used to trigger the tag response to the Inventory Initiated sequence.
●Fast Inventory Initiated, used to perform the anticollision sequence triggered by the
Initiate command.
●Fast Read Single Block, used to output the 32 bits of the selected block and its
locking status.
●Fast Read Multiple Blocks, used to read the selected blocks and send back their
value.
Doc ID 15336 Rev 1119/100
CommandsLRIS64K
5.1 Initial dialogue for vicinity cards
The dialog between the vicinity coupling device (VCD) and the vicinity integrated circuit
Card or VICC (LRIS64K) takes place as follows:
●activation of the LRIS64K by the RF operating field of the VCD.
●transmission of a command by the VCD.
●transmission of a response by the LRIS64K.
These operations use the RF power transfer and communication signal interface described
below (see Power transfer, Frequency and Operating field). This technique is called RTF
(Reader Talk First).
5.1.1 Power transfer
Power is transferred to the LRIS64K by radio frequency at 13.56 MHz via coupling antennas
in the LRIS64K and the VCD. The RF operating field of the VCD is transformed on the
LRIS64K antenna to an AC Voltage which is rectified, filtered and internally regulated. The
amplitude modulation (ASK) on this received signal is demodulated by the ASK
demodulator.
5.1.2 Frequency
The ISO/IEC 15693 standard defines the carrier frequency (fC) of the operating field as
13.56 MHz ±7 kHz.
5.1.3 Operating field
The LRIS64K operates continuously between H
●The minimum operating field is H
●The maximum operating field is H
A VCD shall generate a field of at least H
volume.
and H
min
and has a value of 150 mA/m rms.
min
and has a value of 5 A/m rms.
max
and not exceeding H
min
max
.
max
in the operating
20/100Doc ID 15336 Rev 11
LRIS64KCommunication signal from VCD to LRIS64K
105%
a
95%
5%
60%
Carrier
Amplitude
t
t
2
t
1
t
3
t
4
Min (µs)
t1
6,0
t22,1
t3
0
Max (µs)
9,44
t1
4,5
t4
00,8
b
The clock recovery shall be operational after t
4
max.
ai15793
6 Communication signal from VCD to LRIS64K
Communications between the VCD and the LRIS64K takes place using the modulation
principle of ASK (Amplitude Shift Keying). Two modulation indexes are used, 10% and
100%. The LRIS64K decodes both. The VCD determines which index is used.
The modulation index is defined as [a – b]/[a + b] where a is the peak signal amplitude and
b, the minimum signal amplitude of the carrier frequency.
Depending on the choice made by the VCD, a “pause” will be created as described in
Figure 3 and Figure 4.
The LRIS64K is operational for any degree of modulation index from between 10% and
30%.
Figure 3.100% modulation waveform
Table 10.10% modulation parameters
SymbolParameter definitionValue
hr0.1 x (a – b)Max
hf0.1 x (a – b)Max
Doc ID 15336 Rev 1121/100
Communication signal from VCD to LRIS64KLRIS64K
Figure 4.10% modulation waveform
Carrier
Carrier
Amplitude
Amplitude
a
a
b
b
t1
t1
t1
t23,0 µs
t23,0 µs
t23,0 µst30
t30
t30
Modulation
Modulation
Modulation
Index
Index
Index
The VICC shall be operational for any value of modulation index between 10 % and 30 %.
The data coding implemented in the LRIS64K uses pulse position modulation. Both data
coding modes that are described in the ISO/IEC15693 are supported by the LRIS64K. The
selection is made by the VCD and indicated to the LRIS64K within the start of frame (SOF).
7.1 Data coding mode: 1 out of 256
The value of one single byte is represented by the position of one pause. The position of the
pause on 1 of 256 successive time periods of 18.88 µs (256/f
byte. In this case the transmission of one byte takes 4.833 ms and the resulting data rate is
1.65 kbits/s (f
/8192).
C
Figure 5 illustrates this pulse position modulation technique. In this figure, data E1h (225
decimal) is sent by the VCD to the LRIS64K.
The pause occurs during the second half of the position of the time period that determines
the value, as shown in Figure 6.
A pause during the first period transmits the data value 00h. A pause during the last period
transmit the data value FFh (255 decimal).
), determines the value of the
C
Figure 5.1 out of 256 coding mode
Doc ID 15336 Rev 1123/100
Data rate and data codingLRIS64K
AI06657
2
2
5
18.88 µs
9.44 µs
Pulse
Modulated
Carrier
2
2
6
2
2
4
. . . . . . .. . . . . . .
Time Period
one of 256
Figure 6.Detail of a time period
7.2 Data coding mode: 1 out of 4
The value of 2 bits is represented by the position of one pause. The position of the pause on
1 of 4 successive time periods of 18.88 µs (256/f
successive pairs of bits form a byte, where the least significant pair of bits is transmitted first.
In this case the transmission of one byte takes 302.08 µs and the resulting data rate is 26.48
Kbits/s (f
Figure 8 shows the transmission of E1h (225d - 1110 0001b) by the VCD.
/512). Figure 7 illustrates the 1 out of 4 pulse position technique and coding.
C
), determines the value of the 2 bits. Four
C
24/100Doc ID 15336 Rev 11
LRIS64KData rate and data coding
AI06658
9.44 µs9.44 µs
75.52 µs
28.32 µs9.44 µs
75.52 µs
47.20µs9.44 µs
75.52 µs
66.08 µs9.44 µs
75.52 µs
Pulse position for "00"
Pulse position for "11"
Pulse position for "10" (0=LSB)
Pulse position for "01" (1=LSB)
AI06659
75.52µs75.52µs75.52µs75.52µs
00
10
0111
Figure 7.1 out of 4 coding mode
Figure 8.1 out of 4 coding example
Doc ID 15336 Rev 1125/100
Data rate and data codingLRIS64K
AI06661
37.76µs
9.44µs
9.44µs
37.76µs
AI06660
37.76µs
9.44µs
9.44µs
37.76µs
9.44µs
AI06662
9.44µs
37.76µs
9.44µs
7.3 VCD to LRIS64K frames
Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are
implemented using code violation. Unused options are reserved for future use.
The LRIS64K is ready to receive a new command frame from the VCD 311.5 µs (t
sending a response frame to the VCD.
The LRIS64K takes a power-up time of 0.1 ms after being activated by the powering field.
After this delay, the LRIS64K is ready to receive a command frame from the VCD.
7.4 Start of frame (SOF)
The SOF defines the data coding mode the VCD is to use for the following command frame.
The SOF sequence described in Figure 9 selects the 1 out of 256 data coding mode. The
SOF sequence described in Figure 10 selects the 1 out of 4 data coding mode. The EOF
sequence for either coding mode is described in Figure 11.
Figure 9.SOF to select 1 out of 256 data coding mode
) after
2
Figure 10. SOF to select 1 out of 4 data coding mode
Figure 11. EOF for either data coding mode
26/100Doc ID 15336 Rev 11
LRIS64KCommunications signal from LRIS64K to VCD
8 Communications signal from LRIS64K to VCD
The LRIS64K has several modes defined for some parameters, owing to which it can
operate in different noise environments and meet different application requirements.
8.1 Load modulation
The LRIS64K is capable of communication to the VCD via an inductive coupling area
whereby the carrier is loaded to generate a subcarrier with frequency f
generated by switching a load in the LRIS64K.
The load-modulated amplitude received on the VCD antenna must be of at least 10mV
when measured as described in the test methods defined in International Standard
ISO/IEC10373-7.
8.2 Subcarrier
The LRIS64K supports the one-subcarrier and two-subcarrier response formats. These
formats are selected by the VCD using the first bit in the protocol header. When one
subcarrier is used, the frequency f
When two subcarriers are used, the frequency f
is 484.28 kHz (f
continuous phase relationship between f
of the subcarrier load modulation is 423.75 kHz (fC/32).
S1
/28). When using the two-subcarrier mode, the LRIS64K generates a
C
and fS2.
S1
is 423.75 kHz (fC/32), and frequency fS2
S1
. The subcarrier is
S
8.3 Data rates
The LRIS64K can respond using the low or the high data rate format. The selection of the
data rate is made by the VCD using the second bit in the protocol header. It also supports
the x2 mode available on all the Fast commands. Ta bl e 1 1 shows the different data rates
produced by the LRIS64K using the different response format combinations.
Table 11.Response data rates
Data rateOne subcarrierTwo subcarriers
Standard commands6.62 Kbit/s (f
Low
Fast commands13.24 Kbit/s (f
Standard commands26.48 Kbit/s (f
High
Fast commands52.97 Kbit/s (f
/2048)6.67 Kbit/s (fc/2032)
c
/1024)not applicable
c
/512)26.69 Kbit/s (fc/508)
c
/256)not applicable
c
Doc ID 15336 Rev 1127/100
Bit representation and codingLRIS64K
37.76µs
ai12076
18.88µs
ai12066
37.76µs
ai12077
18.88µs
ai12067
9 Bit representation and coding
Data bits are encoded using Manchester coding, according to the following schemes. For
the low data rate, same subcarrier frequency or frequencies is/are used, in this case the
number of pulses is multiplied by 4 and all times will increase by this factor. For the Fast
commands using one subcarrier, all pulse numbers and times are divided by 2.
9.1 Bit coding using one subcarrier
9.1.1 High data rate
A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of
18.88 µs as shown in Figure 12.
Figure 12. Logic 0, high data rate, one subcarriers
For the fast commands, a logic 0 starts with 4 pulses at 423.75 kHz (f
/32) followed by an
C
unmodulated time of 9.44 µs as shown in Figure 13.
Figure 13. Logic 0, high data rate, one subcarriers x2
A logic 1 starts with an unmodulated time of 18.88 µs followed by 8 pulses at 423.75 kHz
(f
/32) as shown in Figure 14.
C
Figure 14. Logic 1, high data rate, one subcarriers
For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by 4
pulses of 423.75 kHz (f
/32) as shown in Figure 15.
C
Figure 15. Logic 1, high data rate, one subcarriers x2
28/100Doc ID 15336 Rev 11
LRIS64KBit representation and coding
151.04µs
ai12068
75.52µs
ai12069
151.04µs
ai12070
75.52µs
ai12071
9.1.2 Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of
75.52 µs as shown in Figure 16.
Figure 16. Logic 0, low data rate, one subcarriers
For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (f
/32) followed by an
C
unmodulated time of 37.76 µs as shown in Figure 17.
Figure 17. Logic 0, low data rate, one subcarriers x2
A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz
(f
/32) as shown in Figure 18.
C
Figure 18. Logic 1, low data rate, one subcarriers
For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by
16 pulses at 423.75 kHz (f
/32) as shown in Figure 18.
C
Figure 19. Logic 1, low data rate, one subcarriers x2
Doc ID 15336 Rev 1129/100
Bit representation and codingLRIS64K
37.46µs
ai12074
37.46µs
ai12073
149.84µs
ai12072
149.84µs
ai12075
9.2 Bit coding using two subcarriers
9.3 High data rate
A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by 9 pulses at 484.28 kHz
(f
/28) as shown in Figure 20. For the Fast commands, the x2 mode is not available.
C
Figure 20. Logic 0, high data rate, two subcarriers
A logic 1 starts with 9 pulses at 484.28 kHz (f
(f
/32) as shown in Figure 21. For the Fast commands, the x2 mode is not available.
C
Figure 21. Logic 1, high data rate, two subcarriers
9.4 Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by 36 pulses at 484.28 kHz
(f
/28) as shown in Figure 22. For the Fast commands, the x2 mode is not available.
C
Figure 22. Logic 0, low data rate, two subcarriers
A logic 1 starts with 36 pulses at 484.28 kHz (f
(f
/32) as shown in Figure 23. For the Fast commands, the x2 mode is not available.
C
/28) followed by 8 pulses at 423.75 kHz
C
/28) followed by 32 pulses at 423.75 kHz
C
Figure 23. Logic 1, low data rate, two subcarriers
30/100Doc ID 15336 Rev 11
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