2048-bit EEPROM tag IC at 13.56 MHz, with 64-bit UID and
Sawn Bumped Wafer
Password, ISO15693 and ISO18000-3 Mode 1 compliant
Features
■ ISO 15693 standard fully compliant
■ ISO 18000-3 Mode 1 standard fully compliant
■ 13.56 MHz ±7 kHz carrier frequency
■ To tag: 10% or 100% ASK modulation using
1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse
position coding
■ From tag: Load modulation using Manchester
coding with 423 kHz and 484 kHz subcarriers
in Low (6.6 Kbit/s) or High (26 Kbit/s) data rate
mode. Supports the 53 Kbit/s data rate with
Fast commands
The LRIS2K is a contactless memory powered by the received carrier electromagnetic
wave, which follows the ISO 15693 recommendation for radio frequency power and signal
interface. It is a 2048-bit electrically erasable programmable memory (EEPROM). The
memory is organized as 64 blocks of 32 bits. The LRIS2K is accessed via the 13.56 MHz
carrier electromagnetic wave on which incoming data are demodulated from the received
signal amplitude modulation (ASK: amplitude shift keying). The received ASK wave is 10%
or 100% modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode or a
Data rate of 26 Kbit/s using the 1/4 pulse coding mode.
Outgoing data are generated by the LRIS2K load variation using Manchester coding with
one or two subcarrier frequencies at 423 KHz and 484 kHz. Data are transferred from the
LRIS2K at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The LRIS2K
supports the 53 Kbit/s in high data rate mode in one subcarrier frequency at 423 kHz.
The LRIS2K also features a unique 32-bit multi-password protection scheme.
Figure 1.Pad connections
Table 1.Signal names
AC1Antenna coil
AC0Antenna coil
Signal nameFunction
Doc ID 13888 Rev 911/98
DescriptionLRIS2K
1.1 Memory mapping
The LRIS2K is divided into 64 blocks of 32 bits as shown in Ta bl e 2 . Each block can be
individually read- and/or write-protected using a specific lock or password command.
The user area consists of blocks that are always accessible. Read and Write operations are
possible if the addressed block is not protected. During a Write, the 32 bits of the block are
replaced by the new 32-bit value.
The LRIS2K also has a 64-bit block that is used to store the 64-bit unique identifier (UID).
The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user and its value is
written by ST on the production line.
The LRIS2K also includes an AFI register in which the application family identifier is stored,
and a DSFID register in which the data storage family identifier used in the anticollision
algorithm is stored. The LRIS2K has four additional 32-bit blocks in which the Kill code and
the password codes are stored.
Table 2.Memory map
Add07 815 1623 2431Protect status
0User area5 bits
1User area5 bits
2User area5 bits
3User area5 bits
4User area5 bits
5User area5 bits
6User area5 bits
7User area5 bits
8User area5 bits
.........
60User area5 bits
61User area5 bits
62User area5 bits
63User area5 bits
UID 0UID 1UID 2UID 3
UID 4UID 5UID 6UID 7
AFIDSFID
(1)
0
(1)
1
(1)
2
(1)
3
1. RFU bit (b8) of Request_flag set to 1.
12/98Doc ID 13888 Rev 9
Kill code5 bits
Password code 15 bits
Password code 25 bits
Password code 35 bits
LRIS2KDescription
1.2 Commands
The LRIS2K supports the following commands:
●Inventory, used to perform the anticollision sequence.
●Stay Quiet, used to put the LRIS2K in quiet mode, where it does not respond to any
inventory command.
●Select, used to select the LRIS2K. After this command, the LRIS2K processes all
Read/Write commands with Select_flag set.
●Reset To Ready, used to put the LRIS2K in the ready state.
●Read Block, used to output the 32 bits of the selected block and its locking status.
●Write Block, used to write the 32-bit value in the selected block, provided that it is not
locked.
●Lock Block, used to lock the selected block. After this command, the block cannot be
modified.
●Write AFI, used to write the 8-bit value in the AFI register.
●Lock AFI, used to lock the AFI register.
●Write DSFID, used to write the 8-bit value in the DSFID register.
●Lock DSFID, used to lock the DSFID register.
●Get System Info, used to provide the system information value
●Get Multiple Block Security Status, used to send the security status of the selected
block.
●Initiate, used to trigger the tag response to the Inventory Initiated sequence.
●Inventory Initiated, used to perform the anticollision sequence triggered by the Initiate
command.
●Kill, used to definitively deactivate the tag.
●Write Password, used to write the 32 bits of the selected password.
●Lock Password, used to write the Protect Status bits of the selected block.
●Present Password, enables the user to present a password to unprotect the user
blocks linked to this password.
●Fast Initiate, used to trigger the tag response to the Inventory Initiated sequence.
●Fast Inventory Initiated, used to perform the anticollision sequence triggered by the
Initiate command.
●Fast Read Single Block, used to output the 32 bits of the selected block and its
locking status.
Doc ID 13888 Rev 913/98
DescriptionLRIS2K
1.3 Initial dialogue for vicinity cards
The dialog between the vicinity coupling device (VCD) and the vicinity integrated circuit
Card or VICC (LRIS2K) takes place as follows:
●activation of the LRIS2K by the RF operating field of the VCD.
●transmission of a command by the VCD.
●transmission of a response by the LRIS2K.
These operations use the RF power transfer and communication signal interface described
below (see Power transfer, Frequency and Operating field). This technique is called RTF
(Reader Talk First).
1.3.1 Power transfer
Power is transferred to the LRIS2K by radio frequency at 13.56 MHz via coupling antennas
in the LRIS2K and the VCD. The RF operating field of the VCD is transformed on the
LRIS2K antenna to an AC Voltage which is rectified, filtered and internally regulated. The
amplitude modulation (ASK) on this received signal is demodulated by the ASK
demodulator.
1.3.2 Frequency
The ISO 15693 standard defines the carrier frequency (fC) of the operating field as
13.56 MHz ±7 kHz.
1.3.3 Operating field
The LRIS2K operates continuously between H
●The minimum operating field is H
●The maximum operating field is H
A VCD shall generate a field of at least H
volume.
and H
min
and has a value of 150 mA/m rms.
min
and has a value of 5 A/m rms.
max
and not exceeding H
min
max
.
max
in the operating
14/98Doc ID 13888 Rev 9
LRIS2KLRIS2K block security
2 LRIS2K block security
The LRIS2K provides a special protection mechanism based on passwords. Each memory
block of the LRIS2K can be individually protected by one out of three available passwords,
and each block can also have Read/Write access conditions set.
Each memory block of the LRIS2K is assigned with a Protect Status area including a Block
Lock bit, two Password Control bits and two Read/Write protection bits as shown in Ta bl e 4 .
Ta bl e 4 describes the organization of the Protect status area which can be read using the
Read Single Block command with the Option_flag set to ‘1’, and the Get Multiple Block
Security status command.
Table 3.Memory blocks with protect status area
Add07 815 1623 2431Protect status
0User area5 bits
1User area5 bits
...User area5 bits
Table 4.Protect status area organization
b
7
000Password Control bits
b
6
b
5
b
4
b
3
b
2
b
1
Read / Write protection
bits
b
0
Block Lock
When the Block Lock bit is set to ‘1’, for instance by issuing a Block Lock command, the 2
Read/Write protection bits (b
, b2) are used to set the Read/Write access of the block as
1
described in Ta b le 5 .
The next 2 bits of the Protect Status area (b
, b4) are the Password Control bits. The value
3
of these two bits is used to link a password to the block as defined in Ta bl e 5 .
Combinations not described in Ta bl e 5 are reserved.
, b
1
Password
Control bits
b4, b
3
Block access when
password presented
Block access when
password not presented
Block protection status
the block is protected by
password 1
the block is protected by
password 2
the block is protected by
password 3
the block is not protected
by a password
Table 5.Read / Write protection bit setting and block protection status
Block lock
function
b
0b2
00000Not applicableREADWRITEthe block is not protected
11101READNO WRITENO READNO WRITE
11110READNO WRITENO READNO WRITE
11111READNO WRITENO READNO WRITE
10000Not applicableREADNO WRITE
Doc ID 13888 Rev 915/98
LRIS2K block securityLRIS2K
The LRIS2K password protection is organized around a dedicated set of commands plus a
system area of four password blocks where the password values and the Kill code are
stored. Each password block also has a Protect Status area, making it possible to set the
Read / Write access right of each individual block. This system area is described in Ta bl e 6 .
Table 6.Password system area
Add07 815 1623 2431Protect status
0Kill code5 bits
1Password 15 bits
2Password 25 bits
3Password 35 bits
The dedicated password commands are:
●Write Password:
The Write Password command is used to write a 32-bit block into the password system
area. This command must be used to write or update password values and to set the
kill code. Depending on the Read/Write access set in the Protect Status area, it is
possible to modify a password value after issuing a valid Present Password command.
●Lock Password:
The Lock Password command is used to set the Protect Status area of the selected
block. Bits b
The Block Lock bit, b
to b1 of the Protect Status are affected by the Lock Password command.
4
, is set to ‘1’ automatically. After issuing a Lock Password
0
command, the protection settings of the selected block are activated. The protection of
a locked block cannot be changed. A Lock Password command sent to a locked block
returns an error code.
The Lock Password command is also used to set the Protect Status areas of the
password blocks. RFU bit 8 of the Request_flag is used to select either the memory
area (bit 8 = ‘0’) or the password area (bit 8 = ‘1’).
●Present Password:
The Present Password command is used to present one of the three passwords to the
LRIS2K in order to modify the access rights of all the memory blocks linked to that
password (Ta bl e 5 ) including the password itself. If the presented password is correct,
the access rights remain activated until the tag is powered off or until a new Present
Password command is issued.
16/98Doc ID 13888 Rev 9
LRIS2KExample of LRIS2K security protection
3 Example of LRIS2K security protection
Ta bl e 7 and Ta bl e 8 show the block security protections before and after a valid Present
Password command. The Ta bl e 7 shows blocks access rights of an LRIS2K after power-up.
After a valid Present Password command with password 1, the memory block access is
changed as given in Tab le 8 .
Table 7.LRIS2K block security protection after power-up
Protect status
Add
0781516232431b
0Protection: Standard, Read - No Writexxx00001
4Protection: Pswd 1,No Read- No Writexxx 01111
Table 8.LRIS2K block security protection after a valid presentation of password 1
Add
0781516232431b
0Protection: Standard,Read - No Writexxx00001
4Protection: Pswd 1,Read- No Writexxx 01111
7b6b5b4b3b2b1b0
Protect status
7b6b5b4b3b2b1b0
Doc ID 13888 Rev 917/98
Communication signal from VCD to LRIS2KLRIS2K
AI06683
tRFF
tRFSBL
tRFR
105%
a
t
100%
95%
60%
5%
4 Communication signal from VCD to LRIS2K
Communications between the VCD and the LRIS2K takes place using the modulation
principle of ASK (Amplitude Shift Keying). Two modulation indexes are used, 10% and
100%. The LRIS2K decodes both. The VCD determines which index is used.
The modulation index is defined as [a – b]/[a + b] where a is the peak signal amplitude and
b, the minimum signal amplitude of the carrier frequency.
Depending on the choice made by the VCD, a “pause” will be created as described in
Figure 2 and Figure 3.
The LRIS2K is operational for any degree of modulation index from between 10% and 30%.
The data coding implemented in the LRIS2K uses pulse position modulation. Both data
coding modes that are described in the ISO15693 are supported by the LRIS2K. The
selection is made by the VCD and indicated to the LRIS2K within the start of frame (SOF).
5.1 Data coding mode: 1 out of 256
The value of one single byte is represented by the position of one pause. The position of the
pause on 1 of 256 successive time periods of 18.88 µs (256/f
byte. In this case the transmission of one byte takes 4.833 ms and the resulting data rate is
1.65 kbits/s(f
/8192).
C
Figure 4 illustrates this pulse position modulation technique. In this figure, data E1h (225
decimal) is sent by the VCD to the LRIS2K.
The pause occurs during the second half of the position of the time period that determines
the value, as shown in Figure 5.
A pause during the first period transmits the data value 00h. A pause during the last period
transmit the data value FFh (255 decimal).
), determines the value of the
C
Figure 4.1 out of 256 coding mode
20/98Doc ID 13888 Rev 9
LRIS2KData rate and data coding
AI06657
2
2
5
18.88 µs
9.44 µs
Pulse
Modulated
Carrier
2
2
6
2
2
4
. . . . . . .. . . . . . .
Time Period
one of 256
Figure 5.Detail of a time period
Doc ID 13888 Rev 921/98
Data rate and data codingLRIS2K
AI06658
9.44 µs9.44 µs
75.52 µs
28.32 µs9.44 µs
75.52 µs
47.20µs9.44 µs
75.52 µs
66.08 µs9.44 µs
75.52 µs
Pulse position for "00"
Pulse position for "11"
Pulse position for "10" (0=LSB)
Pulse position for "01" (1=LSB)
AI06659
75.52µs75.52µs75.52µs75.52µs
00
10
0111
5.2 Data coding mode: 1 out of 4
The value of 2 bits is represented by the position of one pause. The position of the pause on
1 of 4 successive time periods of 18.88 µs (256/f
successive pairs of bits form a byte, where the least significant pair of bits is transmitted first.
In this case the transmission of one byte takes 302.08 µs and the resulting data rate is 26.48
Kbits/s (f
/512). Figure 6 illustrates the 1 out of 4 pulse position technique and coding.
C
Figure 7 shows the transmission of E1h (225d - 1110 0001b) by the VCD.
Figure 6.1 out of 4 coding mode
), determines the value of the 2 bits. Four
C
22/98Doc ID 13888 Rev 9
Figure 7.1 out of 4 coding example
LRIS2KData rate and data coding
AI06661
37.76µs
9.44µs
9.44µs
37.76µs
AI06660
37.76µs
9.44µs
9.44µs
37.76µs
9.44µs
5.3 VCD to LRIS2K frames
Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are
implemented using code violation. Unused options are reserved for future use.
The LRIS2K is ready to receive a new command frame from the VCD 311.5 µs (t
sending a response frame to the VCD.
The LRIS2K takes a power-up time of 0.1 ms after being activated by the powering field.
After this delay, the LRIS2K is ready to receive a command frame from the VCD.
5.4 Start of frame (SOF)
The SOF defines the data coding mode the VCD is to use for the following command frame.
The SOF sequence described in Figure 8 selects the 1 out of 256 data coding mode. The
SOF sequence described in Figure 9 selects the 1 out of 4 data coding mode. The EOF
sequence for either coding mode is described in Figure 10.
Figure 8.SOF to select 1 out of 256 data coding mode
) after
2
Figure 9.SOF to select 1 out of 4 data coding mode
Doc ID 13888 Rev 923/98
Data rate and data codingLRIS2K
AI06662
9.44µs
37.76µs
9.44µs
Figure 10. EOF for either data coding mode
24/98Doc ID 13888 Rev 9
LRIS2KCommunications signal from LRIS2K to VCD
6 Communications signal from LRIS2K to VCD
The LRIS2K has several modes defined for some parameters, owing to which it can operate
in different noise environments and meet different application requirements.
6.1 Load modulation
The LRIS2K is capable of communication to the VCD via an inductive coupling area
whereby the carrier is loaded to generate a subcarrier with frequency f
generated by switching a load in the LRIS2K.
The load-modulated amplitude received on the VCD antenna must be of at least 10mV
when measured as described in the test methods defined in International Standard
ISO10373-7.
6.2 Subcarrier
The LRIS2K supports the one-subcarrier and two-subcarrier response formats. These
formats are selected by the VCD using the first bit in the protocol header. When one
subcarrier is used, the frequency f
When two subcarriers are used, the frequency f
is 484.28 kHz (f
continuous phase relationship between f
of the subcarrier load modulation is 423.75 kHz (fC/32).
S1
/28). When using the two-subcarrier mode, the LRIS2K generates a
C
and fS2.
S1
is 423.75 kHz (fC/32), and frequency fS2
S1
. The subcarrier is
S
6.3 Data rates
The LRIS2K can respond using the low or the high data rate format. The selection of the
data rate is made by the VCD using the second bit in the protocol header. It also supports
the x2 mode available on all the Fast commands. Tab le 1 0 shows the different data rates
produced by the LRIS2K using the different response format combinations.
Table 10.Response data rates
Data rateOne subcarrierTwo subcarriers
Standard commands6.62 Kbits/s (f
Low
Fast commands13.24 Kbits/s (f
Standard commands26.48 Kbits/s (f
High
Fast commands52.97 Kbits/s (f
/2048)6.67 Kbits/s (fc/2032)
c
/1024)not applicable
c
/512)26.69 Kbits/s (fc/508)
c
/256)not applicable
c
Doc ID 13888 Rev 925/98
Bit representation and codingLRIS2K
37.76µs
ai12076
18.88µs
ai12066
37.76µs
ai12077
18.88µs
ai12067
7 Bit representation and coding
Data bits are encoded using Manchester coding, according to the following schemes. For
the low data rate, same subcarrier frequency or frequencies is/are used, in this case the
number of pulses is multiplied by 4 and all times will increase by this factor. For the Fast
commands using one subcarrier, all pulse numbers and times are divided by 2.
7.1 Bit coding using one subcarrier
7.1.1 High data rate
A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of
18.88 µs as shown in Figure 11.
Figure 11. Logic 0, high data rate
For the fast commands, a logic 0 starts with 4 pulses at 423.75 kHz (f
/32) followed by an
C
unmodulated time of 9.44 µs as shown in Figure 12.
Figure 12. Logic 0, high data rate x2
A logic 1 starts with an unmodulated time of 18.88 µs followed by 8 pulses at 423.75 kHz
/32) as shown in Figure 13.
(f
C
Figure 13. Logic 1, high data rate
For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by 4
pulses of 423.75 kHz (f
/32) as shown in Figure 14.
C
Figure 14. Logic 1, high data rate x2
26/98Doc ID 13888 Rev 9
LRIS2KBit representation and coding
151.04µs
ai12068
75.52µs
ai12069
151.04µs
ai12070
75.52µs
ai12071
7.1.2 Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of
75.52 µs as shown in Figure 15.
Figure 15. Logic 0, low data rate
For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (f
/32) followed by an
C
unmodulated time of 37.76 µs as shown in Figure 16.
Figure 16. Logic 0, low data rate x2
A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz
/32) as shown in Figure 17.
(f
C
Figure 17. Logic 1, low data rate
For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by
16 pulses at 423.75 kHz (f
/32) as shown in Figure 17.
C
Figure 18. Logic 1, low data rate x2
Doc ID 13888 Rev 927/98
Bit representation and codingLRIS2K
37.46µs
ai12074
37.46µs
ai12073
149.84µs
ai12072
149.84µs
ai12075
7.2 Bit coding using two subcarriers
7.3 High data rate
A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by 9 pulses at 484.28 kHz
/28) as shown in Figure 19. For the Fast commands, the x2 mode is not available.
(f
C
Figure 19. Logic 0, high data rate
A logic 1 starts with 9 pulses at 484.28 kHz (f
/32) as shown in Figure 20. For the Fast commands, the x2 mode is not available.
(f
C
Figure 20. Logic 1, high data rate
7.4 Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by 36 pulses at 484.28 kHz
/28) as shown in Figure 21. For the Fast commands, the x2 mode is not available.
(f
C
Figure 21. Logic 0, low data rate
A logic 1 starts with 36 pulses at 484.28 kHz (f
/32) as shown in Figure 22. For the Fast commands, the x2 mode is not available.
(f
C
/28) followed by 8 pulses at 423.75 kHz
C
/28) followed by 32 pulses at 423.75 kHz
C
Figure 22. Logic 1, low data rate
28/98Doc ID 13888 Rev 9
LRIS2KLRIS2K to VCD frames
113.28µs
ai12078
37.76µs
56.64µs
ai12079
18.88µs
8 LRIS2K to VCD frames
Frames are delimited by an SOF and an EOF. They are implemented using code violation.
Unused options are reserved for future use. For the low data rate, the same subcarrier
frequency or frequencies is/are used. In this case the number of pulses is multiplied by 4.
For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.
8.1 SOF when using one subcarrier
8.2 High data rate
The SOF includes an unmodulated time of 56.64 µs, followed by 24 pulses at 423.75 kHz
/32), and a logic 1 that consists of an unmodulated time of 18.88 µs followed by 8 pulses
(f
C
at 423.75 kHz as shown in Figure 23.
Figure 23. Start of frame, high data rate, one subcarrier
For the Fast commands, the SOF comprises an unmodulated time of 28.32 µs, followed by
12 pulses at 423.75 kHz (f
/32), and a logic 1 that consists of an unmodulated time of
C
9.44µs followed by 4 pulses at 423.75 kHz as shown in Figure 24.
Figure 24. Start of frame, high data rate, one subcarrier x2
Doc ID 13888 Rev 929/98
LRIS2K to VCD framesLRIS2K
453.12µs
ai12080
151.04µs
226.56µs
ai12081
75.52µs
8.3 Low data rate
The SOF comprises an unmodulated time of 226.56 µs, followed by 96 pulses at 423.75 kHz
/32), and a logic 1 that consists of an unmodulated time of 75.52 µs followed by 32 pulses
(f
C
at 423.75 kHz as shown in Figure 25.
Figure 25. Start of frame, low data rate, one subcarrier
For the Fast commands, the SOF comprises an unmodulated time of 113.28 µs, followed by
48 pulses at 423.75 kHz (f
followed by 16 pulses at 423.75 kHz as shown in Figure 26.
Figure 26. Start of frame, low data rate, one subcarrier x2
/32), and a logic 1 that includes an unmodulated time of 37.76 µs
C
30/98Doc ID 13888 Rev 9
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