ST LNBP21 User Manual

LNBP21

LNBP SUPPLY AND CONTROL IC WITH

STEP-UP CONVERTER AND I

■ COMPLETE INTERFACE BETWEEN LNB

■ BUILT-IN DC/DC CONTROLLER FOR

■ ACCURATE BUILT-IN 22KHz TONE

■ SUITS WIDELY ACCEPTED STANDARDS

■ FAST OSCILLATOR START -U P F ACILITA TES

■ BUIL T-IN 22KHz TONE DETECTOR

■ LOOP-THROUGH FUNCTION FOR SLAVE

■ LNB SHORT CIRCUIT PROTECTION AND

■ CABLE LENGTH DIGITAL COMPENSATION

■ INTERNAL OVER TEMPERATURE

■ ESD RATING 4KV ON POWER

2CTM

AND I

BUS SINGLE 12V SUPPLY OPERATION OSCILLATOR

DiSEqC

ENCODING SUPPORTS BI-DIRECTIONAL DiSEqC OPERATION DIAGNOSTIC

PROTECTION INPUT-OUTPUT PINS

C INTERFACE

SO-20PowerSO-20

DESCRIPTION

Intended for analog and digital satellite STB receivers/SatTV, sets/PC cards, the LNBP21 is a monolithic voltage regulator and interface IC, assembled in SO-20 and PowerSO-20, specifically designed to provide the power and the 13/18V, 22KHz t one signalling to the LNB down converter in the antenna or to the multiswitch box. In this application field, it offers a complete solution with extremely low co mpo nent c ount, low

Figure 1: Block Diagram

Gate

Sense

Vup

Vcc

Byp

SDA SCL

ADDR

DSQIN

Preregul.+

U.V.lockout

+P.ON res.

I²C interf.

Step-up

Controller

LNBP21

Feedback

Enable I Select V Sele ct

Linear Post-reg

+Modulator

+Protections

22KHz Oscill.

Diagnostics

Tone

Detector

LT1

LT2

OUT

EXTM

DETIN

DSQOUT

Rev. 3

1/24October 2004

LNBP21

power dissipation together with simple design and

2CTM

standard interfacing. This IC has a built in DC/DC step-up controller that, from a single supply source ranging from 8 to 15V, generates the voltages that let the linear post-regulator to work at a minimum dissipated power. An UnderVoltage Lockout circuit will disable the whole circuit when th e supplied V

drops below a fixed threshold (6.7V typically). The internal 22KHz tone generator is factory trimmed in accordance to the standards, and can be controlled either by the I dedicated pin (DSQIN) that allows immediate DiSEqC

data encoding (*). A ll the functions of

this IC are controlled via I

2CTM

interface or by a

2CTM

bus by writing 6 bits on the System Register (SR, 8 bits). The same register can be read back, a nd two bits will report the diagnostic status. When the IC is put in Stand-by (EN bit LOW), the power blocks are disabled and the loop-through switch between LT1 and LT2 pins is closed, thus leaving all LNB powering and control functions to the Master Receiver (**). When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V (typ.) by mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typ.) the sel ected vol tage value to compensate for the ex cess voltage drop along the coaxial cable (LLC bit HIGH). In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. Another bit of the SR is addressed to the remote control of non-DiSEqC LNBs: the TEN (Tone ENable) bit. When it is set to HIGH, a continuous 22KHz tone is generated regardless of the DSQIN pin logic status. The TEN bi t must be set LOW when the DSQIN pin is used for DiSEqC DiSEqC 22KHz tone detector. Its input pin (DETIN) must be AC coupled to the DiSEqC

encoding. The fully bidirectional

interfacing is completed b y the bui lt-in

bus, and the extracted PWK data are available on the DSQOUT pin (*). In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. When external

(*): External components are needed to comply to bi-di rectional Di S EqCTM bus hard ware requir em ents. Full complian ce of the whole appl i cation to DiSEqCTM specificat i ons is not imp l i ed by the use of th i s I C. (**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must be externally limited.

modulation is not used, the relevant pin can be left open.

The current limitation block has two thresholds that can be selected by the I

bit of the SR; the

SEL

lower threshold is between 400 and 550mA (I

=HIGH), while the higher threshold is

SEL

between 500 and 650mA (I

SEL

=LOW).

The current protection block is SOA type. This limits the short circuit current (I 200mA with I I

=LOW when the output port is connected to

SEL

=HIGH and at 300mA with

SEL

) typically at

ground. It is possible to set the Short Circuit Current

protection either statically (simple current clam p) or dynamically by the PCL bit of the SR; when the PCL (Pulsed Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically: as soon as an overloa d is detected, the output is shut-down for a time t

, typically

off

900ms. Simultaneously th e OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time t 10t

(typ.). At the end of ton, if the overload is still

off

=1/

detected, the protection circuit will cycle again through T

and Ton. At the end of a full Ton in

off

which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical T

time is 990ms and it is determined by an

on+Toff

internal timer. This d yn amic operat ion can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions (**).

However, there could be some cases in which an highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=HIGH) and then switching to the dynamic m ode (PCL=LO W) a fter a chosen am ount of time. When in static m ode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared.

This IC is also protected against overheating: when the junction temperature exceeds 150°C (typ.), the step-up converter and the linear regulator are shut off, the loop-trough switch is opened, and the OTF bit of the SR is set to HIGH. Normal operation is resum ed and the OTF bit is reset to LOW when the junction is cooled down to 140°C (typ.).

2/24

Table 1: Ordering Codes

LNBP21

TYPE

SO-20

(Tube)

SO-20

(Tape & Reel)

PowerSO-20

(Tube)

PowerSO-20

(Tape & Reel)

LNBP21 LNBP21D2 LNBP21D2-TR LNBP21PD LNBP21PD-TR

Table 2: Absolute Maximum Ratings

Symbol Parameter Value Unit

V V

LT1

DETIN

GATE

SENSE

ADDRESS

T T

DC Input Voltage

, V

DC Input Voltage

LT2

Output Current

DC Output Pin Voltage

Logic Input Voltage (SDA, SCL, DSQIN)

Detector Input Signal Amplitude Logic High Output Voltage (DSQOUT)

Bypass Switch ON Current

Bypass Switch OFF Voltage

Gate Current Current Sense Voltage Address Pin Voltage Storage Temperature Range

stg

Operating Junction Temperature Range

16 V 25 V 20 V

Internally Limited mA

-0.3 to 22 V

-0.3 to 7 V 2 7V

900 mA ±20 V

±400 mA

-0.3 to 1 V

-0.3 to 7 V

-40 to +150 °C

-40 to +125 °C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

Table 3: Thermal Data

Symbol Parameter SO-20 PowerSO-20 Unit

thj-case

Thermal Resistance Junction-case

15 2 °C/W

Figure 2: Pin Conf i guration (top view)

SO-20

PowerSO-20

3/24

LNBP21

Table 4: Pin Description

PIN NUMBER

SYMBOL NAME FUNCTION

Supply Input 8V to 15V supply. A 220µF bypass capacitor to

GND with a 470nF (ceramic) in parallel is recommended

GATE External Switch Gate External MOS switch Gate connection of the

step-up converter

SENSE Current Sense Input Current Sense comparator input. Connected to

current sensing resistor

Step-up Voltage Input of the linear post-regulator. The voltage on this

pin is monitored by internal step-ut controller to keep a minimum dropout across the linear pass transistor

OUT Output Port Output of the linear post regulator modulator to the

LNB. See truth table for voltage selections.

SDA Serial Data

SCL Serial Clock

Bidirectional data from/to I Clock from I

C bus.

DSQIN DiSEqC Input When the TEN bit of the System Register is LOW,

this pin will accept the DiSEqC code from the main µcontroller. The LNBP21 will use this code to modulate the internally generated 22kHz carrier. Set to GND this pin if not used.

DETIN Detector In 22kHz Tone Detector Input. Must be AC coupled to

the DiSEqC bus.

DSQOUT DiSEqC Output Open collector output of the tone Detector to the

main µcontroller for DiSEqC data decoding. It is LOW when tone is detected.

EXTM External Modulator External Modulation Input. Need DC decoupling to

the AC source. If not used, can be left open. GND Ground Pins to be connected to ground. 5, 6, 15, 16 1, 6, 10, 11, 20 BYP Bypass Capacitor Needed for internal pre regulator filtering 8 8

LT1 Loop Through Switch In standby mode the power switch between L T1 and

LT2 is closed. Max allowed current is 900mA. this

pin can be left open if loopthrough function is not

needed.

LT2 Loop Through Switch Same as above 2 3

ADDR Address Setting

C bus addresses available by setting the

Four I

Address Pin level voltage

vs. PAC KAG E

SO-20 PowerSO-20

19 18

17 17

14 16

20 19

11 12 12 13 13 14

10 15

4/24

Figure 3: Typical Applica t i on Circuit

C3 470nF

470nF

Ceramic

C4 470nF

470nF

Ceramic

IC2

(Note 3)

L1=22µH

Vin

12V

C2 220µF

220µF

STS4DNFS30L

ΩΩΩΩ

0.1

(Note 4)

C1 220µF

220µF

IC1

Vup

Gate

Sense

Vcc

DSQIN(Note 1)

DSQIN(Note 1) SCL

SCL SDA

SDA

D1 1N4001

LNBP21

GND

LT1

LT2

DETIN

DETIN (Note 1)

(Note 1)

Byp

EXTM

ADDRESS

DSQOUT

C8 10nF

10nF

C6 10nF

10nF

C5 470nF

470nF

C7 10nF

10nF

D2 BAT43

BAT43

Master S TB

270µH

15 ohm

see Note 2

0<Vaddr<V

Byp

LNBP21

to LNB

(*) Set to GND if not used (**) fil ter to be used according to EUTELSAT re c o m m endation to implemen t t h e Di S E q CTM 2.x, not needed if bidirec tional DiSEqCTM 2.x is not impl em ented (see Di S EqC implem entation not e) (***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel MosFet, needed for the DC/DC converter,

in a So-8 pa ckage. It ca n be replaced b y a schottky di ode (STPS2L3A or similar) and a N-Channel MosFet (STN4 NF 03L or similar)

I2C BUS INTERFACE

Data transmission from main µP to the LNBP21 and viceversa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).

DATA VALIDITY

As shown in fig. 3, the data on the SDA line must be stable during the h igh period of t he clock. T he HIGH and LOW state of the data line can only change when the c lock signal on the SCL line is LOW.

ACKNOWLEDGE

The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 4). The peripheral (LNBP21) that acknowledges has to pull-down (LOW) the SDA line during the ack nowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, other-wise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transm itter can generate t he STOP information in order to abort the transfer.

START AND STOP CONDITIONS

As shown in fig. 4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.

The LNBP21 won't generate the acknowledge if the V

supply is below the Undervoltage Lockout

threshold (6.7V typ.). The stop condition is a LOW to HI GH t ransition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition.

TRANSMISSION WITHOUT ACKNOWLEDGE

Avoiding to detect the acknowledge of the

LNBP21, the µP can use a simpler transmission:

BYTE FORMAT

Every byte transferred to the SDA line must contain 8 bits. Eac h byte must be follo wed by an ac-knowledge bit. The MSB is transferred first.

simply it waits one clock without checking the

slave acknowledging, and sends the new data.

This approach of course is less protected from

misworking and decreases the noise immunity.

5/24

LNBP21

Figure 4: Data Validity On The I2C BUS

Figure 5: Timi ng Diagram On I

C Bus

Figure 6: Acknowledge On I

6/24

C Bus

LNBP1 SOFTWARE DESCRIPTION

LNBP21

INTERFACE PROTOCOL

The interface protocol comprises:

- A start condition (S)

CHIP ADDRESS DATA

MSB LSB MSB LSB

S0001000R/WACK ACKP

ACK= Acknowledge S= Start P= Stop R/W= Read/Write

- A chip address byte = hex 10 / 11 (the LSB bit

determines read(=1)/write(=0) transmission)

- A sequence of data (1 byte + acknowledge)

- A stop condition (P)

SYSTEM REGISTER (SR, 1 BYTE)

MSB LSB R, W R, W R, W R, W R, W R, W R R

PCL ISEL TEN LLC VSEL EN OTF OLF

R,W= read and write bit R= Read-only bit All bits reset to 0 at Power-On

TRANSMITTED DATA (I2C BUS WRITE MODE)

When the R/W bit in the chip addres s is set to 0, the main µP can write on the System Register (SR) of the LNBP21 via I

C bus. Only 6 bits out of

the 8 available can be written by the µP, since the

remaining 2 are left to the diagnostic flags, and are

read-only.

PCL ISEL TEN LLC VSEL EN OTF OLF Function

=13V, VUP=16V Loopthrough switch open

001XX 011XX 101XX

111XX 0 1 X X 22KHz tone is controlled by DSQIN pin 1 1 X X 22KHz tone is ON, DSQIN pin disabled

01XX

11XX 0 1 X X Pulsed (dynamic) current limiting is selected 1 1 X X Static current limiting is selected

XXXXX0XXPower blocks disabled, Loopthrough switch closed

X= don't care. Values are typical unl ess otherwi se specified

RECEIVED DATA (I2C bus READ MODE)

The LNBP21 c an provide to th e Master a copy of the SYSTEM R EGISTER inform ation via I

C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following master generate d clocks bits, the LNBP21 issues a byte on the SDA da ta bus line (MSB transmitted first). At the ninth clock bit the MCU master can:

OUT

=18V, VUP=21V Loopthrough switch open

OUT

=14V, VUP=17V Loopthrough switch open

OUT

=19V, VUP=22V Loopthrough switch open

OUT

OUT(min)

=500mA, I =400mA, I

OUT(max) OUT(max)

=650mA ISC=300mA =550mA ISC=300mA

- acknowledge the reception, starting in this way the transmission of another byte from the LNBP21;

- no acknowledge, stopping the read mode communication.

While the whole register is read back by the µP, only the two read-only bi ts OLF and OTF conv ey diagnostic informations about the LNBP21.

7/24

LNBP21

PCL ISEL TEN LLC VSEL EN OTF OLF Function

TJ<140°C, normal operation

>150°C, power block disabled, Loopthrough switch open

0 1

OUT<IOMAX

OUT>IOMAX

, normal operation , overload protection triggered

These bits are read exactly the same as

they were left after last write operation

Values are typical unl ess otherwi se specified

0 1

POWER-ON I2C INTERFACE RESET

The I

C interface built in the LNBP21 is automatically reset at power-on. As long as the V

stays be-low the UnderVoltage Lockout

threshold (6.7V typ.), the interface will not respond to any I

C command and the System Register (SR) is in itialized to all zeroe s, thus keeping the power blocks disabled. Once the V

7.3V, the I

C interface becomes operative and the

rises above

SR can be configured by the main µP. This is due to About 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the Power-On reset circuit.

DiSEqC

IMPLEMENTATION

The LNBP21 helps the system designer to implement the bidirectional (2.x) DiSEqC protocol by allowing an easy PWK modulation/ demodulation of the 22KHz carrier. The PWK data are exchanged between the LNBP21 and the main µP using logic levels that are compatible with both 3.3 and 5V microcontrollers. This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the µP, thus leaving to the resident firmware the task of e ncoding and decoding the

PWK data in accordance t o the DiSEqC protocol. Full compliance of the s ystem to the s pecification is thus not implied by the bare use of the LNBP21.

The system designer should also take in consideration the bus hardware requirements, that include the source impedance of the Master Transmitter measured at 22KHz. To limit the attenuation at carrier frequency, this impedance has to be 15ohm at 22K Hz, d ropping to zero ohm at DC to allow the power flow towards the peripherals. This can be simply accomplished by the LR termination put on the OUT pin of the LNBP, as sh own i n the T y pical Application Circuit on page 5.

Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination, and the OUT pin can be directly connected to the LNB supply port of the Tune r. There is also no need of Tone Decoding, thus, it is recommended to connect the DETIN and DS QOUT pins to ground to avoid EMI.

ADDRESS PIN

Connecting this pin to GND the Chip I

C interface address is 0001000, but, it is possib le to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page

10).

8/24

+ 16 hidden pages