LNB supply and control IC with step-up and I²C interface
Features
■ Complete interface between LNB and I²C bus
■ Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @
0.5 A)
■ Selectable output current limit by external
resistor
■ Compliant with main satellite receiver output
voltage specifications
■ Accurate built-in 22 kHz tone generator suits
widely accepted standards
■ 22 kHz tone waveform integrity guaranteed
also at no load condition
■ Low-drop post regulator and high efficiency
step-up PWM with integrated power N-MOS
allowing low power losses
■ Overload and overtemperature internal
protection with I²C diagnostic bits
■ LNB short-circuit dynamic protection
■ +/- 4 kV ESD tolerant on output power pins
LNBH25L
QFN24 (4 x 4 mm)
the LNB down-converter in the antenna dish or to
the multi-switch box. In this application field, it
offers a complete solution with extremely low
component count and low power dissipation
together with a simple design and I²C standard
interfacing.
Applications
■ STB satellite receivers
■ TV satellite receivers
■ PC card satellite receivers
Description
Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the
LNBH25L is a monolithic voltage regulator and
interface IC, assembled in QFN24 (4x4)
specifically designed to provide the 13/18 V
power supply and the 22 kHz tone signalling to
Table 1. Device summary
Order code Package Packaging
LNBH25LPQR QFN24 (4 x 4) Tape and reel
February 2012 Doc ID 022634 Rev 2 1/28
www.st.com
28
Contents LNBH25L
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4
2.3 Data encoding by external DiSEqC™ envelope control
through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7 Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6
2.9 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.10 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7
2.11 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/28 Doc ID 022634 Rev 2
LNBH25L Contents
7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID 022634 Rev 2 3/28
Block diagram LNBH25L
1 Block diagram
Figure 1. Block diagram
ADDR
DSQIN
SDASCL
I2C Digital core
DAC
Drop control
Tone ctrl
Diagnostics
Protections
LX
PWM CTRL
Isense
PGND
VUP
ISEL
Voltage
reference
Current
Limit
selection
VCCGND BYP
Linear
Regulator
Gate ctrl
VOUT
AM10460v1
4/28 Doc ID 022634 Rev 2
LNBH25L Application information
2 Application information
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates the voltages (V
13 V / 18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum
dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at
V
UP
- V
= 1 V typ.). The IC is also provided with an undervoltage lockout circuit that
OUT
disables the whole circuit when the supplied V
typically). The step-up converter soft-start function reduces the inrush current during
startup. The SS time is internally fixed at 4ms typ. to switch from 0 to 13 V and 6 ms typ. to
switch from 0 to 18 V.
2.1 DiSEqC data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards,
and can be activated in 3 different ways:
1. by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL
compatible). In this case the I²C tone control bits must be set: EXTM = TEN = 1.
2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this
case the I²C tone control bits must be set: EXTM=0 and TEN=1.
3. through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this
case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.
) that let the integrated LDO post-regulator (generating the
UP
drops below a fixed threshold (4.7 V
CC
2.2 Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility an external tone signal can be input to the DSQIN pin by
setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the V
LNBH25L integrated tone generator.
The output tone waveforms are internally controlled by the LNBH25L tone generator in
terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN
pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible
22 kHz signal is required for the proper control of the DSQIN pin function. Before sending
the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As
soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the
LNBH25L activates the 22 kHz tone on the V
output with about 1 µs delay from TTL
OUT
signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN
has expired (refer to
Figure 2
).
Figure 2. Tone enable and disable timing (using external waveform)
DSQIN
Tone
~ 1 µs
Output
~ 60 µs
OUT
AM10426v1
pin, by using the
Doc ID 022634 Rev 2 5/28
Application information LNBH25L
2.3 Data encoding by external DiSEqC™ envelope control through the DSQIN pin
If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz
generator activated during the tone transmission by connecting the DiSEqC envelope
source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM = 0 and
TEN = 1. In this way, the internal 22 kHz signal is superimposed to the V
generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH,
the internal control circuit activates the 22 kHz tone output.
DC voltage to
OUT
The 22 kHz tone on the V
pin is activated with about 6 µs delay from the DSQIN TTL
OUT
signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22
kHz TTL signal on DSQIN has expired (refer to
Figure 3. Tone enable and disable timing (using envelope signal)
DSQIN
Tone
Output
~ 6 µs
2.4 Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
the ISEL pin. The resistor value defines the output current limit by the equation:
Equation 1
13915
=
MAX
.)typ(I
RSEL
111.1
Figure 3
).
15 µs ~ 60 µs
AM10427v1
where RSEL is the resistor connected between ISEL and GND expressed in kΩ and
I
(typ.) is the typical current limit threshold expressed in mA. I
MAX
750 mA.
2.5 Output voltage selection
The linear regulator output voltage level can be easily programmed in order to accomplish
application specific requirements, using 4 bits of an internal DATA1 register (see
and
Ta bl e 1 3
6/28 Doc ID 022634 Rev 2
for exact programmable values). Register writing is accessible via the I²C bus.
can be set up to
MAX
Section 7.3
LNBH25L Application information
2.6 Diagnostic and protection functions
The LNBH25L has 3 diagnostic internal functions provided via the I²C bus, by reading 3 bits
on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that
is no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature
and overload protection status (OTF and OLF). One bit is dedicated to the input voltage
power not good function (PNG). Once the OLF (or OTF or PNG) bit has been activated (set
to “1”), it is latched to “1” until the relevant cause is removed and a new register reading
operation is done.
2.7 Surge protection and TVS diodes
The LNBH25L device is directly connected to the antenna cable in a set-top box.
Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing
damage to the attached devices. Surge pulses occur due to direct or indirect lightning
strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields
causing high voltage or current transients. Transient voltage suppressor (TVS) devices are
usually used, as shown in the following schematic, to protect the STB output circuits where
the LNBH25L and other devices are electrically connected to the antenna cable.
Figure 4. Surge protection circuit
For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically
designed by ST. The selection of the LNBTVS diode should be made based on the
maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS
datasheet for further details).
2.8 Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH25L is automatically reset at power-on. As long as the
V
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does
CC
not respond to any I²C command and all data register bits are initialized to zeroes, therefore
keeping the power blocks disabled. Once the V
becomes operative and the data registers can be configured by the main microprocessor.
rises above 4.8 V typ. the I²C interface
CC
2.9 PNG: input voltage minimum detection
When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds,
the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to
Doc ID 022634 Rev 2 7/28
Ta bl e 1 2
for threshold details.
Application information LNBH25L
2.10 OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set to LOW, the
overcurrent protection circuit works dynamically: as soon as an overload is detected, the
output current is provided for a T
for a T
time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system
OFF
register is set to “1”. After this time has elapsed, the output is resumed for a time T
end of T
and T
, if the overload is still detected, the protection circuit cycles again through T
ON
. At the end of a full TON in which no overload is detected, normal operation is
ON
resumed and the OLF diagnostic bit is reset to LOW after a register reading is done. Typical
T
ON
+ T
time is 990 ms and an internal timer determines it. This dynamic operation can
OFF
greatly reduce the power dissipation in a short-circuit condition, still ensuring excellent
power-on startup in most conditions. However, there may be some cases in which a highly
capacitive load on the output can cause a difficult startup when the dynamic protection is
chosen. This can be solved by initiating any power startup in static mode (PCL=1) and then
switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the
output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” when the current
clamp limit is reached and returns LOW when the overload condition is cleared and a
register reading is done.
time of 90 ms, after which the output is set in shutdown
ON
. At the
ON
OFF
After the overload condition is removed, normal operation can be resumed in two ways,
according to the OLR I²C bit on the DATA4 register.
If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
enable the output stage, the VSEL bits must be set again by the microprocessor, and the
OLF bit is reset to “0” after a register reading operation.
If OLR=0, output is automatically re-enabled as soon as the overload condition is removed,
and the OLF bit is reset to “0” after a register reading operation.
2.11 OTF: thermal protection and diagnostic
The LNBH25L is also protected against overheating: when the junction temperature
exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off, the
diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition
is removed, normal operation can be resumed in two ways, according to the THERM I²C bit
on the DATA4 register.
If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
enable the output stage, the VSEL bits must be set again by the microprocessor, while the
OTF bit is reset to “0” after a register reading operation.
If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is
removed, while the OTF bit is reset to “0” after a register reading operation.
pin) is disabled. To re-
OUT
pin) is disabled. To re-
OUT
8/28 Doc ID 022634 Rev 2
LNBH25L Pin configuration
3 Pin configuration
Figure 5. Pin connections (top view)
192021222324
GNDNC DSQIN
NC
1
GND
2
LX
3
VUP
VOUT
GND
LNBH25L
PGND
4
5
NC
ADDR NC
6
SDA
Table 2. Pin description
SCL
7 8 9 121110
ISEL
Pin n° Symbol Name Pin function
3 LX N-MOS drain Integrated N-channel Power MOSFET drain.
4 P-GND Power ground
DC-DC converter power ground. To be connected directly to the
Epad.
NC
NCNC
GND
VCC
VBYP
GND
NC
18
17
16
15
14
13
AM10461v1
6 ADDR Address setting
Two I²C bus addresses available by setting the address pin level
voltage. See
Ta b l e 1 5
.
7 SCL Serial clock Clock from I²C bus.
8 SDA Serial data Bi-directional data from/to the I²C bus.
9 ISEL Current selection
2,15, 18, 19,
23
GND Analog ground Analog circuits ground. To be connected directly to the Epad.
The resistor “RSEL” connected between ISEL and GND defines the
linear regulator current limit threshold. Refer to
Needed for internal pre-regulator filtering. The BYP pin is intended
16 BYP Bypass capacitor
only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent
damage to the device.
17 V
20 V
CC
OUT
Supply input 8 to 16 V IC DC-DC power supply.
LNB output port
Output of the integrated very low drop linear regulator. See
for voltage selection and description.
Input of the linear post-regulator. The voltage on this pin is
21 V
UP
Step-up voltage
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
Doc ID 022634 Rev 2 9/28
Section 2.4
.
Ta bl e 1 3
Pin configuration LNBH25L
Table 2. Pin description (continued)
Pin n° Symbol Name Pin function
It can be used as DiSEqC envelope input or external 22 kHz TTL
DSQIN for
DiSEqC envelope
22 DSQIN
Epad Epad Exposed pad
input
or
External 22 kHz
TTL input
input depending on the EXTM I²C bit setting as follows:
EXTM=0, TEN=1: it accepts the DiSEqC envelope code from the
main microcontroller. The LNBH25L uses this code to modulate the
internally generated 22 kHz carrier.
EXTM=TEN=1: it accepts external 22 kHz logic signals which
activate the 22 kHz tone output (refer to
Pull up high if the tone output is activated only by the TEN I²C bit.
To be connected with power grounds and to the ground layer
through vias to dissipate the heat.
Section 2.3
).
1, 5, 10, 11,
12, 13, 14, 24
N.C.
Not internally
connected
Not internally connected pins. These pins can be connected to GND
to improve thermal performances.
10/28 Doc ID 022634 Rev 2
LNBH25L Maximum ratings
4 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
V
I
V
CC
UP
OUT
OUT
V
DC power supply input voltage pins -0.3 to 20 V
DC input voltage -0.3 to 40 V
Output current Internally limited mA
DC output pin voltage -0.3 to 40 V
Logic input pins voltage (SDA, SCL, DSQIN, ADDR pins) -0.3 to 7 V
I
LX LX input voltage -0.3 to 30 V
V
BYP
Internal reference pin voltage -0.3 to 4.6 V
ISEL Current selection pin voltage -0.3 to 3.5 V
T
STG
T
ESD
Storage temperature range -50 to 150 °C
Operating junction temperature range -25 to 125 °C
J
ESD rating with human body model (HBM) all pins, unless power output
pins
2kV
ESD rating with human body model (HBM) for power output pins 4
Table 4. Thermal data
Symbol Parameter Value Unit
thJC Thermal resistance junction-case 2 °C/W
R
thJA
R
Thermal resistance junction-ambient with device soldered on 2s2p 4layer PCB provided with thermal vias below exposed pad.
40 °C/W
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to the network ground terminal.
Doc ID 022634 Rev 2 11/28
Typical application circuits LNBH25L
5 Typical application circuits
Figure 6. DiSEqC 1.x application circuit
D2
21
Vup
Vin
12V
DiSEqC
22KHz TTL
DiSEqC
Envelope TTL
or
D1
L1
C1
C2
R1 (RSEL)
C3
C4
I2C Bus
3
LX
17
Vcc
DSQIN
22
6
ADDR
8
SDA
{
7
SCL
9
ISEL
LNBH25L
P-GND A-GND
15
4
Table 5. Typical application circuit bill of material
Component Notes
Vout
Byp
to LNB
20
C5
D3
16
C7
AM10462v 1
R1 (RSEL) SMD resistor. Refer to
Ta b l e 1 2
and ISEL pin description in
C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable.
C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.
C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.
C4, C7 220 nF ceramic capacitors.
D1 STPS130A or similar schottky diode.
D3
BAT54, BAT43, 1N5818, or any low power schottky diode with I
> 25 V, VF < 0.5 V. To be placed as close as possible to V
V
RRM
D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier.
L1 10 µH inductor with I
sat
> I
peak
where I
12/28 Doc ID 022634 Rev 2
Ta bl e 2
(AV) > 0.2 A,
F
pin.
OUT
is the boost converter peak current.
peak
LNBH25L I²C bus interface
6 I²C bus interface
Data transmission from the main microprocessor to the LNBH25L and vice versa takes
place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
6.1 Data validity
As shown in
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
Figure 7
, the data on the SDA line must be stable during the high semi-period
6.2 Start and stop condition
As shown in
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
Figure 8
, a start condition is a HIGH to LOW transition of the SDA line while
6.3 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4 Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA
line is stable LOW during this clock pulse. The peripheral which has been addressed must
generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH25L does not
generate an acknowledge if the V
V typ.).
Figure 9
CC
). The peripheral (LNBH25L) that acknowledges
supply is below the undervoltage lockout threshold (4.7
6.5 Transmission without acknowledge
To avoid detection of the LNBH25L acknowledges, the microprocessor can use a simpler
transmission: it simply waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach is of course less protected from misworking and
decreases the noise immunity.
Doc ID 022634 Rev 2 13/28
I²C bus interface LNBH25L
Figure 7. Data validity on the I²C bus
Figure 8. Timing diagram of I²C bus
Figure 9. Acknowledge on the I²C bus
14/28 Doc ID 022634 Rev 2
LNBH25L I²C interface protocol
7 I²C interface protocol
7.1 Write mode transmission
The LNBH25L interface protocol is made up of:
● a start condition (S)
● a chip address byte with the LSB bit R/W = 0
● a register address (internal address of the first register to be accessed)
● a sequence of data (byte to write in the addressed internal register + acknowledge)
● the following bytes, if any, to be written in successive internal registers
● a stop condition (P). The transfer lasts until a stop bit is encountered
● the LNBH25L, as slave, acknowledges every byte transfer.
Figure 10. Example of writing procedure starting with first data address 0x2
CHIP ADDRESS
MSB
S 000100X
DATA 1
Add=0x2
MSB LSB
N/A
N/A
N/A
N/A
VSEL4
LSB
VSEL3
REGISTER ADDRESS
MSB
00000XXX
ACK
R/W = 0
MSB LSB
N/A
N/A
VSEL2
VSEL1
ACK
N/A
DATA 2
Add=0x3
N/A
N/A
LSB
N/A
EXTM
ACK
DATA 3
Add=0x 4
MSB LSB
N/A
N/A
TEN
ACK
N/A
N/A
N/A
PCL
MSB LSB
N/A
ACK
N/A
N/A
DATA 4
Add=0x5
N/A
THERM
N/A
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see
select the REGISTER ADDRESS (see
Ta bl e 6
to
Ta bl e 1 1
Ta bl e 1 5
).
for pin selection) and to
OLR
N/A
N/A
N/A
(a)
P
ACK
AM10463v1
a. The writing procedure can start from any register address by simply setting the X values in the register address
byte (after the chip address). It can be also stopped from the master by sending a stop condition after any
acknowledge bit.
Doc ID 022634 Rev 2 15/28
I²C interface protocol LNBH25L
7.2 Read mode transmission
In read mode the bytes sequence must be as follows:
● a start condition (S)
● a chip address byte with the LSB bit R/W=0
● the register address byte of the internal first register to be accessed
● a stop condition (P)
● a new master transmission with the chip address byte and the LSB bit R/W=1
● after the acknowledge the LNBH25L starts to send the addressed register content. As
long as the master keeps the acknowledge LOW, the LNBH25L transmits the next
address register byte content.
● the transmission is terminated when the master sets the acknowledge HIGH with a
following stop bit.
Figure 11. Example of reading procedure starting with first status address 0X0
CHIP ADDRESS
MSB
S 000100X
DATA 1
Add=0x2
MSB LSB
N/A
N/A
N/A
N/A
VSEL4
VSEL3
LSB
REGISTER ADDRESS
MSB
00000XXX
ACK
R/W = 0
STATUS 1
Add=0x 0
MSB LSB
N/A
N/A
OTF
PNG
MSB LSB
N/A
N/A
VSEL2
VSEL1
ACK
N/A
N/A
N/A
DATA 2
Add= 0x3
N/A
N/A
LSB
ACK
MSB LSB
N/A
OLF
N/A
EXTM
ACK
TEN
N/A
ACK
CHIP ADDRESS
MSB
P
S000100X
STATUS 2
Add=0x1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DATA 3
Add=0x 4
MSB LSB
N/A
N/A
N/A
N/A
N/A
N/A
PCL
LSB
R/W = 1
ACK
DATA 4
Add=0x5
MSB LSB
N/A
N/A
ACK
THERM
N/A
ACK
N/A
OLR
N/A
N/A
N/A
P
ACK
AM10464v1
(b)
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see
select the REGISTER ADDRESS (see
b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X
values in the register address byte (after the first chip address in the above figure). It can be also stopped from
the master by sending a stop condition after any acknowledge bit.
16/28 Doc ID 022634 Rev 2
Ta bl e 6
to
Ta bl e 1 1
Ta bl e 1 5
).
for pin selection) and to
LNBH25L I²C interface protocol
7.3 Data registers
The data 1..4 registers can be addressed both in write and read mode. In read mode they
return the last writing byte status received in the previous write transmission.
The following tables provide the register address values of data 1..4 and a function
description of each bit.
Table 6. Data 1 (read/write register. Register address = 0X2)
BIT Name Value Description
Bit 0
(LSB)
Bit 1 VSEL2 0/1
Bit 2 VSEL3 0/1
Bit 3 VSEL4 0/1
Bit 4 N/A 0 Reserved. Keep to “0”
Bit 5 N/A 0 Reserved. Keep to “0”
Bit 6 N/A 0 Reserved. Keep to “0”
Bit 7
(MSB)
VSEL1 0/1
Output voltage selection bits. (Refer to
N/A 0 Reserved. Keep to “0”
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 7. Data 2 (read/write register. Register address = 0X3)
BIT Name Value Description
Bit 0
(LSB)
Bit 1 N/A 0 Reserved. Keep to “0”
Bit 2 EXTM
1 22 kHz tone enabled. Tone output controlled by the DSQIN pin
TEN
0 22 kHz tone output disabled
1 DSQIN input pin is set to receive external 22 kHz TTL signal source
0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal
Ta bl e 1 3
)
Bit 3 N/A 0 Reserved. Keep to “0”
Bit 4 N/A 0 Reserved. Keep to “0”
Bit 5 N/A 0 Reserved. Keep to “0”
Bit 6 N/A 0 Reserved. Keep to “0”
Bit 7
(MSB)
N/A 0 Reserved. Keep to “0”
N/A = Reserved bit.
All bits reset to “0” at power-on.
Doc ID 022634 Rev 2 17/28
I²C interface protocol LNBH25L
Table 8. Data 3 (read/write register. Register address = 0X4)
BIT Name Value Description
Bit 0
(LSB)
N/A 0 Reserved. Keep to “0”
Bit 1 N/A 0 Reserved. Keep to “0”
1 Pulsed (Dynamic) LNB output current limiting is deactivated
Bit 2 PCL
0 Pulsed (Dynamic) LNB output current limiting is activated
Bit 3 N/A 0 Reserved. Keep to “0”
Bit 4 N/A 0 Reserved. Keep to “0”
Bit 5 N/A 0 Reserved. Keep to “0”
Bit 6 N/A 0 Reserved. Keep to “0”
Bit 7
(MSB)
N/A 0 Reserved. Keep to “0”
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 9. Data 4 (read/write register. Register address = 0X5)
BIT Name Value Description
Bit 0
(LSB)
N/A 0 Reserved. Keep to “0”
Bit 1 N/A 0 Reserved. Keep to “0”
Bit 2 N/A 0 Reserved. Keep to “0”
In case of overload protection activation (OLF=1), all VSEL 1..4 bits are reset to
1
“0” and LNB output (V
pin) is disabled. The VSEL bits must be set again by the
OUT
master after the overcurrent condition is removed (OLF=0).
Bit 3 OLR
In case of overload protection activation (OLF=1) the LNB output (V
automatically enabled as soon as the overload condition is removed (OLF=0) with
0
the previous VSEL bits setting.
Bit 4 N/A 0 Reserved. Keep to “0”
Bit 5 N/A 0 Reserved. Keep to “0”
If thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and
1
LNB output (V
pin) is disabled. The VSEL bits must be set again by the master
OUT
after the overtemperature condition is removed (OTF=0).
Bit 6 THERM
In case of thermal protection activation (OTF=1) the LNB output (V
0
automatically enabled as soon as the overtemperature condition is removed
(OTF=0) with the previous VSEL bits setting.
Bit 7
(MSB)
N/A 0 Reserved. Keep to “0”
OUT
OUT
pin) is
pin) is
N/A = Reserved bit.
All bits reset to “0” at power-on.
18/28 Doc ID 022634 Rev 2
LNBH25L I²C interface protocol
7.4 Status registers
The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic
functions described in the following tables.
Table 10. STATUS 1 (Read register. Register address = 0X0)
BIT Name Value Description
V
pin overload protection has been triggered (I
Bit 0
(LSB)
Bit 1 N/A - Reserved
Bit 2 N/A - Reserved
Bit 3 N/A - Reserved
Bit 4 N/A - Reserved
Bit 5 N/A - Reserved
OLF
1
0 No overload protection has been triggered to the V
OUT
the overload operation settings (PCL bit).
OUT
OUT
> I
MAX
pin (I
). Refer to
< I
OUT
MAX
Ta bl e 8
).
for
Junction overtemperature is detected, T
Bit 6 OTF
Bit 7
(MSB)
PNG
1
setting in
Junction overtemperature not detected, TJ < 135 °C. TJ is below thermal
0
protection threshold.
1 Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to
0 Input voltage (VCC pin) higher than LPD thresholds. Refer to
Ta b l e 9
.
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 11. STATUS 2 (Read register. Register address = 0X1)
BIT Name Value Description
Bit 0
(LSB)
Bit 1 N/A - Reserved
Bit 2 N/A - Reserved
Bit 3 N/A - Reserved
Bit 4 N/A - Reserved
Bit 5 N/A - Reserved
N/A - Reserved
> 150 °C. See also the THERM bit
J
Ta b l e 1 2
Ta bl e 1 2
.
.
Bit 6 N/A - Reserved
Bit 7
(MSB)
N/A - Reserved
N/A = Reserved bit.
All bits reset to “0” at power-on.
Doc ID 022634 Rev 2 19/28
Electrical characteristics LNBH25L
8 Electrical characteristics
Refer to
RSEL = 16.2 kΩ, DSQIN = LOW, V
values are referred to T
for I²C access to the system register (
Table 12. Electrical characteristics
.
Section 5
, TJ from 0 to 85 °C, all data 1..4 register bits set to 0 unless VSEL1 = 1,
= 25 °C. V
J
= 12 V, I
IN
= V
OUT
Section 6
OUT
= 50 mA, unless otherwise stated. Typical
OUT
pin voltage. See software description section
and
Section 7
).
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IN
I
IN
Supply voltage
Supply current
(1)
81216V
=0 mA 6 mA
I
OUT
22 kHz tone enabled (TEN=1,
DSQIN=High), I
OUT
=0 mA
10
VSEL1=VSEL2=VSEL3=VSEL4=0 1
V
V
V
I
OUT
OUT
OUT
MAX
I
SC
Output voltage total accuracy Valid at any V
Line regulation VIN=8 to 16 V 40 mV
Load regulation I
Output current limiting
thresholds
Output short-circuit current RSEL= 16.2 kΩ 350 mA
SS Soft-start time V
SS Soft-start time V
T13-18 Soft transition rise time V
T18-13 Soft transition fall time V
T
T
OFF
ON
Dynamic overload protection
OFF time
Dynamic overload protection
ON time
from 50 to 500 mA 75 100
OUT
RSEL = 16.2 kΩ
RSEL = 22 kΩ
from 0 to 13 V 4 ms
OUT
from 0 to 18 V 6 ms
OUT
from 13V to 18 V 1.5 ms
OUT
from 18V to 13 V 1.5 ms
OUT
PCL=0, output shorted 900
PCL=0, output shorted T
selected level -3.5 +3.5 %
OUT
500 750
350 550
/10
OFF
mA
ms
DSQIN=High, EXTM=0, TEN=1
A
F
D
Eff
F
UVLO
TONE
TONE
TONE
t
, t
r
DC/DC
SW
V
LP
Tone amplitude
from 0 to 500 mA
I
OUT
from 0 to 750 nF
C
BUS
Tone frequency
Tone duty cycle 43 50 57 %
Tone rise or fall time
f
(2)
DC-DC converter efficiency I
DSQIN=High, EXTM=0, TEN=1
=500mA 93 %
OUT
DC-DC converter switching
frequency
Undervoltage lockout
thresholds
Low power diagnostic (LPD)
thresholds
UVLO threshold rising 4.8
UVLO threshold falling 4.7
V
threshold rising 7.2
LP
VLP threshold falling 6.7
20/28 Doc ID 022634 Rev 2
0.55 0.675 0.8 V
PP
20 22 24 kHz
5815µs
440 kHz
V
V
LNBH25L Electrical characteristics
Table 12. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
IH
I
IH
I
OBK
I
SINK
I
SINK_TIME-
OUT
I
REV
T
SHDN
ΔT
SHDN
1. In applications where (VCC-V
account in the application thermal management design.
2. Guaranteed by design.
Table 13. Output voltage selection table (Data1 register, write mode)
VSEL4 VSEL3 VSEL2 VSEL1
0000 0.000 V
DSQIN, pin logic low 0.8 V
IL
DSQIN, pin logic high 2 V
DSQIN, pin input current VIH=5 V 15 µA
Output backward current All VSELx=0, V
Output low-side sink current V
Low-side sink current timeout V
Max. reverse current
forced at V
OUT
forced at V
OUT
V
forced at V
OUT
after I
SINK_TIME-OUT
=30 V -3 -6mA
OBK
OUT_nom
OUT_nom
OUT_nom
+0.1 V 70 mA
+0.1 V 10 ms
+0.1 V,
is elapsed
Thermal shutdown threshold 150 °C
Thermal shutdown hysteresis 15 °C
) >1.3 V, the increased power dissipation inside the integrated LDO must be taken into
OUT
V
V
OUT
min.
pin
OUT
voltage
V
OUT
max.
disabled. LNBH25L set in standby
OUT
000112.54513.00013.455
2mA
Function
001012.86713.33313.800
001113.18813.66714.145
010013.5114.00014.490
100017.51518.15018.785
100117.83618.48319.130
101018.15818.81719.475
101118.4819.15019.820
Doc ID 022634 Rev 2 21/28
Electrical characteristics LNBH25L
TJ from 0 to 85 °C, VI = 12 V.
Table 14. I²C electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
V
IH
I
IN
V
OL
F
MAX
1. Guaranteed by design.
Low level input voltage SDA, SCL 0.8 V
High level input voltage SDA, SCL 2 V
Input current SDA, SCL, V
Low level output voltage
(1)
SDA (open drain), IOL = 6 mA 0.6 V
= 0.4 to 4.5 V -10 10 µA
IN
Maximum clock frequency SCL 400 kHz
TJ from 0 to 85 °C, VI = 12 V.
Table 15. Address pin characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
V
ADDR-1
V
ADDR-2
“0001000(R/W)” address pin
voltage range
“0001001(R/W)” address pin
voltage range
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
00.8V
25V
22/28 Doc ID 022634 Rev 2
LNBH25L Package mechanical data
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK
specifications, grade definitions and product status are available at:
packages, depending on their level of environmental compliance. ECOPACK
www.st.com
. ECOPACK
is an ST trademark.
Table 16. QFN24L (4 x 4 mm) mechanical data
(mm)
Dim.
Min. Typ. Max.
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 3.90 4.00 4.10
D2 2.55 2.70 2.80
E 3.90 4.00 4.10
E2 2.55 2.70 2.80
e 0.45 0.50 0.55
L 0.25 0.35 0.45
Doc ID 022634 Rev 2 23/28
Package mechanical data LNBH25L
Figure 12. QFN24L (4 x 4 mm) package dimensions
24/28 Doc ID 022634 Rev 2
7596209_D
LNBH25L Package mechanical data
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 99 101 3.898 3.976
T 14.4 0.567
Ao 4.35 0.171
Bo 4.35 0.171
Ko 1.1 0.043
Po 4 0.157
P 8 0.315
Doc ID 022634 Rev 2 25/28
Package mechanical data LNBH25L
Figure 13. QFN24L (4 x 4) footprint recommended data (mm.)
26/28 Doc ID 022634 Rev 2
LNBH25L Revision history
10 Revision history
Table 17. Document revision history
Date Revision Changes
09-Jan-2012 1 Initial release.
15-Feb-2012 2 Modified: D1 and D3
Table 5 on page 12
.
Doc ID 022634 Rev 2 27/28
LNBH25L
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28/28 Doc ID 022634 Rev 2
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