ST LNBH25L User Manual
LNB supply and control IC with step-up and I²C interface
Features
■ Complete interface between LNB and I²C bus
■ Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @
0.5 A)
■ Selectable output current limit by external
resistor
■ Compliant with main satellite receiver output
voltage specifications
■ Accurate built-in 22 kHz tone generator suits
widely accepted standards
■ 22 kHz tone waveform integrity guaranteed
also at no load condition
■ Low-drop post regulator and high efficiency
step-up PWM with integrated power N-MOS
allowing low power losses
■ Overload and overtemperature internal
protection with I²C diagnostic bits
■ LNB short-circuit dynamic protection
■ +/- 4 kV ESD tolerant on output power pins
LNBH25L
QFN24 (4 x 4 mm)
the LNB down-converter in the antenna dish or to
the multi-switch box. In this application field, it
offers a complete solution with extremely low
component count and low power dissipation
together with a simple design and I²C standard
interfacing.
Applications
■ STB satellite receivers
■ TV satellite receivers
■ PC card satellite receivers
Description
Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the
LNBH25L is a monolithic voltage regulator and
interface IC, assembled in QFN24 (4x4)
specifically designed to provide the 13/18 V
power supply and the 22 kHz tone signalling to
Table 1. Device summary
Order code Package Packaging
LNBH25LPQR QFN24 (4 x 4) Tape and reel
February 2012 Doc ID 022634 Rev 2 1/28
www.st.com
28
Contents LNBH25L
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4
2.3 Data encoding by external DiSEqC™ envelope control
through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7 Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6
2.9 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.10 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7
2.11 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/28 Doc ID 022634 Rev 2
LNBH25L Contents
7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID 022634 Rev 2 3/28
Block diagram LNBH25L
1 Block diagram
Figure 1. Block diagram
ADDR
DSQIN
SDASCL
I2C Digital core
DAC
Drop control
Tone ctrl
Diagnostics
Protections
LX
PWM CTRL
Isense
PGND
VUP
ISEL
Voltage
reference
Current
Limit
selection
VCCGND BYP
Linear
Regulator
Gate ctrl
VOUT
AM10460v1
4/28 Doc ID 022634 Rev 2
LNBH25L Application information
2 Application information
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates the voltages (V
13 V / 18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum
dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at
V
UP
- V
= 1 V typ.). The IC is also provided with an undervoltage lockout circuit that
OUT
disables the whole circuit when the supplied V
typically). The step-up converter soft-start function reduces the inrush current during
startup. The SS time is internally fixed at 4ms typ. to switch from 0 to 13 V and 6 ms typ. to
switch from 0 to 18 V.
2.1 DiSEqC data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards,
and can be activated in 3 different ways:
1. by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL
compatible). In this case the I²C tone control bits must be set: EXTM = TEN = 1.
2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this
case the I²C tone control bits must be set: EXTM=0 and TEN=1.
3. through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this
case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.
) that let the integrated LDO post-regulator (generating the
UP
drops below a fixed threshold (4.7 V
CC
2.2 Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility an external tone signal can be input to the DSQIN pin by
setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the V
LNBH25L integrated tone generator.
The output tone waveforms are internally controlled by the LNBH25L tone generator in
terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN
pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible
22 kHz signal is required for the proper control of the DSQIN pin function. Before sending
the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As
soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the
LNBH25L activates the 22 kHz tone on the V
output with about 1 µs delay from TTL
OUT
signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN
has expired (refer to
Figure 2
).
Figure 2. Tone enable and disable timing (using external waveform)
DSQIN
Tone
~ 1 µs
Output
~ 60 µs
OUT
AM10426v1
pin, by using the
Doc ID 022634 Rev 2 5/28
Application information LNBH25L
2.3 Data encoding by external DiSEqC™ envelope control through the DSQIN pin
If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz
generator activated during the tone transmission by connecting the DiSEqC envelope
source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM = 0 and
TEN = 1. In this way, the internal 22 kHz signal is superimposed to the V
generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH,
the internal control circuit activates the 22 kHz tone output.
DC voltage to
OUT
The 22 kHz tone on the V
pin is activated with about 6 µs delay from the DSQIN TTL
OUT
signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22
kHz TTL signal on DSQIN has expired (refer to
Figure 3. Tone enable and disable timing (using envelope signal)
DSQIN
Tone
Output
~ 6 µs
2.4 Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
the ISEL pin. The resistor value defines the output current limit by the equation:
Equation 1
13915
=
MAX
.)typ(I
RSEL
111.1
Figure 3
).
15 µs ~ 60 µs
AM10427v1
where RSEL is the resistor connected between ISEL and GND expressed in kΩ and
I
(typ.) is the typical current limit threshold expressed in mA. I
MAX
750 mA.
2.5 Output voltage selection
The linear regulator output voltage level can be easily programmed in order to accomplish
application specific requirements, using 4 bits of an internal DATA1 register (see
and
Ta bl e 1 3
6/28 Doc ID 022634 Rev 2
for exact programmable values). Register writing is accessible via the I²C bus.
can be set up to
MAX
Section 7.3
LNBH25L Application information
2.6 Diagnostic and protection functions
The LNBH25L has 3 diagnostic internal functions provided via the I²C bus, by reading 3 bits
on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that
is no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature
and overload protection status (OTF and OLF). One bit is dedicated to the input voltage
power not good function (PNG). Once the OLF (or OTF or PNG) bit has been activated (set
to “1”), it is latched to “1” until the relevant cause is removed and a new register reading
operation is done.
2.7 Surge protection and TVS diodes
The LNBH25L device is directly connected to the antenna cable in a set-top box.
Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing
damage to the attached devices. Surge pulses occur due to direct or indirect lightning
strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields
causing high voltage or current transients. Transient voltage suppressor (TVS) devices are
usually used, as shown in the following schematic, to protect the STB output circuits where
the LNBH25L and other devices are electrically connected to the antenna cable.
Figure 4. Surge protection circuit
For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically
designed by ST. The selection of the LNBTVS diode should be made based on the
maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS
datasheet for further details).
2.8 Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH25L is automatically reset at power-on. As long as the
V
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does
CC
not respond to any I²C command and all data register bits are initialized to zeroes, therefore
keeping the power blocks disabled. Once the V
becomes operative and the data registers can be configured by the main microprocessor.
rises above 4.8 V typ. the I²C interface
CC
2.9 PNG: input voltage minimum detection
When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds,
the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to
Doc ID 022634 Rev 2 7/28
Ta bl e 1 2
for threshold details.
Application information LNBH25L
2.10 OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set to LOW, the
overcurrent protection circuit works dynamically: as soon as an overload is detected, the
output current is provided for a T
for a T
time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system
OFF
register is set to “1”. After this time has elapsed, the output is resumed for a time T
end of T
and T
, if the overload is still detected, the protection circuit cycles again through T
ON
. At the end of a full TON in which no overload is detected, normal operation is
ON
resumed and the OLF diagnostic bit is reset to LOW after a register reading is done. Typical
T
ON
+ T
time is 990 ms and an internal timer determines it. This dynamic operation can
OFF
greatly reduce the power dissipation in a short-circuit condition, still ensuring excellent
power-on startup in most conditions. However, there may be some cases in which a highly
capacitive load on the output can cause a difficult startup when the dynamic protection is
chosen. This can be solved by initiating any power startup in static mode (PCL=1) and then
switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the
output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” when the current
clamp limit is reached and returns LOW when the overload condition is cleared and a
register reading is done.
time of 90 ms, after which the output is set in shutdown
ON
. At the
ON
OFF
After the overload condition is removed, normal operation can be resumed in two ways,
according to the OLR I²C bit on the DATA4 register.
If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
enable the output stage, the VSEL bits must be set again by the microprocessor, and the
OLF bit is reset to “0” after a register reading operation.
If OLR=0, output is automatically re-enabled as soon as the overload condition is removed,
and the OLF bit is reset to “0” after a register reading operation.
2.11 OTF: thermal protection and diagnostic
The LNBH25L is also protected against overheating: when the junction temperature
exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off, the
diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition
is removed, normal operation can be resumed in two ways, according to the THERM I²C bit
on the DATA4 register.
If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
enable the output stage, the VSEL bits must be set again by the microprocessor, while the
OTF bit is reset to “0” after a register reading operation.
If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is
removed, while the OTF bit is reset to “0” after a register reading operation.
pin) is disabled. To re-
OUT
pin) is disabled. To re-
OUT
8/28 Doc ID 022634 Rev 2
LNBH25L Pin configuration
3 Pin configuration
Figure 5. Pin connections (top view)
192021222324
GNDNC DSQIN
NC
1
GND
2
LX
3
VUP
VOUT
GND
LNBH25L
PGND
4
5
NC
ADDR NC
6
SDA
Table 2. Pin description
SCL
7 8 9 121110
ISEL
Pin n° Symbol Name Pin function
3 LX N-MOS drain Integrated N-channel Power MOSFET drain.
4 P-GND Power ground
DC-DC converter power ground. To be connected directly to the
Epad.
NC
NCNC
GND
VCC
VBYP
GND
NC
18
17
16
15
14
13
AM10461v1
6 ADDR Address setting
Two I²C bus addresses available by setting the address pin level
voltage. See
Ta b l e 1 5
.
7 SCL Serial clock Clock from I²C bus.
8 SDA Serial data Bi-directional data from/to the I²C bus.
9 ISEL Current selection
2,15, 18, 19,
23
GND Analog ground Analog circuits ground. To be connected directly to the Epad.
The resistor “RSEL” connected between ISEL and GND defines the
linear regulator current limit threshold. Refer to
Needed for internal pre-regulator filtering. The BYP pin is intended
16 BYP Bypass capacitor
only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent
damage to the device.
17 V
20 V
CC
OUT
Supply input 8 to 16 V IC DC-DC power supply.
LNB output port
Output of the integrated very low drop linear regulator. See
for voltage selection and description.
Input of the linear post-regulator. The voltage on this pin is
21 V
UP
Step-up voltage
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
Doc ID 022634 Rev 2 9/28
Section 2.4
.
Ta bl e 1 3
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