ST LNBH24 User Manual

Dual LNB supply and control IC with step-up and I²C interface

Features

■ Complete interface between LNBS and I²C bus

■ Built-in DC-DC converter for single 12 V supply

operation and high efficiency (typ. 93%@0.5 A)

■ Selectable output current limit through external

resistor

■ Compliant with main satellite receivers output

voltage specification

■ New accurate built-in 22 kHz tone generator

meets widely accepted standards (patent pending)

■ Fast oscillator start-up facilitates DiSEqC™

encoding

■ Built-in 22 kHz tone detector supports bi-

directional DiSEqC™ 2.0

■ Very low-drop post regulator and high

efficiency step-up PWM with integrated power N-MOS allow low power losses

■ Two output pins suitable for bypassing the

output R-L filter and avoiding tone distortion (RL filter as per DiSEqC™ 2.0 specs, see typ. application circuits)

■ Overload and over-temperature internal

protections with I²C diagnostic bits

■ Output voltage and output current level

diagnostic feedback by I²C bits

■ LNB short circuit dynamic protection

■ +/- 4 kV ESD tolerant on output power pins

LNBH24

PowerSSO-36 (ePad)

designed to provide the 13/18 V power supply and the 22 kHz tone signalling for two independent LNB down-converters in the antenna dishes and/or multi-switch box. In this application field, it offers a dual tuner STBs with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.

Description

Intended for analog and digital dual satellite receivers/sat-TV, sat-PC cards, the LNBH24 is a monolithic voltage regulator and interface IC, assembled in PowerSSO-36 ePad, specifically

Table 1. Device summary

Order code Package Packaging

LNBH24PPR PowerSSO-36 (Exposed pad) Tape and reel

April 2009 Rev 3 1/30

www.st.com

Contents LNBH24

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 DiSEqC™ data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 DiSEqC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 DiSEqC™ 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 Data encoding through external tone generator (EXTM) . . . . . . . . . . . . . . 6

2.6 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.9 Output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.11 Minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.12 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.13 Over-current and short-circuit protection and diagnostic . . . . . . . . . . . . . . 8

2.14 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 LNBH24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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LNBH24 Contents

7.2 System register (SR, 1 Byte for each section A and B) . . . . . . . . . . . . . . 16

7.3 Transmitted data (I²C bus write mode) for each section A/B . . . . . . . . . . 16

7.4 Diagnostic received data (I²C read mode) for both sections A/B . . . . . . . 17

7.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.7 DiSEqC™ implementation for each section A/B . . . . . . . . . . . . . . . . . . . 18

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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Block diagram LNBH24

1 Block diagram

Figure 1. Block diagram

TEN-

EN-

VSEL-

TTX-

TEN-

SDA SCL

I²C Diagnostics

LNBH24

ADDR -

I²C interface

TEN-

EN-

VSEL-

VSELTTX-

TTX-

TEN-

Byp

Preregulator

Preregulator +U.V.lockout

+U.V.lockout +P.ON reset

+P.ON reset

ITEST-

Linear Post -reg

Linear Post -reg +Protections

+Protections +Diagnostics

+Diagnostics

Oscill.

VOUT-BControl

VCC-

ISEL -

22KHz Tone

22KHz Tone Amp. Diagn.

Amp. Diagn.

22KHz Tone

Det.

Freq. Det.

TTX-

PWM

Controller

TTX-

Rsense

VCC-

EN-

VSEL-

ISEL-

- -

TTX-

- -

LX-

Rsense

P-GND-

-- -

P-GND-

-- -

VoRX -

VCTRL -

VoTX -

TTX-

TTX-A-

TTX-

EXTM -

DSQIN -

DETIN -

DSQOUT

TTX-A-

22KHz Tone

22KHz Tone Amp. Diagn.

Amp. Diagn.

22KHz Tone

22KHz Tone Freq. Det.

Freq. Det.

PWM

Det.

Controller

EN-

VSEL-

ISEL-

Linear Post -reg

Linear Post -reg +Protections

+Protections +Diagnostics

+Diagnostics

ISEL -

ITEST-

22KHz

22KHz Oscill.

Oscill.

ADDR -

VOUT-AControl

ADDR -

ISEL -

TTX-

LX-

P-GND-

VoRX -

VCTRL -

VoTX -

EXTM -

DSQIN -

DETIN -

DSQOUT

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A-GND

LNBH24 Introduction

2 Introduction

The LNBH24 includes two completely independent sections. Except for the VCC and I²C inputs, each circuit can be separately controlled and have independent external components. The specification that follow should be considered equally for both sections (A/B).

2.1 Application information

This IC has a built-in DC-DC step-up converter which, from a single 8 V to 15 V source, generates the voltages (V dissipated power of 0.375 W Typ. @ 500 mA load (the linear post-regulator drop voltage is internally held at V

UP-VOUT

entire circuit when the supplied V

Note: In this document the V

output (V

oRX

pin).

2.2 DiSEqC™ data encoding and decoding

) that allow the linear post-regulator to work at a minimum

=0.75 V typ.). An under voltage lockout circuit will disable the

drops below a fixed threshold (6.7 V typically).

is intended as the voltage present at the linear post-regulator

OUT

The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance with the standards, and can be selected through I²C interface TTX bit (or TTX pin) and activated by a dedicated pin (DSQIN) which allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the 22 kHz presence is requested in continuous mode. In standby condition (EN bit LOW). The TTX function must be disabled setting TTX to LOW.

2.3 DiSEqC™ 2.0 implementation

The built-in 22 kHz Tone detector completes the fully bi-directional DiSEqC™ 2.0 (see

Note:) interfacing. Its input pin (DETIN) must be AC coupled to the DiSEqC™ bus, and

extracted PWK data are available on the DSQOUT pin. To comply with the bi-directional DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH24 is provided with two output pins for each section, one for the DC voltage output (V for the 22 kHz tone transmission (V transmission while the V

provides the 13/18 V output voltage. This allows the 22 kHz

oRX

Tone to pass without any losses due to the R-L filter impedance (see Figure 4). During the 22 kHz transmission, in DiSEqC™ 2.0 applications, activated by DSQIN pin or by the TEN bit, the V

pin must be preventively set ON by the TTX function. This can be controlled

oTX

both through the TTX pin and the I²C bit. As soon as the tone transmission is expired, the V

must be disabled by setting the TTX to LOW to set the device in the 22 kHz receiving

oTX

mode. The 13/18 V power supply is always provided to the LNB from the V the R-L filter.

oTX

). The V

must be activated only during the tone

oTX

oRX

pin through

oRX

) and one

2.4 DiSEqC™ 1.X implementation

When the LNBH24 is used in DiSEqC™ 1.x applications the R-L filter is always needed for the proper operation of the 22 kHz tone generator (patent pending. See Figure 4). Also in this case, the TTX function must be preventively enabled before to start the 22 kHz data transmission and disabled as soon as the data transmission has been expired. The tone can

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Introduction LNBH24

be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal circuit activates the 22 kHz tone on the V

output with 0.5 cycle ± 25 µs delay from the TTL signal

oTX

presence on the DSQIN pin, and it stops with 1 cycle ± 25 µs delay after the TTL signal is expired.

2.5 Data encoding through external tone generator (EXTM)

In order to improve design flexibility an external tone input pin is available (EXTM). The EXTM is a Logic input pin which activates the 22 kHz tone output, on the V the LNBH24 integrated tone generator (similar to the DSQIN pin function). In fact, the output tone waveform characteristics will always be internally controlled by the LNBH24 tone generator and the EXTM signal will be used as a timing control for DiSEqC tone data encoding on the V control of the EXTM pin function. Before sending the TTL signal on the EXTM pin, the V tone generator must be previously enabled through the TTX function (TTX pin or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal code, it activates the 22 kHz tone on the V presence on the EXTM pin, and it stops with 2 cycles ± 25 µs delay after the TTL signal is expired (see Figure 2).

Figure 2. EXTM timings

output. A TTL-compatible 22 kHz signal is required for the proper

oTX

output with 1.5 cycles ± 25 µs delay from the TTL signal

oTX

pin, by using

oTX

2.6 I²C interface

The main functions of the IC are controlled via I²C BUS by writing 8 bits on the system register (SR 8 bits in write mode). On the same register there are 8 bits that can be read back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF), while three will report the last output voltage register status (EN, VSEL, LLC) received by the IC (see the diagnostic functions section). Each section (A/B) has two selectable I²C addresses selectable, respectively, through the ADDR-A and ADDR-B pins (see address pins characteristics Ta bl e 1 0).

2.7 Output voltage selection

When the IC sections are in standby mode (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by means of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH24 is provided with the LLC I²C bit which increase the selected voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable.

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LNBH24 Introduction

The LNBH24 is also compliant with the USA LNB power supply standards. In order to allow fast transition of the output voltage from 18 V to 13 V and vice-versa, the LNBH24 is provided with the VCTRL TTL pin which keeps the output at 13 V when it is set LOW and at 18 V when it is set HIGH or floating. VSEL and, if required, LLC bits must be set HIGH before using the VCTRL pin to switch the output voltage level. If VCTRL = 1 or floating, then V

= 18.5 V (or 19.5 V if LLC=1). With VCTRL=0 V

OUT

Should be noted that the VCTRL pin controls only the linear regulator V step-up V VCTRL = 0 (keeping V

voltage is controlled only through the VSEL and LLC I²C bits. That is, even if

= 13.4 V) you will have V

OUT

=13.4 V (LLC= either 0 or 1).

OUT

= 19.25 V typ when VSEL = 1 and

stage while the

OUT

20.25 V with VSEL = LLC = 1. This means that VCTRL = 0 must be used only for short period to avoid the higher power dissipation. In standby condition (EN bit LOW) all the I²C bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during the standby condition).

2.8 Diagnostic and protection functions

The LNBH24 has 5 diagnostic internal functions provided via I²C BUS by reading 5 bits on the system register (SR bits in read mode). All the diagnostic bits are, in normal operation (no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature and over-load protection status (OTF and OLF), while the remaining 3 bits are dedicated to the output voltage level (VMON), 22 kHz Tone (TMON) and to the Minimum Load Current diagnostic function (IMON).

2.9 Output voltage diagnostic

When VSEL = 0 or 1 and LLC = 0, the output voltage pin (V as long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to "1". The output voltage diagnostic is valid only with LLC = 0 and AUX = 0. Any VMON information with LLC = 1 and/or AUX = 1 must be disregarded by the MCU.

2.10 22 kHz tone diagnostic

The 22 kHz tone can be internally detected and monitored If the DETIN pin is connected to the LNB output bus (see typical application circuits) through a decoupling capacitor. The Tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude and/or the Tone frequency is out of the guaranteed limits (see TMON limits in the electrical characteristics in Ta bl e 13 ), the TMON I²C Bit is set to "1".

2.11 Minimum output current diagnostic

In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) the LNBH24 is provided with a minimum output current flag by the IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA typically with ITEST=1, and 6 mA with ITEST=0. The minimum current diagnostic function (IMON) is always active. In order for it to function even in a multi-IRD configuration (multiswitch), where the supply current could be sunk only from the higher supply voltage connected to the multi-switch box, the LNBH24 is provided with the AUX I²C bit. To force the LNBH24 output voltage as the highest voltage on the bus (22 V typ.) during the minimum current diagnostic phase, the AUX I²C bit can be set HIGH before reading the IMON I²C bit status. When the AUX bit is set to HIGH, the V

is set to 22 V (typ.) and the VUP is set to

OUT

) is internally monitored and,

oRX

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Introduction LNBH24

22.75 V (V function is used to force the V soon as the minimum current test phase is expired, so that the V

= V

+ 0.75 V typ.) independent of the VSEL/LLC bits status. If the AUX

OUT

to 22 V, it is recommended to set the AUX bit to LOW as

OUT

voltage will be

OUT

controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the IMON function must be used only with the 22 kHz tone transmission deactivated (TEN = 0 and DSQIN = LOW), otherwise the IMON bit could be set to 0 even if the output current is below the minimum current thresholds (6 mA or 12 mA).

2.12 Output current limit selection

The linear regulator current limit threshold can be set through an external resistor connected to ISEL pin. The resistor value defines the output current limit by the equation: I

where R current limit threshold is 1.0 A typ with R

MAX(A)

= 10000/R

SEL

is the resistor connected between ISEL and GND. The highest selectable

=10 kΩ. The above equation defines the typical

SEL

threshold value for each output. However, it is suggested not to exceed for an extended period a total of current of 1 A from both sections (I

OUT_A

+ I

< 1 A) in order to avoid

OUT_B

triggering the over-temperature protection.

2.13 Over-current and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically through the PCL bit of the I²C SR. When the PCL (pulsed current limiting) bit is set to LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output is shut down for a time T the system register is set to "1". After this time has elapsed, the output is resumed for a time T

= (1/10) T

= 90 ms (typ.). At the end of TON, if the overload is still detected, the

OFF

protection circuit will cycle again through T overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW. Typical T

ON+TOFF

operation can greatly reduce the power dissipation in short-circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=1) and then switching to the dynamic mode (PCL = 0) after a chosen amount of time depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to "1" when the current clamp limit is reached and returns LOW when the overload condition is cleared.

, typically 900 ms. Simultaneously the diagnostic OLF I²C bit of

OFF

and TON. At the end of a full TON in which no

OFF

time is 990 ms and an internal timer determines it. This dynamic

2.14 Thermal protection and diagnostic

The LNBH24 is also protected against overheating. When the junction temperature exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut off, and the diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135 °C (typ.).

Note: External components are needed to comply to bi-directional DiSEqC™ bus hardware

requirements. Full compliance of the whole application with DiSEqC™ specifications is not implied by the use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT.

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LNBH24 Pin configuration

3 Pin configuration

Figure 3. Pin connections

EXTM-B

A-GND

TTX-B

DETIN-B

DSQIN-B

DSQOUT-B

ADDR-B

LX-B

P-GND-B

P-GND-A

LX-A

SDA

SCL

ADDR-A

DSQOUT-A

DSQIN-A

DETIN-A

TTX-A

EXTM-B

VCTRL-B

ISEL-B

VUP-B

VOTX-B

VORX-B

A-GND

VCC

VCC-L

BYP

VORX-A

VOTX-A

VUP-A

ISEL-A

VCTRL-A

EXTM-A

Table 2. Pin description

Pin n°

(sec. A/B)

29 V

28 V

11 LX-A

8LX-B

22 V

33 V

26 V

31 V

25 V

32 V

12 SDA Serial data Bi-directional data from / to I²C BUS.

13 SCL Serial clock Clock from I²C BUS.

16 DSQIN-A

4DSQIN-B

Symbol Name Function

L Supply input 8 to 15 V analog power supply.

CC–

Supply input 8 to 15 V IC DC-DC power supply.

N-MOS Drain Integrated N-Channel power MOSFETs drain.

oRX

oTX

-A

-B

-A

-B

-A

-B

Step-Up voltage

LDO output port

Output port during

22 kHz Tone TX

Input of the linear post-regulators. The voltage on these pins is monitored by the internal step-up controllers to keep a minimum dropout across the linear pass transistors.

Outputs of the linear post-regulators. See Ta bl e 6 for voltage selections and description.

TX Outputs to the LNB. See Ta bl e 6 for selection.

These pins will accept the DiSEqC code from the main

DiSEqC inputs

microcontroller. The LNBH24 will uses this code to modulate the internally-generated 22 kHz carrier. Set to ground if not used.

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