Datasheet LNBH24 Datasheet (ST)

Dual LNB supply and control IC with step-up and I²C interface

Features

■ Complete interface between LNBS and I²C bus

■ Built-in DC-DC converter for single 12 V supply

operation and high efficiency (typ. 93%@0.5 A)

■ Selectable output current limit through external

resistor

■ Compliant with main satellite receivers output

voltage specification

■ New accurate built-in 22 kHz tone generator

meets widely accepted standards (patent pending)

■ Fast oscillator start-up facilitates DiSEqC™

encoding

■ Built-in 22 kHz tone detector supports bi-

directional DiSEqC™ 2.0

■ Very low-drop post regulator and high

efficiency step-up PWM with integrated power N-MOS allow low power losses

■ Two output pins suitable for bypassing the

output R-L filter and avoiding tone distortion (RL filter as per DiSEqC™ 2.0 specs, see typ. application circuits)

■ Overload and over-temperature internal

protections with I²C diagnostic bits

■ Output voltage and output current level

diagnostic feedback by I²C bits

■ LNB short circuit dynamic protection

■ +/- 4 kV ESD tolerant on output power pins

LNBH24

PowerSSO-36 (ePad)

designed to provide the 13/18 V power supply and the 22 kHz tone signalling for two independent LNB down-converters in the antenna dishes and/or multi-switch box. In this application field, it offers a dual tuner STBs with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.

Description

Intended for analog and digital dual satellite receivers/sat-TV, sat-PC cards, the LNBH24 is a monolithic voltage regulator and interface IC, assembled in PowerSSO-36 ePad, specifically

Table 1. Device summary

Order code Package Packaging

LNBH24PPR PowerSSO-36 (Exposed pad) Tape and reel

April 2009 Rev 3 1/30

www.st.com

30

Contents LNBH24

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 DiSEqC™ data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 DiSEqC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 DiSEqC™ 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 Data encoding through external tone generator (EXTM) . . . . . . . . . . . . . . 6

2.6 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.9 Output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.11 Minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.12 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.13 Over-current and short-circuit protection and diagnostic . . . . . . . . . . . . . . 8

2.14 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 LNBH24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/30

LNBH24 Contents

7.2 System register (SR, 1 Byte for each section A and B) . . . . . . . . . . . . . . 16

7.3 Transmitted data (I²C bus write mode) for each section A/B . . . . . . . . . . 16

7.4 Diagnostic received data (I²C read mode) for both sections A/B . . . . . . . 17

7.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.7 DiSEqC™ implementation for each section A/B . . . . . . . . . . . . . . . . . . . 18

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3/30

Block diagram LNBH24

1 Block diagram

Figure 1. Block diagram

..

A

-

A

TEN-

EN-

VSEL-

TTX-

A

TEN-

SDA SCL

A

-

A

-

A

-

A

-

I²C Diagnostics

²

I²C Diagnostics

²

A

-

LNBH24

ADDR -

²

I²C interface

TEN-

EN-

VSEL-

VSELTTX-

TTX-

TEN-

V

-

Byp

CC

Preregulator

Preregulator +U.V.lockout

+U.V.lockout +P.ON reset

+P.ON reset

B

-

B

-

B

ITEST-

B

Linear Post -reg

Linear Post -reg +Protections

+Protections +Diagnostics

+Diagnostics

Oscill.

B

-

B

VOUT-BControl

VCC-

ISEL -

-

ISEL -

-

B

-

B

-

B

22KHz Tone

22KHz Tone Amp. Diagn.

Amp. Diagn.

22KHz Tone

Det.

Freq. Det.

TTX-

PWM

Controller

.

B

TTX-

Rsense

B

--

-

VCC-

-

L

EN-

VSEL-

B

-

ISEL-

-

ISEL-

-

.

- -

TTX-

- -

A

-

LX-

A

Rsense

P-GND-

-- -

P-GND-

-- -

A

V

-

V

-

A

UP

-

VoRX -

A

VCTRL -

-

VCTRL -

-

A

-

VoTX -

A

TTX-

TTX-A-

TTX-

EXTM -

DSQIN -

DETIN -

DSQOUT

TTX-A-

-

A

-

A

22KHz Tone

-

A

-

22KHz Tone Amp. Diagn.

Amp. Diagn.

22KHz Tone

22KHz Tone Freq. Det.

Freq. Det.

PWM

Det.

Controller

.

EN-

-

EN-

-

VSEL-

ISEL-

Linear Post -reg

Linear Post -reg +Protections

+Protections +Diagnostics

+Diagnostics

ISEL -

A

-

A

ITEST-

A

22KHz

22KHz Oscill.

Oscill.

ADDR -

VOUT-AControl

-

ADDR -

ISEL -

TTX-

LX-

B

P-GND-

V

-

B

UP

VoRX -

-

VCTRL -

VoTX -

EXTM -

DSQIN -

DETIN -

DSQOUT

B

-

B

-

B

-

B

-

B

-

4/30

A-GND

-

A-GND

-

LNBH24 Introduction

2 Introduction

The LNBH24 includes two completely independent sections. Except for the VCC and I²C inputs, each circuit can be separately controlled and have independent external components. The specification that follow should be considered equally for both sections (A/B).

2.1 Application information

This IC has a built-in DC-DC step-up converter which, from a single 8 V to 15 V source, generates the voltages (V dissipated power of 0.375 W Typ. @ 500 mA load (the linear post-regulator drop voltage is internally held at V

UP-VOUT

entire circuit when the supplied V

Note: In this document the V

output (V

oRX

pin).

2.2 DiSEqC™ data encoding and decoding

) that allow the linear post-regulator to work at a minimum

UP

=0.75 V typ.). An under voltage lockout circuit will disable the

drops below a fixed threshold (6.7 V typically).

CC

is intended as the voltage present at the linear post-regulator

OUT

The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance with the standards, and can be selected through I²C interface TTX bit (or TTX pin) and activated by a dedicated pin (DSQIN) which allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the 22 kHz presence is requested in continuous mode. In standby condition (EN bit LOW). The TTX function must be disabled setting TTX to LOW.

2.3 DiSEqC™ 2.0 implementation

The built-in 22 kHz Tone detector completes the fully bi-directional DiSEqC™ 2.0 (see

Note:) interfacing. Its input pin (DETIN) must be AC coupled to the DiSEqC™ bus, and

extracted PWK data are available on the DSQOUT pin. To comply with the bi-directional DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH24 is provided with two output pins for each section, one for the DC voltage output (V for the 22 kHz tone transmission (V transmission while the V

provides the 13/18 V output voltage. This allows the 22 kHz

oRX

Tone to pass without any losses due to the R-L filter impedance (see Figure 4). During the 22 kHz transmission, in DiSEqC™ 2.0 applications, activated by DSQIN pin or by the TEN bit, the V

pin must be preventively set ON by the TTX function. This can be controlled

oTX

both through the TTX pin and the I²C bit. As soon as the tone transmission is expired, the V

must be disabled by setting the TTX to LOW to set the device in the 22 kHz receiving

oTX

mode. The 13/18 V power supply is always provided to the LNB from the V the R-L filter.

oTX

). The V

must be activated only during the tone

oTX

oRX

pin through

oRX

) and one

2.4 DiSEqC™ 1.X implementation

When the LNBH24 is used in DiSEqC™ 1.x applications the R-L filter is always needed for the proper operation of the 22 kHz tone generator (patent pending. See Figure 4). Also in this case, the TTX function must be preventively enabled before to start the 22 kHz data transmission and disabled as soon as the data transmission has been expired. The tone can

5/30

Introduction LNBH24

be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal circuit activates the 22 kHz tone on the V

output with 0.5 cycle ± 25 µs delay from the TTL signal

oTX

presence on the DSQIN pin, and it stops with 1 cycle ± 25 µs delay after the TTL signal is expired.

2.5 Data encoding through external tone generator (EXTM)

In order to improve design flexibility an external tone input pin is available (EXTM). The EXTM is a Logic input pin which activates the 22 kHz tone output, on the V the LNBH24 integrated tone generator (similar to the DSQIN pin function). In fact, the output tone waveform characteristics will always be internally controlled by the LNBH24 tone generator and the EXTM signal will be used as a timing control for DiSEqC tone data encoding on the V control of the EXTM pin function. Before sending the TTL signal on the EXTM pin, the V tone generator must be previously enabled through the TTX function (TTX pin or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal code, it activates the 22 kHz tone on the V presence on the EXTM pin, and it stops with 2 cycles ± 25 µs delay after the TTL signal is expired (see Figure 2).

Figure 2. EXTM timings

output. A TTL-compatible 22 kHz signal is required for the proper

oTX

output with 1.5 cycles ± 25 µs delay from the TTL signal

oTX

pin, by using

oTX

2.6 I²C interface

The main functions of the IC are controlled via I²C BUS by writing 8 bits on the system register (SR 8 bits in write mode). On the same register there are 8 bits that can be read back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF), while three will report the last output voltage register status (EN, VSEL, LLC) received by the IC (see the diagnostic functions section). Each section (A/B) has two selectable I²C addresses selectable, respectively, through the ADDR-A and ADDR-B pins (see address pins characteristics Ta bl e 1 0).

2.7 Output voltage selection

When the IC sections are in standby mode (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by means of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH24 is provided with the LLC I²C bit which increase the selected voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable.

6/30

LNBH24 Introduction

The LNBH24 is also compliant with the USA LNB power supply standards. In order to allow fast transition of the output voltage from 18 V to 13 V and vice-versa, the LNBH24 is provided with the VCTRL TTL pin which keeps the output at 13 V when it is set LOW and at 18 V when it is set HIGH or floating. VSEL and, if required, LLC bits must be set HIGH before using the VCTRL pin to switch the output voltage level. If VCTRL = 1 or floating, then V

= 18.5 V (or 19.5 V if LLC=1). With VCTRL=0 V

OUT

Should be noted that the VCTRL pin controls only the linear regulator V step-up V VCTRL = 0 (keeping V

voltage is controlled only through the VSEL and LLC I²C bits. That is, even if

UP

= 13.4 V) you will have V

OUT

=13.4 V (LLC= either 0 or 1).

OUT

= 19.25 V typ when VSEL = 1 and

UP

stage while the

OUT

20.25 V with VSEL = LLC = 1. This means that VCTRL = 0 must be used only for short period to avoid the higher power dissipation. In standby condition (EN bit LOW) all the I²C bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during the standby condition).

2.8 Diagnostic and protection functions

The LNBH24 has 5 diagnostic internal functions provided via I²C BUS by reading 5 bits on the system register (SR bits in read mode). All the diagnostic bits are, in normal operation (no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature and over-load protection status (OTF and OLF), while the remaining 3 bits are dedicated to the output voltage level (VMON), 22 kHz Tone (TMON) and to the Minimum Load Current diagnostic function (IMON).

2.9 Output voltage diagnostic

When VSEL = 0 or 1 and LLC = 0, the output voltage pin (V as long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to "1". The output voltage diagnostic is valid only with LLC = 0 and AUX = 0. Any VMON information with LLC = 1 and/or AUX = 1 must be disregarded by the MCU.

2.10 22 kHz tone diagnostic

The 22 kHz tone can be internally detected and monitored If the DETIN pin is connected to the LNB output bus (see typical application circuits) through a decoupling capacitor. The Tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude and/or the Tone frequency is out of the guaranteed limits (see TMON limits in the electrical characteristics in Ta bl e 13 ), the TMON I²C Bit is set to "1".

2.11 Minimum output current diagnostic

In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) the LNBH24 is provided with a minimum output current flag by the IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA typically with ITEST=1, and 6 mA with ITEST=0. The minimum current diagnostic function (IMON) is always active. In order for it to function even in a multi-IRD configuration (multiswitch), where the supply current could be sunk only from the higher supply voltage connected to the multi-switch box, the LNBH24 is provided with the AUX I²C bit. To force the LNBH24 output voltage as the highest voltage on the bus (22 V typ.) during the minimum current diagnostic phase, the AUX I²C bit can be set HIGH before reading the IMON I²C bit status. When the AUX bit is set to HIGH, the V

is set to 22 V (typ.) and the VUP is set to

OUT

) is internally monitored and,

oRX

7/30

Introduction LNBH24

22.75 V (V function is used to force the V soon as the minimum current test phase is expired, so that the V

UP

= V

+ 0.75 V typ.) independent of the VSEL/LLC bits status. If the AUX

OUT

to 22 V, it is recommended to set the AUX bit to LOW as

OUT

voltage will be

OUT

controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the IMON function must be used only with the 22 kHz tone transmission deactivated (TEN = 0 and DSQIN = LOW), otherwise the IMON bit could be set to 0 even if the output current is below the minimum current thresholds (6 mA or 12 mA).

2.12 Output current limit selection

The linear regulator current limit threshold can be set through an external resistor connected to ISEL pin. The resistor value defines the output current limit by the equation: I

where R current limit threshold is 1.0 A typ with R

MAX(A)

= 10000/R

SEL

is the resistor connected between ISEL and GND. The highest selectable

=10 kΩ. The above equation defines the typical

SEL

threshold value for each output. However, it is suggested not to exceed for an extended period a total of current of 1 A from both sections (I

OUT_A

+ I

< 1 A) in order to avoid

OUT_B

triggering the over-temperature protection.

2.13 Over-current and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically through the PCL bit of the I²C SR. When the PCL (pulsed current limiting) bit is set to LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output is shut down for a time T the system register is set to "1". After this time has elapsed, the output is resumed for a time T

= (1/10) T

ON

= 90 ms (typ.). At the end of TON, if the overload is still detected, the

OFF

protection circuit will cycle again through T overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW. Typical T

ON+TOFF

operation can greatly reduce the power dissipation in short-circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=1) and then switching to the dynamic mode (PCL = 0) after a chosen amount of time depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to "1" when the current clamp limit is reached and returns LOW when the overload condition is cleared.

, typically 900 ms. Simultaneously the diagnostic OLF I²C bit of

OFF

and TON. At the end of a full TON in which no

OFF

time is 990 ms and an internal timer determines it. This dynamic

2.14 Thermal protection and diagnostic

The LNBH24 is also protected against overheating. When the junction temperature exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut off, and the diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135 °C (typ.).

Note: External components are needed to comply to bi-directional DiSEqC™ bus hardware

requirements. Full compliance of the whole application with DiSEqC™ specifications is not implied by the use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT.

8/30

LNBH24 Pin configuration

3 Pin configuration

Figure 3. Pin connections

36

EXTM-B

A-GND

TTX-B

DETIN-B

DSQIN-B

DSQOUT-B

ADDR-B

NC

LX-B

P-GND-B

P-GND-A

LX-A

SDA

SCL

ADDR-A

DSQOUT-A

DSQIN-A

DETIN-A

TTX-A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

EXTM-B

35

VCTRL-B

34

ISEL-B

33

VUP-B

32

VOTX-B

31

VORX-B

30

A-GND

29

VCC

28

VCC-L

27

BYP

26

VORX-A

25

VOTX-A

24

NC

23

NC

22

VUP-A

21

ISEL-A

20

VCTRL-A

19

EXTM-A

Table 2. Pin description

Pin n°

(sec. A/B)

29 V

28 V

11 LX-A

8LX-B

22 V

33 V

26 V

31 V

25 V

32 V

12 SDA Serial data Bi-directional data from / to I²C BUS.

13 SCL Serial clock Clock from I²C BUS.

16 DSQIN-A

4DSQIN-B

Symbol Name Function

CC

L Supply input 8 to 15 V analog power supply.

CC–

Supply input 8 to 15 V IC DC-DC power supply.

N-MOS Drain Integrated N-Channel power MOSFETs drain.

UP

oRX

oTX

-A

-B

-A

-B

-A

-B

Step-Up voltage

LDO output port

Output port during

22 kHz Tone TX

Input of the linear post-regulators. The voltage on these pins is monitored by the internal step-up controllers to keep a minimum dropout across the linear pass transistors.

Outputs of the linear post-regulators. See Ta bl e 6 for voltage selections and description.

TX Outputs to the LNB. See Ta bl e 6 for selection.

These pins will accept the DiSEqC code from the main

DiSEqC inputs

microcontroller. The LNBH24 will uses this code to modulate the internally-generated 22 kHz carrier. Set to ground if not used.

9/30

Pin configuration LNBH24

Table 2. Pin description (continued)

Pin n°

(sec. A/B)

18 TTX-A

2TTX-B

17 DETIN-A

3DETIN-B

15 DSQOUT- A

5 DSQOUT- B

19 EXTM-A

36 EXTM-B

Symbol Name Function

The TTX pins can be used as well as the TTX I²C bits of the

TTX enable

system register, to control the TTX function enable. Set floating or to GND if not used.

Tone decoders

inputs

22 kHz tone decoders inputs must be AC coupled to the DiSEqC 2.0 BUS. Set to GND if not used.

Open drain outputs of the tone detectors to the main

DiSEqC outputs

µController for DiSEqC 2.0 data decoding. They are LOW when tone is detected on DETIN pins. Set to GND if not used.

External

modulation

External modulation logic input pins which activate the 22 kHz tone output on the V

10 P-GND-A

Power grounds DC-DC converters power grounds.

9 P-GND-B

ePad ePad Exposed Pad

To be connected with power grounds and to the ground layer through vias to dissipate the heat.

1, 30 A-GND Analog grounds Analog circuits grounds.

Needed for internal pre-regulator filtering. The BYP pin is

27 BYP By-pass capacitor

intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.

pins. Set to ground if not used.

oTX

14 ADDR-A

6 ADDR-B

21 ISEL-A

34 ISEL-B

20 VCTRL-A

35 VCTRL-B

Address setting

Current selection

Output voltage

control

Two I²C addresses available for each section by setting the Address pins voltage level. See Ta bl e 1 0

The resistors “RSEL” connected between ISEL and GND define the linear regulators current limit protection threshold by the equation: I

(typ)=10000/ RSEL.

MAX

13 V-18 V linear regulators V only with VSEL=1. If V

19.5V if LLC=1). If V

=1 or floating VoRX=18.5 V (or

CTRL

=0 than VoRX=13.4 V (LLC=either 0

CTRL

or 1). Leave floating if not used. DO NOT connect to GND if not used.

7, 23, 24 N.C. Not connected Not internally connected pins.

switch control. To be used

oRX

10/30

LNBH24 Maximum ratings

4 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

, VCCDC power supply input voltage pins -0.3 to 16 V

CC-L

V

UP

I

O

V

oRX

V

oTX

V

LX LX input voltage -0.3 to 24 V

V

DETIN

V

OH

V

BYP

ISEL Current selection pin voltage -0.3 to 4.6 V

DC input voltage -0.3 to 24 V

Output current Internally limited

DC output pin voltage -0.3 to 25 V

Tone output pin voltage -0.3 to 25 V

Logic input voltage (TTX, SDA, SCL, DSQIN, EXTM, V

I

, Address) -0.3 to 7 V

CTRL

Detector input signal amplitude 2 V

Logic high output voltage (DSQOUT) -0.3 to 7 V

Internal reference pin voltage (Note 1) -0.3 to 4.6 V

PP

T

STG

T

ESD

Storage temperature range -50 to 150 °C

Operating junction temperature range -25 to 125 °C

J

ESD rating with human body model (HBM) for all pins unless 8, 11, 25, 26, 31, 32

2

ESD rating with human body model (HBM) for pins 25, 26, 31, 32 4

kV

ESD rating with human body model (HBM) for pins 8, 11 0.6

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.

These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.

Note: 1 The BYP pin is intended only to connect an external ceramic capacitor. Any connection of

this pin to external current or voltage sources may cause permanent damage to the device.

Table 4. Thermal data

Symbol Parameter Value Unit

R

thJC

thJA

Thermal resistance junction-case 2 °C/W

Thermal resistance junction-ambient (PSSO-36) with device soldered on 2s2p PC Board

30 °C/W

11/30

Application circuit LNBH24

5 Application circuit

Figure 4. Typical application circuit

D3a

D3a 1N4007

1N4007

20

D1a

D1a STPS130A

STPS130A

V

IN

+12V

D1b

D1b STPS130A

STPS130A

L1a

L1a 22µH

22µH

L1b

L1b 22µH

22µH

C4a

C3a

C4a

C3a

470nF

100µF

470nF

100µF

C1 C2

100µF

C4b

C3b

C4b

C3b

470nF

100µF

470nF

100µF

Ferrite

Rsel-A

C7

100nF

Ferrite

L2a

Bead

11KΩ

L2b

Bead

I2C

C5b

C5b 100µF

100µF

C5b

Rsel-B

11KΩ

R1

R1 100Ω

100Ω

C8

C8 220nF

220nF

19

20

C6b

C6b 470nF

470nF

C6b

C6b 470nF100µF

470nF100µF

19

VCTRL-A

EXTM-A

-A

V

22

UP

LX-A

11

ISEL-A

21

ISEL-B

34

V

29

CC

V

-L

28

CC

LX-B

8

SCL

13

SDA

12

-B

V

33

UP

P-GND-B10P-GND-A ADDR-B

VCTRL-A

A-GND

1-30

L

L N

N B

B H

H 2

2 4

4

EXTM-B

BYP

27

35

36

35

36

VCTRL-B

C11

C11 470nF

470nF

VCTRL-B

DSQOUT-A

DSQOUT-B

ADDR-A

14

D3b

D3b 1N4007

1N4007

VoTX-A

VoRX-A

DETIN-A

DSQIN-A

TTX-A

DSQIN-B

TTX-B

DETIN-B

VoRX-B

VoTX-B

25

26

C10a

C10a 220nF

220nF

17

16

16 15

15 18

18

4

4 5

5 2

2

3

31

C10b

C10b 220nF

220nF

32

69

D4a

D4a 1N5818

1N5818

D2a

D2a BAT43

BAT43

R3a 10KΩ

R3b 10KΩ

D2b

D2b BAT43

BAT43

D4b

1N5818

C9a 10µF

L3a

220µH

15 Ω

15 Ω R4a

R4a

L3b

220µH

15Ω

15Ω R4b

R4b

C9b 10µF

C12a

10nF

C12b

C12b 10nF

10nF

LNBOUT_A

C13a 10nF

LNBOUT_B

C13b 10nF

12/30

LNBH24 Application circuit

Table 5. Bill of material (valid for A and B sections except for C1, C2, C7, C8 and R1)

Component Notes

R1, R4 1/4 W resistors. Refer to the typical application circuit for the relative values

R3, R

SEL

C1 25 V electrolytic capacitor, 100 µF or higher is suitable.

C9 10µF, > 35 V electrolytic capacitor

C3, C5 100µF, > 25 V electrolytic capacitor, ESR in the 150 mΩ to 350 mΩ range

1/8 W resistors. Refer to the typical application circuit for the relative values

C2, C4, C6, C7, C8, C10,

C11, C12, C13

D1

D2 BAT43, 1N5818, or any schottky diode with I

D3 1N4007 or equivalent

D4 1N5818 or equivalent schottky diode

L1

L2

L3 220 µH-270 µH inductor with current rating higher than rated output current

>25 V ceramic capacitors. Refer to the typ. appl. circuit for the relative values

STPS130A or any similar schottky diode with V

> I

I

F(AV)

OUT_MAX

22µH inductor with I

x (V

UP_MAX/VIN_MIN

SAT>IPEAK

, where I

)

F(AV)

is the boost converter peak current:

PEAK

> 25 V and I

RRM

>0.2A, V

RRM

higher than:

F(AV)

> 25 V, VF<0.5 V

Ferrite bead, Panasonic-EXCELS A35, Murata-BL01RN1-A62, Taiyo-YudenBKP1608HS600 or equivalent with similar or higher impedance and current rating higher than 2A

13/30

I²C bus interface LNBH24

6 I²C bus interface

Data transmission from main MCU to the LNBH24 and vice-versa takes place through the 2 wires I²C bus Interface, consisting of the 2 SDA and SCL lines (pull-up resistors to positive supply voltage must be externally connected).

6.1 Data validity

As shown in Figure 5 the data on the SDA line must be stable during the high semi-period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

6.2 Start and stop condition

As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.

6.3 Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

6.4 Acknowledge

The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 7). The peripheral (LNBH24) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH24 will not generate acknowledge if the V

supply is below the under-voltage lockout threshold (6.7 V typ.).

CC

6.5 Transmission without acknowledge

Avoiding to detect the acknowledges of the LNBH24, the MCU can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from malfunctions and decreases the noise immunity.

14/30

LNBH24 I²C bus interface

Figure 5. Data validity on the I²C bus

Figure 6. Timing diagram of I²C bus

Figure 7. Acknowledge on the I²C bus

15/30

LNBH24 software description LNBH24

7 LNBH24 software description

The LNBH24 I²C interface controls both the IC sections A and B depending on the address sent before the DATA byte. The description below is valid for both sections.

7.1 Interface protocol

The interface protocol comprises:

● A start condition (S)

● A chip address byte (the LSB bit determines read (=1)/write (=0) transmission)

● A sequence of data (1 byte + acknowledge)

● A stop condition (P)

Section address (A or B) Data

MSB LSB MSB LSB

S 0 0 0 1 0 X X R/W ACK ACK P

ACK = Acknowledge

S = Start

P = Stop

R/W = 1/0, Read/Write bit

X = 0/1, two addresses for each section selectable by ADDR-A/B pins (see Ta bl e 1 0)

7.2 System register (SR, 1 Byte for each section A and B)

Mode MSB LSB

Write PCL TTX TEN LLC VSEL EN ITEST AUX

Read IMON VMON TMON LLC VSEL EN OTF OLF

Write = control bits functions in write mode

Read = diagnostic bits in read mode.

All bits reset to 0 at power on

7.3 Transmitted data (I²C bus write mode) for each section A/B

When the R/W bit in the section address is set to 0, the main MCU can write on the system register (SR) of the relative section (A or B, depending on the 7 bit address value) via I²C BUS. All and 8 bits are available and can be written by the MCU to control the device functions as per the below Tab le 6 .

16/30

LNBH24 LNBH24 software description

Table 6. Truth table

PCL TTX TEN LLC VSEL EN ITEST AUX Function

0001 0V

0011 0V

0101 0V

0111 0V

XX1X 1V

= 13.4 V, VUP=14.15 V, (VUP-V

oRX

= 18.5 V, VUP=19.25 V, (VUP-V

oRX

= 14.4 V, VUP=15.15 V, (VUP-V

oRX

= 19.5 V, VUP=20.25 V, (VUP-V

oRX

= 22 V, VUP=22.75 V, (VUP-V

oRX

=0.75 V)

oRX

=0.75 V)

0 1 22 KHz controlled by DSQIN pin (only if TTX=1)

1 1 1 22 KHz tone output is always activated

01V

11V

output is ON, V

oRX

output is ON, V

oRX

Tone generator output is OFF

oTX

Tone generator output is ON

oTX

0 1 Pulsed (dynamic) current limiting is selected

1 1 Static current limiting is selected

X X 1 0 Minimum output current diagnostic threshold = 6mA typ.

X X 1 1 Minimum output current diagnostic threshold = 12mA typ.

X X X X X 0 X X Power block disabled

X = don't care

All values are typical unless otherwise specified

Valid with TTX pin floating or connected GND

7.4 Diagnostic received data (I²C read mode) for both sections A/B

The LNBH24 can provide to the master a copy of the diagnostic system register information via I²C bus in read mode. The read mode is master activated by sending the chip address with R/W bit set to 1. At the following master generated clock bits, the LNBH24 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can:

● Acknowledge the reception, thus starting the transmission of another byte from the

LNBH24

● No acknowledge, stopping the read mode communication

Three bits of the register are read back as a copy of the corresponding write output voltage register status (LLC, VSEL, EN), while the other five bits convey diagnostic information about the over-temperature (OTF), output voltage level (VMON), output overload (OLF), minimum output current presence (IMON) and 22 kHz tone (TMON). In normal operation the diagnostic bits are set to zero, while if a failure is occurring, the corresponding bit is set to one. At start-up all the bits are reset to zero.

17/30

LNBH24 software description LNBH24

Table 7. Register

IMON VMON TMON LLC VSEL EN OTF OLF Function

0/1 0/1 0/1

< 135°C, normal operation

J

> 150°C, power blocks disabled

J

< I

O

> I

O

These bits are set to 1 if the relative parameter is out of the specification limits.

, normal operation

OMAX

, Overload Protection triggered

OMAX

These bits are read

exactly the same as

they were left after

last write operation

0T

1T

0I

1I

Note: Values are typical unless otherwise specified.

7.5 Power-on I²C interface reset

The I²C interface built in the LNBH24 is automatically reset at power-ON. As long as the VCC stays below the undervoltage lockout (UVL) threshold (6.7 V), the interface will not respond to any I²C command and the system registers (SR) are initialized to all zeroes, thus keeping the power blocks disabled. Once the V operative and the SRs can be configured by the main MCU. This is due to 500 mV hysteresis provided in the UVL threshold to avoid false re-triggering of the power-ON reset circuit.

rises above 7.3 V typ. The I²C interface becomes

CC

7.6 Address pin

For each section of the LNBH24 it is possible to select two I²C interface addresses by means of the relevant ADDR pin. The ADDR pins are TTL-compatible and can be set as per address pins characteristics Tab le 1 0 .

7.7 DiSEqC™ implementation for each section A/B

LNBH24 helps system designer to implement the bi-directional DiSEqC 2.0 protocol by allowing easy PWK modulation/demodulation of the 22 kHz carrier. Between the LNBH24 and the main MCU the PWK data is exchanged using logic levels that are compatible with both 3.3 V and 5 V MCU. This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the MCU, thus leaving to the firmware the task of encoding and decoding the PWK data in accordance with the DiSEqC protocol. Full compliance of the system to the specification is thus not implied by the bare use of the LNBH24. The system designer should also take in consideration the bus hardware requirements, which can be simply accomplished by the R-L termination connected on the V in the typical application circuits in Figure 4. To avoid any losses due to the R-L impedance during the tone transmission, LNBH24 has dedicated Tone output (V after the filter and must be enabled by setting the TTX function to HIGH only during the tone transmission (see DiSEqC 2.0 implementation in sections 2.2 and 2.3). Also unidirectional DiSEqC 1.x and non-DiSEqC system need this termination connected through a bypass capacitor and after an R-L filter with 15 Ω in parallel with a 220 µH-270 µH inductor. However, there is no need for tone decoding, so the DETIN and DSQOUT pins can be left connected to GND.

pins of the LNBH24, as shown

OUT

oTX

) that is connected

18/30

LNBH24 Electrical characteristics

8 Electrical characteristics

Refer to the typical application circuit in Figure 4, TJ from 0 to 85 °C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R 50 mA, unless otherwise stated. Typical values are referred to T voltage. See software description section for I²C access to the system register.

Table 8. Electrical characteristics of sections A/B

Symbol Parameter Test conditions Min. Typ. Max. Unit

= 11 kΩ, DSQIN=LOW, VI = 12 V, I

SEL

= 25 °C. V

J

OUT=VoRX

OUT

=

V

13/18

T

R

I

MAX

T

F

TONE

A

TONE

D

TONE

t

F

EXTM

Eff

IN

I

IN

OUT

- T

I

SC

OFF

ON

, t

r

f

DC-DC

Supply voltage I

Supply current

=750mA, VSEL=LLC=1 8 12 15 V

OUT

Both sections A and B enabled,

=0

I

OUT

EN=TEN=TTX=1, I

OUT

=0

20 30

50 70

EN=0 6

AUX=1; I

=50mA 22

OUT

LLC=0 17.8 18.5 19.2

Output voltage

SEL

=1, I

OUT

=750mA

LLC=1 18.8 19.5 20.2

V

LLC=0 12.8 13.4 14

V

SEL

=0, I

OUT

=750mA

LLC=1 13.8 14.4 15

VSEL=0 5 40

Line regulation VIN=8 to 15V

VSEL=1 5 60

Load regulation V

13/18V Rise and Fall transition time by V

F

CTRL

Output current limiting

Output short circuit current V

Dynamic overload protection OFF time

Dynamic overload protection ON time

=0 or 1, I

SEL

=LLC=1, V

V

SEL

HIGH and vice versa, I

from 50 to750mA 200 mV

OUT

from LOW to

CTRL

from 6 to

OUT

575 µs

450mA, CO from 10 to 330nF

R

=11KΩ 750 1000

SEL

= 22KΩ 300 600

R

SEL

=0/1, AUX=0/1 1000 mA

SEL

PCL=0, Output shorted 900

PCL=0, Output shorted T

OFF

/10

Tone frequency DSQIN=HIGH or TEN=1, TTX=1 20 22 24 kHz

DSQIN=HIGH or TEN=1, TTX=1

Tone amplitude

I

from 0 to750mA

OUT

C

from 0 to 750nF

OUT

0.4 0.65 0.9 V

Tone duty cycle DSQIN=HIGH or TEN=1, TTX=1 43 50 57 %

Tone rise or fall time DSQIN=HIGH or TEN=1, TTX=1 5 8 15 µs

EXTM frequency V

DC-DC converter efficiency I

=3.3V, V

EXTM-H

=750mA 93 %

OUT

EXTM-L

=0V,

(1)

20 22 24 kHz

mABoth sections A and B enabled,

V

mV

mA

ms

PP

19/30

Electrical characteristics LNBH24

Table 8. Electrical characteristics of sections A/B (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

F

SW

F

DETIN

V

DETIN

Z

DETIN

V

I

OZ

V

I

OBK

T

SHDN

ΔT

SHDN

1. External signal frequency range in which the EXTM function is guaranteed.

2. Frequency range in which the DETIN function is guaranteed. The V

capacitor. See typical application circuit in Figure 4).

DC-DC converter switching frequency

Tone detector frequency capture range

0.4V

sine wave

PP

(2)

Tone detector input amplitude Sine wave signal, 22 kHz 0.3 1.5 V

Tone detector input impedance

DSQOUT pin logic LOW DETIN Tone present, IOL=2mA 0.3 0.5 V

OL

DSQOUT pin leakage current DETIN Tone absent, VOH=6V 10 µA

DSQIN,TTX,13/18, EXTM pin

IL

logic Low

DSQIN,TTX,13/18, EXTM pin

IH

logic High

DSQIN,TTX,13/18, EXTM pin

IH

input current

Output backward current EN=0, V

=5V 15 µA

V

IH

=21V -6 -15 mA

OBK

Thermal shut-down threshold 150 °C

Thermal shut-down hysteresis

level is intended on the LNBOUT (before the C12A/B

PP

220 kHz

19 22 25 kHz

PP

150 kΩ

0.8 V

2V

15 °C

TJ from 0 to 85 °C, VI = 12 V.

Table 9. I²C electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

IL

V

IH

I

IN

V

OL

F

MAX

LOW Level input voltage SDA, SCL 0.8 V

HIGH Level input voltage SDA, SCL 2 V

Input current SDA, SCL, VI = 0.4 to 4.5 V -10 10 µA

Low level output voltage SDA (open drain), IOL = 6 mA 0.6 V

Maximum clock frequency SCL 400 kHz

20/30

LNBH24 Electrical characteristics

TJ from 0 to 85 °C, VI = 12 V.

Table 10. Address pins characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

V

ADDR-A1

V

ADDR-A2

V

ADDR-B1

"0001000(R/W)" Address pin voltage range for section A

"0001001(RW)" Address pin voltage range for section A

"0001010(R/W)" Address pin voltage range for section B

Section “A” address selection

R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)

Section “B” address selection

R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)

00.8V

25V

00.8V

V

ADDR-B2

"0001011(RW)" Address pin voltage range for section B

R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)

25V

Refer to the typical application circuit in Figure 4, TJ from 0 to 85 °C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R mA, unless otherwise stated. Typical values are referred to T See software description section for I²C

Table 11. Output voltage diagnostic (VMON bit) characteristics of sections A/B

Symbol Parameter Test condition Min. Typ. Max. Unit

V

TH-L

V

TH-L

Diagnostic low threshold at

=13.4V typ.

V

O

Diagnostic low threshold at VO=18.5V typ.

NB: if the output voltage is lower than the min. value the VMON I²C bit is set to 1.

When VSEL=0: If VMON=0 then V

When VSEL=1: If VMON=0 then V

EN=1, VSEL=0 LLC=0

EN=VSEL=1 LLC=0

>85% of VO typ.; If VMON=1 then VO<95% of VO typ.

O

>84% of VO typ.; If VMON=1 then VO<96% of VO typ.

O

access to the system register.

= 11 kΩ, DSQIN=LOW, VI=12 V, IO = 50

SEL

= 25 °C. VO=V

J

pin voltage.

oRX

85 90 95 %

84 90 96 %

Refer to the typical application circuit in Figure 4, TJ from 0 to 85 °C, EN=1, VSEL=LLC=TEN=PCL=TTX=0, DSQIN=LOW, R otherwise stated. Typical values are referred to T software description section for I²C

Table 12. Minimum output current diagnostic (IMON bit) characteristics of sections A/B

access to the system register.

= 11 kΩ, VI = 12 V, IO = 50 mA, unless

SEL

= 25 °C. VO=V

J

pin voltage. See

oRX

Symbol Parameter Test condition Min. Typ. Max. Unit

I

TH

Minimum current diagnostic threshold

NB: if the output current is lower than the min. threshold limit the IMON I²C bit is set to 1. If the output current is

higher than the max threshold limit the IMON I²C bit is set to 0.

ITEST=1, AUX=0/1 5 12 20

mA

ITEST=0, AUX=0/1 2.5 6 10

21/30

Electrical characteristics LNBH24

Refer to the typical application circuit in Figure 4, TJ from 0 to 85 °C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R mA, unless otherwise stated. Typical values are referred to T description section for I²C

Table 13. 22KHz tone diagnostic (TMON bit) characteristics of sections A/B

Symbol Parameter Test condition Min. Typ. Max. Unit

access to the system register.

=11 kΩ, DSQIN=LOW, VI=12 V, IO = 50

SEL

= 25 °C. See software

J

A

F

TH-L

TH-H

TH-L

TH-H

Amplitude diagnostic low threshold

Amplitude diagnostic high threshold

Frequency diagnostic low thresholds

Frequency diagnostic high thresholds

NB: if the 22 kHz tone parameters are lower or higher than the above limits the TMON I²C bit is set to 1.

DETIN pin AC coupled 200 300 400 mV

DETIN pin AC coupled 900 1100 1200 mV

DETIN pin AC coupled 13 16.5 20 kHz

DETIN pin AC coupled 24 29.5 38 kHz

22/30

LNBH24 Typical performance characteristics

9 Typical performance characteristics

Refer to the typical application circuit in Figure 4, TJ from 0 to 85 °C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R 50 mA, unless otherwise stated. Typical values are referred to T

Figure 8. Output voltage vs. temperature Figure 9. Output voltage vs. temperature

14

13.8

13.6

13.4

[V]

OUT

13.2

V

13

12.8

12.6

-10 0 10 20 30 40 50 60 70 80 90

VCC=12 V

=50 mA

I

OUT

=13 V range

V

OUT

EN=1, VSEL=LLC=0

T [°C]

15

14.8

14.6

14.4

[V]

OUT

14.2

V

14

13.8

13.6

= 11 kΩ, DSQIN=LOW, VI = 12 V, I

SEL

= 25 °C, V

J

VCC=12 V

VCC=12 V I

I

=50 mA

OUT

=14 V range

V

OUT

EN=LLC=1, VSEL=0

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

OUT=VoRX

OUT

.

=

Figure 10. Output voltage vs. temperature Figure 11. Output voltage vs. temperature

19.2

VCC=12 V

VCC=12 V I

I

=50 mA

19

OUT

V

=18 V range

OUT

18.8

18.6

[V]

OUT

18.4

V

18.2

18

EN=VSEL=1, LLC=0

17.8

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

Figure 12. Load regulation vs. temperature Figure 13. Supply current vs. temperature

0

-20

-40

-60

-80

-100

Load [mV]

-120

-140

V

=12 V, I

= from 50 to 750 mA

OUT

T [°C]

V

CC

-160

-10 0 10 20 30 40 50 60 70 80 90

20.3

VCC=12 V

20.1

=50 mA

I

OUT

=19.5 V range

V

OUT

19.9

19.7

[V]

19.5

OUT

19.3

V

19.1

18.9

18.7

18.7 EN=VSEL=LLC=1

EN=VSEL=LLC=1

18.5

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

40

VCC=12V, I

=No Load

VCC=12V, I

=No Load

OUT

35

30

25

[mA]

20

IN

I

15

10

5

0

-10 0 10 20 30 40 50 60 70 80 90

OUT

Both Sections Enabled with EN=LLC=VSEL=1, TEN=TTX=0

T [°C]

23/30

Typical performance characteristics LNBH24

Figure 14. Supply current vs. temperature Figure 15. Supply current vs. temperature ON

VCC=12 V, I

70

60

50

40

[mA]

IN

I

30

20

10

0

-10 0 10 20 30 40 50 60 70 80 90

=No Load

OUT

Both Sections Enabled with EN=TEN=TTX=LLC=VSEL=1

T [°C]

140

130

120

110

100

[ms]

90

ON

T

80

70

60

50

40

-10 0 10 20 30 40 50 60 70 80 90

time vs. temperature

V

= 12 V, V

= Shorted to GND

OUT

V

CC

T [°C]

Figure 16. Dynamic overload protection OFF

1300

1200

1100

1000

900

[ms]

800

OFF

T

700

600

500

400

-10 0 10 20 30 40 50 60 70 80 90

time vs. temperature

V

= 12 V, V

= Shorted to GND

OUT

V

CC

T [°C]

Figure 18. Output current limiting vs.

1000

950

900

[mA]

850

MAX

I

800

750

temperature

VCC= 12 V, R

-10 0 10 20 30 40 50 60 70 80 90

= 11 kohm

SEL

T [°C]

Figure 17. Output current limiting vs. R

1.4

VCC= 12 V

1.2

1

0.8

[A]

0.6

MAX

I

0.4

0.2

0

10 12 14 16 18 20 2 2 24 26 28 30 32

R

[kOhm]

R

[kOhm]

SEL

Figure 19. Output current limiting vs.

temperature

550

500

450

[mA]

400

MAX

I

350

VCC=12 V, R

300

-10 0 10 20 30 40 50 60 70 80 90

= 22 Kohm

SEL

T [°C]

SEL

24/30

LNBH24 Typical performance characteristics

Figure 20. Tone frequency vs. temperature Figure 21. Tone amplitude vs. temperature

28

V

= 12 V, I

OUT

= 50 mA

T [°C]

V

CC

26

24

[kHz]

22

TONE

F

20

18

EN=TEN=TTX=1

16

-10 0 10 20 30 40 50 60 70 80 90

Figure 22. Tone duty cycle vs. temperature Figure 23. Tone rise time vs. temperature

55

V

CC

54

53

52

51

[%]

50

TONE

49

D

48

47

46

EN=TEN=TTX=1

45

-10 0 10 20 30 40 50 60 70 80 90

1000

V

= 12 V, I

OUT

= 50 mA

T [°C]

V

CC

900

800

[mV]

700

TONE

A

600

500

EN=TEN=TTX=1

400

-10 0 10 20 30 40 50 60 70 80 90

14

V

CC

13

12

11

10

9

[µs]

r

t

8

7

6

5

EN=TEN=TTX=1

4

-10 0 10 20 30 40 50 60 70 80 90

Figure 24. Tone fall time vs. temperature Figure 25. Output backward current vs.

14

V

= 12 V, I

OUT

= 50 mA

T [°C]

V

CC

13

13 12

12

11

11 10

10

9

[µs]

f

t

8

8 7

7

6

6 5

5

EN=TEN=TTX=1

4

-10 0 10 20 30 40 50 60 70 80 90

0

-1

[mA]

-2

OBK

I

-3

-4

-10 0 10 20 30 40 50 60 70 80 90

temperature

V

= 12 V, V

V

= 12 V, V

CC

EN=0

= 21 V externally forced

OBK

T [°C]

25/30

Typical performance characteristics LNBH24

Figure 26. DC-DC converter efficiency vs.

100

90

80

70

Eff [%]

60

50

40

-10 0 10 20 30 40 50 60 70 80 90

temperature

V

= 12 V, I

OUT

= 750 mA

V

CC

EN=VSEL=LLC=1

T [°C]

Figure 28. DSQIN tone enable transient

DSQIN

response

Figure 27. 22 kHz tone waveform

LNB

OUT

V

= 12 V

V

= 12 V

CC

EN=TEN=TTX=1

Figure 29. DSQIN tone disable transient

response

V

= 12 V

V

= 12 V

CC

EN=TTX=1, TEN=0

DSQIN

LNB

OUT

V

= 12 V

V

= 12 V

CC

EN=TTX=1, TEN=0

LNB

OUT

26/30

LNBH24 Package mechanical data

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK®

27/30

Package mechanical data LNBH24

PowerSSO-36 mechanical data

Dim.

Min. Typ. Max. Min. Typ. Max.

mm. inch.

A 2.15 2.47 0.085 0.097

A2 2.15 2.40 0.085 0.094

a1 0 0.075 0 0.003

b 0.18 0.36 0.007 0.014

c0.23 0.32 0.009 0.013

D 10.10 10.50 0.398 0.413

E 7.4 7.6 0.291 0.299 e 0.5 0.020

e38.5 0.335

F2.3 0.091

G 0.075 0.003

G1 0.06 0.002

H 10.1 10.5 0.398 0.413

h 0.4 0.016

L 0.55 0.85 0.022 0.033 M4.3 0.169 N 10° 10° O 1.2 0.047 Q0.8 0.031

S 2.9 0.114

T 3.65 0.144 U 1.0 0.039

X 4.1 4.7 0.161 0.185

Y4.9 5.5 0.193 0.217

(1) “D and E” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15 mm. (0.006”)

28/30

7655059

LNBH24 Revision history

11 Revision history

Table 14. Document revision history

Date Revision Changes

11-Feb-2008 1 Initial release.

27-Aug-2008 2 Modified mechanical data on page 28.

07-Apr-2009 3 Modified Y dimension mechanical data on page 28.

29/30

LNBH24

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30/30

Datasheet LNBH24 Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Block diagram

Figure 1. Block diagram

2 Introduction

2.1 Application information

2.2 DiSEqC™ data encoding and decoding

2.3 DiSEqC™ 2.0 implementation

2.4 DiSEqC™ 1.X implementation

2.5 Data encoding through external tone generator (EXTM)

Figure 2. EXTM timings

2.7 Output voltage selection

2.8 Diagnostic and protection functions

2.9 Output voltage diagnostic

2.10 22 kHz tone diagnostic

2.11 Minimum output current diagnostic

2.12 Output current limit selection

2.13 Over-current and short-circuit protection and diagnostic

2.14 Thermal protection and diagnostic

3 Pin configuration

Figure 3. Pin connections

Table 2. Pin description

4 Maximum ratings

Table 3. Absolute maximum ratings

Table 4. Thermal data

5 Application circuit

Figure 4. Typical application circuit

Table 5. Bill of material (valid for A and B sections except for C1, C2, C7, C8 and R1)

6.1 Data validity

6.2 Start and stop condition

6.3 Byte format

6.4 Acknowledge

6.5 Transmission without acknowledge

7 LNBH24 software description

7.1 Interface protocol

7.2 System register (SR, 1 Byte for each section A and B)

Table 6. Truth table

Table 7. Register

7.6 Address pin

7.7 DiSEqC™ implementation for each section A/B

8 Electrical characteristics

Table 8. Electrical characteristics of sections A/B

Table 10. Address pins characteristics

Table 11. Output voltage diagnostic (VMON bit) characteristics of sections A/B

Table 12. Minimum output current diagnostic (IMON bit) characteristics of sections A/B

Table 13. 22KHz tone diagnostic (TMON bit) characteristics of sections A/B

9 Typical performance characteristics

Figure 10. Output voltage vs. temperature Figure 11. Output voltage vs. temperature

Figure 12. Load regulation vs. temperature Figure 13. Supply current vs. temperature

Figure 14. Supply current vs. temperature Figure 15. Supply current vs. temperature ON

Figure 20. Tone frequency vs. temperature Figure 21. Tone amplitude vs. temperature

Figure 22. Tone duty cycle vs. temperature Figure 23. Tone rise time vs. temperature

Figure 24. Tone fall time vs. temperature Figure 25. Output backward current vs.

Figure 27. 22 kHz tone waveform

10 Package mechanical data

11 Revision history

Table 14. Document revision history