Datasheet LNBH23 Datasheet (ST)

LNBs supply and control IC with step-up and I²C interface

Features

■ Complete interface between LNB and I²C bus

■ Built-in DC-DC converter for single 12 V supply

operation and high efficiency (typ. 93% @ 0.75
A), with integrated NMOS

■ Selectable output current limit by external

resistor

■ Compliant with main satellite receiver systems

specifications

■ New accurate built-in 22 kHz tone generator

suits widely accepted standards (patent
pending)

■ Fast oscillator start-up facilitates DiSEqC™

encoding

■ Built-in 22 kHz tone detector supports bi-

directional DiSEqC™ 2.0

■ Very low-drop post regulator and high

efficiency step-up PWM with integrated power
NMOS allow low power losses

■ Two output pins suitable to by-pass the output

R-L filter and avoid any tone distortion (R-L
filter as per DiSEqC™ 2.0 specs, see typ.
application circuits)

■ Overload and over-temperature internal

protections with I²C diagnostic bits

■ Output voltage and output current level

diagnostic feedback by I²C bits

■ LNB short circuit dynamic protection

■ ± 4 kV ESD tolerant on output power pins

LNBH23

PowerSSO-24

(Exposed pad)

Description

Intended for analog and digital satellite
receivers/sat-TV, sat-PC cards, the LNBH23 is a
monolithic voltage regulator and interface IC,
assembled in PowerSSO-24 ePAD and QFN32 (5
x 5 mm.) ePAD, specifically designed to provide
the 13/18 V power supply and the 22 kHz tone
signalling to the LNB down-converter in the
antenna dish or to the multi-switch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I²C
standard interfacing.

QFN32 (5 x 5 mm.)

(Exposed pad)

Table 1. Device summary

Order code Package Packaging

LNBH23PPR PowerSSO-24 (Exposed pad) Tape and reel

LNBH23QTR QFN32 (Exposed pad) Tape and reel

November 2010 Doc ID 13356 Rev 7 1/32

www.st.com

32

Contents LNBH23

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 DiSEqC™ data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 DiSEqC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 DiSEqC™ 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 Data encoding by external tone generator (EXTM) . . . . . . . . . . . . . . . . . . 6

2.5 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.6 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.8 Output voltage diagnostic - VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.9 22 kHz tone diagnostic - TMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10 Minimum output current diagnostic - IMON . . . . . . . . . . . . . . . . . . . . . . . . 7

2.11 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.12 Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 8

2.13 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 LNBH23 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.2 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/32 Doc ID 13356 Rev 7

LNBH23 Contents

7.3 Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.4 Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17

7.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.7 DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Doc ID 13356 Rev 7 3/32

Block diagram LNBH23

V

V

1 Block diagram

Figure 1. Block diagram

LX

LX

P-GND

P-GND

Vup

Vup

VoRX

VoRX

VoTX

VoTX

EXTM

EXTM

DSQIN

DSQIN

CTRL

CTRL

Rsense

Rsense

TTX

TTXTTX

SDA SCL

ADDR

ADDR

PWM

Controller

PWM

Controller

EN

EN

VSEL

VSEL

VSEL

VSEL

TTX

TTX

ITEST

ITEST

VOUT Control

VOUT Control

TEN

Linear Post-reg

Linear Post-reg
+Modulator

+Modulator
+Protections

+Protections
+Diagnostics

+Diagnostics

22KHz

22KHz

22KHz
Oscill.

Oscill.

Oscill.

LNBH23

LNBH23

TEN

SDA SCL

I²C interface

I²C interface

I²C Diagnostics

I²C Diagnostics

22KHz Tone

22KHz Tone
Amp. Diagn.

Amp. Diagn.

22KHz Tone

22KHz Tone
Freq. Detector

Freq. Detector

BypVcc Vcc-LISEL TTX

BypVcc Vcc-LBypVcc Vcc-LISEL TTX

Preregulator

Preregulator
+U.V.lockout

+U.V.lockout
+P.ON reset

+P.ON reset

EN

EN

DETIN

DETIN

DSQOUT

DSQOUT

A-GND

A-GND

4/32 Doc ID 13356 Rev 7

LNBH23 Application information

2 Application information

This IC has a built-in DC-DC step-up converter with integrated NMOS that, from a single
source from 8 V to 15 V, generates the voltages (V
work at a minimum dissipated power of 0.375 W Typ. @ 500 mA load (the linear post­regulator drop voltage is internally kept at V

UP-VORX

circuit will disable the whole circuit when the supplied V
V typically).

) that let the linear post-regulator to

UP

=0.75 V typ.). An under voltage lockout

drops below a fixed threshold (6.7

CC

Note: In this document the output voltage (V

post-regulator output (V

ORX

pin).

) is intended as the voltage present at the linear

O

2.1 DiSEqC™ data encoding and decoding

The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance
to the standards, and can be selected by I²C interface TTX bit (or TTX pin) and activated by
a dedicated pin (DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN
I²C bit in case the 22 kHz presence is requested in continuous mode. In stand-by condition
(EN bit LOW) The TTX function must be disabled setting TTX to LOW.

2.2 DiSEqC™ 2.0 implementation

The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC™ 2.0 interfacing
(see Note 1). It’s input pin (DETIN) must be AC coupled to the DiSEqC™ BUS, and
extracted PWK data are available on the DSQOUT pin. To comply to the bi-directional
DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH23 is
provided with two output pins, one for the dc voltage output (V
tone transmission (V
while the V

provides the 13/18 V output voltage. This allows the 22 kHz Tone to pass

oRX

without any losses due to the R-L filter impedance (see Figure 4 typ. application circuit).
During the 22 kHz transmission, in DiSEqC™ 2.0 applications, activated by DSQIN pin or by
the TEN bit, the V
controlled both through the TTX pin and by I²C bit. As soon as the tone transmission is
expired, the V

oTX

kHz receiving mode. The 13/18 V power supply is always provided to the LNB from the V
pin through the R-L filter.

). The V

oTX

pin must be preventively set ON by the TTX function. This can be

oTX

must be activated only during the tone transmission

oTX

must be disabled by setting the TTX to LOW to set the device in the 22

) and one for the 22 kHz

oRX

oRX

2.3 DiSEqC™ 1.X implementation

When the LNBH23 is used in DiSEqC™ 1.x applications the R-L filter is always needed for
the proper operation of the new 22 kHz tone generator (patent pending. See application
circuit). Also in this case, the TTX function must be preventively enabled before to start the
22 kHz data transmission and disabled as soon as the data transmission has been expired.
The tone can be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal
circuit activates the 22 kHz tone on the V
TTL signal presence on the DSQIN pin, and it stops with 1 cycles ±25 µs delay after the TTL
signal is expired.

Doc ID 13356 Rev 7 5/32

oTX

output with 0.5 cycles ±25 µs delay from the

Application information LNBH23

2.4 Data encoding by external tone generator (EXTM)

In order to improve design flexibility an external tone input pin is available (EXTM). The
EXTM is a logic input pin which activates the 22 kHz tone output, on the V
the LNBH23 integrated tone generator (similarly to the DSQIN pin function). As a matter of
fact, the output tone waveform characteristics will be always internally controlled by the
LNBH23 tone generator and the EXTM signal will be used just as a timing control of the
DiSEqC tone data encoding on the V
for the proper control of the EXTM pin function. Before to send the TTL signal on the EXTM
pin, the V

tone generator must be previously enabled through the TTX function (TTX pin

oTX

or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal
code, it activates the 22 kHz tone on the V
TTL signal presence on the EXTM pin, and it stops with 2 cycles ±25 µs delay after the TTL
signal is expired. Refer to the below Figure 2

Figure 2. EXTM waveform

output. A TTL compatible 22 kHz signal is required

oTX

output with 1.5 cycles ±25 µs delay from the

oTX

pin, by using

oTX

2.5 I²C interface

The main functions of the IC are controlled via I²C bus by writing 8 bits on the system
register (SR 8 bits in write mode). On the same register there are 8 bits that can be read
back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the
diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF)
while, three will report the last output voltage register status (EN, VSEL, LLC) received by
the IC (see below diagnostic functions section).

2.6 Output voltage selection

When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the V
LNBs. Additionally, the LNBH23 is provided with the LLC I²C bit that increases the selected
voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable.
The LNBH23 is also compliant to the USA LNB power supply standards. In order to allow
fast transition of the output voltage from 18 V to 13 V and vice versa, the LNBH23 is
provided with the VCTRL TTL pin which keeps the output to 13 V when it is set LOW and to
18 V when it is set HIGH or floating. V
to use the VCTRL pin to switch the output voltage level. If VCTRL=1 or floating V
(or 19.5 V if LLC=1). With VCTRL=0 V
VCTRL pin controls only the linear regulator V
controlled only through the VSEL and LLC I²C bits, that is: Even if VCTRL=0 (keeping

bit (Voltage SELect) for remote controlling of non-DiSEqC

SEL

and, if required, LLC bits must be set HIGH before

SEL

=13.4 V (LLC= either 0 or 1). Be aware that the

oRX

stage while the step-up VUP voltage is

oRX

oRX

=18.5 V

6/32 Doc ID 13356 Rev 7

LNBH23 Application information

V

=13.4 V) you will have VUP=19.25 V typ when V

oRX

=1 and 20.25 V with V

SEL

=LLC=1.

SEL

This means that VCTRL=0 must be used only for short time to avoid the higher power
dissipation. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must be set
LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during
the stand-by condition).

2.7 Diagnostic and protection functions

The LNBH23 has 5 diagnostic internal functions provided via I²C bus by reading 5 bits on
the system register (SR bits in read mode). All the diagnostic bits are, in normal operation
(no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature
and over-load protections status (OTF and OLF) while, the remaining 3 bits, are dedicated to
the output voltage level (VMON), 22 kHz tone (TMON) and to the minimum load current
diagnostic function (IMON).

2.8 Output voltage diagnostic - VMON

When V

=0 or 1 and LLC=0, the output voltage pin (V

SEL

) is internally monitored and, as

oRX

long as the output voltage level is below the guaranteed limits the VMON I²C bit is set to "1".
The output voltage diagnostic is valid only with LLC=0. Any VMON information with LLC=1
must be disregarded by the MCU.

2.9 22 kHz tone diagnostic - TMON

The 22 kHz tone can be internally detected and monitored if DETIN pin is connected to the
LNB output bus (see typical application circuits Figure 4) through a decoupling capacitor.
The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude
and/or the tone frequency is out of the guaranteed limits (see TMON limits in the electrical
characteristics Ta bl e 1 3), the TMON I²C bit is set to "1".

2.10 Minimum output current diagnostic - IMON

In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH23 is provided with a minimum output current flag by the
IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA
typically with ITEST=1 and 6 mA with ITEST=0. The minimum current diagnostic function
(IMON) is always active. In order to make it work even in a multi-IRD configuration (multi­switch), where the supply current could be sunk only from the higher supply voltage
connected to the multi-switch box, the LNBH23 is provided with the AUX I²C bit which can
be set HIGH, in write mode by the MCU, before to read the IMON I²C bit status, to force the
LNBH23 output voltage as the highest voltage on the bus (22 V typ.) during the minimum
current diagnostic phase. When the AUX bit is set to HIGH, the V
V

is set to 22.75 V (V

UP

the AUX function is used to force the V
LOW as soon as the minimum current test phase is expired, so that the V
controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the
IMON function must be used only with the 22 kHz tone transmission deactivated
(TEN=TTX=0 and DSQIN=LOW), otherwise the IMON bit could be erroneously set to 0 even
if the output current is below the minimum current thresholds (6 mA or 12 mA). Any TMON
information with 22 kHz tone enabled must be disregarded by the MCU.

UP

= V

+0.75 V typ.) independently of the VSEL/LLC bits status. If

oRX

to 22 V, it is recommended to set the AUX bit to

oRX

is set to 22 V (typ.) and

oRX

voltage will be

oRX

Doc ID 13356 Rev 7 7/32

Application information LNBH23

2.11 Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to
I

pin. The resistor value defines the output current limit by the equation:

SEL

I

[A] = 10000/R

MAX

where R

SEL

limit threshold is 1.0 A typ with R

SEL

is the resistor connected between I

=10 kΩ. The above equation defines the typical

SEL

and GND. The highest selectable current

SEL

threshold value.

2.12 Over-current and short circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short circuit condition,
the device is provided with a dynamic short circuit protection. It is possible to set the short
circuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C SR. When the PCL (pulsed current limiting) bit is set lo LOW, the over current
protection circuit works dynamically: as soon as an overload is detected, the output current
is provided for 90 ms (typ.), after that the output is set in shut-down for a time T
typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the system register is set to
"1". After this time has elapsed, the output is resumed for a time T
(typ.). At the end of T
through T

and TON. At the end of a full TON in which no overload is detected, normal

OFF

, if the overload is still detected, the protection circuit will cycle again

ON

=1/10 T

ON

operation is resumed and the OLF diagnostic bit is reset to LOW. Typical T
990 ms and an internal timer determines it. This dynamic operation can greatly reduce the
power dissipation in short circuit condition, still ensuring excellent power-on start-up in most
conditions. However, there could be some cases in which a highly capacitive load on the
output may cause a difficult start-up when the dynamic protection is chosen. This can be
solved by initiating any power start-up in static mode (PCL=1) and, then, switching to the
dynamic mode (PCL=0) after a chosen amount of time depending on the output
capacitance. Also in static mode, the diagnostic OLF bit goes to "1" when the current clamp
limit is reached and returns LOW when the overload condition is cleared.

OFF of

= 90 ms

OFF

ON +TOFF

time is

2.13 Thermal protection and diagnostic

The LNBH23 is also protected against overheating: when the junction temperature exceeds
150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic
OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when
the junction is cooled down to 135 °C (typ.).

Note: 1 External components are needed to comply to bidirectional DiSEqC™ bus hardware

requirements. Full compliance of the whole application with DiSEqC™ specifications is not
implied by the use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT. I²C is
trademark of Philips Semiconductors.

8/32 Doc ID 13356 Rev 7

LNBH23 Pin configuration

3 Pin configuration

Figure 3. Pin connections (top view for PowerSSO-24, bottom view for QFN32)

24

24

NC

DETIN

DETIN

VCTRL

VCTRL

P-GND

P-GND

SDA

SDA

SCL

SCL

ADDR

ADDR

DSQOUT

DSQOUT

DSQIN

DSQIN

1

1

2

2

NC

NC

3

3

NC

NC

4

4

NC

NC

5

5

LX

LX

6

6

7

7

8

8

9

9

10

10

11

11

12

12

NC

23

23

ISEL

ISEL

22

22

VUP

VUP

21

21

NC

NC

20

20

VoTX

VoTX

19

19

VoRX

VoRX

18

18

A-GND

A-GND

17

17

VCC

VCC

16

16

VCC-L

VCC-L

15

15

BYP

BYP

14

14

TTX

TTX

13

13

EXTM

EXTM

PowerSSO-24

QFN32 (5 x 5 mm.)

Table 2. Pin description

Pin n° for

QFN32

19 17 V

18 16 V

27 22 V

21 19 V

22 20 V

12 12 DSQIN DiSEqC input

14 14 TTX TTX enable

29 1 DETIN

Pin n° for
PSSO-24

Symbol Name Function

CC

CC–L

Supply input 8 to 15 V IC DC-DC power supply.

Supply input 8 to 15 V analog power supply.

4 6 LX N-MOS drain Integrated N-Channel power MOSFET drain.

Input of the linear post-regulator. The voltage on this pin is

UP

Step-Up voltage

monitored by the internal step-up controller to keep a
minimum dropout across the linear pass transistor.

oRX

Output port for 22

oTX

LDO output port

kHz tone TX

Output of the integrated low drop linear post-regulator. See
truth tables for voltage selections and description.

TX Output to the LNB. See truth tables for selection.

6 8 SDA Serial data Bi-directional data from/to I²C bus.

9 9 SCL Serial clock Clock from I²C bus.

This pin will accept the DiSEqC code from the main
microcontroller. The LNBH23 will use this code to modulate
the internally generated 22 kHz carrier. Set to ground if not
used.

This pin can be used, as well as the TTX I²C bit of the system
register, to control the TTX function enable before to start the
22 kHz tone transmission. Set floating or to GND if not used.

Tone decoder

input

22 kHz tone decoder Input, must be AC coupled to the
DiSEqC 2.0 bus.

Doc ID 13356 Rev 7 9/32

Pin configuration LNBH23

Table 2. Pin description (continued)

Pin n° for

QFN32

Pin n° for
PSSO-24

Symbol Name Function

Open drain output of the tone decoder to the main

11 11 DSQOUT DiSEqC output

microcontroller for DiSEqC 2.0 data decoding. It is LOW
when tone is detected on DETIN pin.

13 13 EXTM

External

modulation

External modulation logic input pin which activates the 22
kHz tone output on the V

Needed for internal pre-regulator filtering. The BYP pin is

15 15 BYP

By-pass

capacitor

intended only to connect an external ceramic capacitor. Any
connection of this pin to external current or voltage sources
may cause permanent damage to the device.

10 10 ADDR Address setting

Two I²C bus addresses available by setting the Address pin
level voltage. See address pin characteristics Ta bl e 1 0

The resistor “RSEL” connected between ISEL and GND

28 23 ISEL Current selection

defines the linear regulator current limit threshold by the
equation: Imax(typ.)=10000/ RSEL.

13V-18V linear regulator V

30 2 VCTRL

Output voltage

control

only with V

19.5V if LLC=1). If VCTRL=0 than V
or 1). Leave floating if not used. Do not connect to ground if

=1. If VCTRL=1 or floating V

SEL

not used.

5 7 P-GND Power ground DC-DC converter power ground.

pin. Set to ground if not used.

oTX

switch control. To be used

oRX

oRX

=18.5V (or

oRX

=13.4V (LLC=either 0

Epad Epad Epad Exposed pad

To be connected with power grounds and to the ground layer
through vias to dissipate the heat.

20 18 A-GND Analog ground Analog circuits ground.

1, 2, 3, 7,
8, 16, 17,

23, 24,
25, 26,

3, 4, 5,

21, 24

N.C. Not connected Not internally connected pins.

31, 32

10/32 Doc ID 13356 Rev 7

LNBH23 Maximum ratings

4 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

, VCCDC power supply input voltage pins -0.3 to 16 V

CC-L

V

UP

I

O

V

oRX

V

oTX

V

LX LX input voltage -0.3 to 24 V

DC input voltage -0.3 to 24 V

Output current Internally Limited mA

DC output pin voltage -0.3 to 25 V

Tone output pin voltage -0.3 to 25 V

Logic input voltage (TTX, SDA, SCL, DSQIN, EXTM, VCTRL,

I

ADDR)

-0.3 to 7 V

V

DETIN

V

V

OH

BYP

Detector input signal amplitude 2 V

Logic high output voltage (DSQOUT) -0.3 to 7 V

Internal reference pin voltage (Note 2) -0.3 to 4.6 V

PP

ISEL Current selection pin voltage -0.3 to 4.6 V

T

STG

T

ESD

Storage temperature range -50 to 150 °C

Operating junction temperature range -25 to 125 °C

J

ESD rating with human body model (HBM) for all pins unless
6, 19, 20 (for PSSO24) and unless 4, 21, 22 (for QFN32)

ESD rating with human body model (HBM) for pins 19, 20 (for
PSSO24) and pins 21, 22 (for QFN32)

ESD rating with human body model (HBM) for pin 6 (for
PSSO24) and pin 4 (for QFN32)

2

4

0.6

kV

Note: 1 Absolute maximum ratings are those values beyond which damage to the device may occur.

These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal.

2 The BYP pin is intended only to connect an external ceramic capacitor. Any connection of

this pin to external current or voltage sources may cause permanent damage to the device.

Table 4. Thermal data

Symbol Parameter QFN32 PowerSSO-24 Unit

R

R

thJC

thJA

Thermal resistance junction-case 2 2 °C/W

Thermal resistance junction-ambient (PowerSSO-

24) with device soldered on 2s2p PC Board

35 30 °C/W

Doc ID 13356 Rev 7 11/32

Application circuit LNBH23

V

5 Application circuit

Figure 4. Typical application circuit

D3 1N4001D3 1N4001

Ferrite Bead Filter

Ferrite Bead Filter

L2 suggested part number:

L2 suggested part number:

MURATA BL01RN1-A62

MURATA BL01RN1-A62
Panasonic EXCELS A35

Panasonic EXCELS A35

in

12V

C1
100µF

Tone Enable

TTX Enable

C4
470nFC4470nF

Ceramic

D1

D1

STPS130A

STPS130A

L1=22µH

C2
100nF

Ceramic

C3
100µFC3100µF

L2

100µF

C7

C7
100nF

100nF

Ceramic

Ceramic

C5

R1

100Ohm

C8

C8
220nF

220nF

Ceramic

Ceramic

I2C Bus

C6
470nF

Ceramic

{

Vup

LX

Vcc

Vcc-

SDA

SCL

DSQIN

TTX

LNBH23

L

P-GND A-GND

VoTX

VoRX

DETIN

Byp

EXTM

ADDR

DSQOUT

VCTRL

ISEL

D4

D4
BAT43

BAT43

C10

C10
220nF

220nF

Ceramic

Ceramic

C9
10µFC910µF

R3
10kOhm

C11
220nF

Ceramic

13/18

R2 (RSEL)
11kOhm

D2
BAT43D2BAT43

C13

C13
10nF

10nF

L3

270µH

R4
15 Ohm

C12

10nF

to LNB

Table 5. Bill of material

Component Notes

R1, R4 1/4W resistors. Refer to the typical application circuit for the relative values

R2 (RSEL), R3 1/4W resistors. Refer to the typical application circuit for the relative values

C1 25V electrolytic capacitor, 100µF or higher is suitable.

C9 10µF, >35V electrolytic capacitor

C3, C5 100µF, >25V electrolytic capacitor, ESR in the 150mΩ to 350mΩ range

C2, C4, C6, C7, C8, C10,

C11, C12, C13

D1

D2, D4 BAT43, 1N5818, or any schottky diode with I

>25V ceramic capacitors. Refer to the typ. appl. circuit for the relative values

STPS130A or any similar schottky diode with V
I

F(AV)

> I

OUT_MAX

x (V

UP_MAX/VIN_MIN

)

RRM

F(AV)

>25V and I

> 0.2A, V

higher than:

F(AV)

> 25 V, VF < 0.5 V

RRM

D3 1N4001 or equivalent

L1

22 µH Inductor with I

Equation 1)

sat>Ipeak

where I

is the boost converter peak current (see

peak

12/32 Doc ID 13356 Rev 7

LNBH23 Application circuit

Table 5. Bill of material (continued)

Component Notes

FERRITE BEAD, Panasonic-EXCELS A35 or Murata-BL01RN1-A62 or Taiyo-Yuden-

L2

L3 220µH-270µH Inductor with current rating higher than rated output current

BKP1608HS600 or equivalent with similar or higher impedance and current rating
higher than 2A

To calculate the boost converter peak current (I

Equation 1

) of L1, use the following formula:

PEAK

Doc ID 13356 Rev 7 13/32

I²C bus interface LNBH23

6 I²C bus interface

Data transmission from main MCU to the LNBH23 and vice versa takes place through the 2
wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).

6.1 Data validity

As shown in Figure 5, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.

6.2 Start and stop condition

As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.

6.3 Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.

6.4 Acknowledge

The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7). The peripheral (LNBH23) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate acknowledge
after the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer. The LNBH23 won't generate acknowledge if the
V

supply is below the under voltage lockout threshold (6.7 V typ.).

CC

6.5 Transmission without acknowledge

Avoiding to detect the acknowledges of the LNBH23, the MCU can use a simpler
transmission: simply it waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach of course is less protected from misworking and
decreases the noise immunity.

14/32 Doc ID 13356 Rev 7

LNBH23 I²C bus interface

Figure 5. Data validity on the I²C bus

Figure 6. Timing diagram of I²C bus

Figure 7. Acknowledge on the I²C bus

Doc ID 13356 Rev 7 15/32

LNBH23 software description LNBH23

7 LNBH23 software description

7.1 Interface protocol

The interface protocol comprises:

● A start condition (S)

● A chip address byte (the LSB bit determines read(=1)/write(=0) transmission)

● A sequence of data (1 byte + acknowledge)

● A stop condition (P)

Chip address Data

MSB LSB MSB LSB

S000101XR/WACK ACKP

ACK = Acknowledge

S = Start

P = Stop

R/W = 1/0, Read/Write bit

X = 0/1, two selectable addresses available through ADDR pin (see Address pin
characteristics Ta bl e 1 0)

7.2 System register (SR, 1 byte)

Mode MSB LSB

Write PCL TTX TEN LLC VSEL EN ITEST AUX

Read IMON VMON TMON LLC VSEL EN OTF OLF

Write = control bits functions in write mode

Read= diagnostic bits in read mode.

All bits reset to 0 at power On

7.3 Transmitted data (I²C bus write mode)

When the R/W bit in the chip address is set to 0, the main MCU can write on the system
register (SR) of the LNBH23 via I²C bus. All and 8 bits are available and can be written by
the MCU to control the device functions as per the below truth table.

16/32 Doc ID 13356 Rev 7

LNBH23 LNBH23 software description

Table 6. Truth table

PCL TTX TEN LLC VSEL EN ITEST AUX Function

00010V

00110V

01010V

01110V

XX1X1V

= 13.4V, VUP=14.15V, (VUP-V

oRX

= 18.5V, VUP=19.25V, (VUP-V

oRX

= 14.4V, VUP=15.15V, (VUP-V

oRX

= 19.5V, VUP=20.25V, (VUP-V

oRX

= 22V, VUP=22.75V, (VUP-V

oRX

oRX

oRX

oRX

oRX

oRX

=0.75V)

0 1 22 kHz controlled by DSQIN pin (only if TTX=1)

1 1 1 22 kHz tone output is always activated

output is ON, V

V

01

11V

oRX

OFF

output is ON, V

oRX

Tone generator output is

oTX

Tone generator output is ON

oTX

0 1 Pulsed (Dynamic) current limiting is selected

1 1 Static current limiting is selected

XX10

XX11

Minimum output current diagnostic threshold = 6mA
typ.

Minimum output current diagnostic threshold = 12mA
typ.

X X X X X 0 X X Power block disabled

=0.75V)

=0.75V)

=0.75V)

=0.75V)

X = don't care
All values are typical unless otherwise specified
Valid with TTX pin floating or to GND

7.4 Diagnostic received data (I²C read mode)

LNBH23 can provide to the MCU Master a copy of the diagnostic system register
information via I²C bus in read mode. The read mode is master activated by sending the
chip address with R/W bit set to 1. At the following master generated clocks bits, LNBH23
issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the
master can:

● Acknowledge the reception, starting in this way the transmission of another byte from

the LNBH23

● No acknowledge, stopping the read mode communication

Three bits of the register are read back as a copy of the corresponding write output voltage
register status (LLC, VSEL, EN), while, the other five bits convey diagnostic information
about the over-temperature (OTF), output voltage level (VMON), output over-load (OLF),
Minimum output current presence (IMON) and 22 kHz tone (TMON). In normal operation the
diagnostic bits are set to zero, while, if a failure is occurring, the corresponding bit is set to
one. At start-up all the bits are reset to zero.

Doc ID 13356 Rev 7 17/32

LNBH23 software description LNBH23

0/1

< 135°C, normal operation

J

> 150°C, power blocks disabled

J

0IO < I

1I

> I

O

These bits are set to 1 if the relative parameter
is out of the specification limits.

, normal operation

OMAX

, Overload Protection triggered

OMAX

(3)

0/1

These bits are read

exactly the same as

they were left after

last write operation

0T

1T

Table 7. Register

IMON VMON TMON LLC VSEL EN OTF OLF Function

(2)

0/1

1. Values are typical unless otherwise specified

2. IMON information must be disregarded if 22 kHz TONE output is enabled

3. VMON information must be disregarded if LLC=1 (valid only if LLC=0)

7.5 Power-on I²C interface reset

I²C interface built in LNBH23 is automatically reset at power-on. As long as the VCC stays
below the under voltage lockout (UVL) threshold (6.7 V), the interface does not respond to
any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the
power blocks disabled. Once the V
operative and the SR can be configured by the main MCU. This is due to 500 mV of
hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset
circuit.

rises above 7.3 V typ. The I²C interface becomes

CC

(1)

(1)

7.6 Address pin

It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL
compatible and can be set as per hereafter address pin characteristics Ta bl e 1 0 .

7.7 DiSEqC™ implementation

LNBH23 helps system designer to implement bi-directional DiSEqC 2.0 protocol by allowing
an easy PWK modulation/demodulation of the 22 kHz carrier. Between the LNBH23 and the
main MCU the PWK data is exchanged using logic levels that are compatible with both 3.3 V
and 5 V MCU. This data exchange is made through two dedicated pins, DSQIN and
DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK
modulation as accurate as possible. These two pins should be directly connected to two I/O
pins of the MCU, thus leaving to the firmware the task of encoding and decoding the PWK
data in accordance to the DiSEqC protocol.
Full compliance of the system to the specification is thus not implied by the bare use of the
LNBH23. The system designer should also take in consideration the bus hardware
requirements; that can be simply accomplished by the R-L termination connected between
V

and V

oRX

avoid any losses due to the R-L impedance during the tone transmission, LNBH23 has
dedicated Tone output (V
setting the TTX function to HIGH only during the tone transmission (see DiSEqC 2.0
operation implementation in section 2.2 and 2.3). Also unidirectional DiSEqC 1.x and non­DiSEqC systems need this termination connected through a bypass capacitor and after a R­L filter with 15 Ω in parallel with a 220 µH-270 µH inductor but, there is no need of tone
decoding, thus DETIN and DSQOUT pins can be left connected to GND.

18/32 Doc ID 13356 Rev 7

pins of LNBH23, as shown in the typical application circuit in Figure 4. To

oTX

) that is connected after the filter and must be enabled by

oTX

LNBH23 Electrical characteristics

8 Electrical characteristics

Refer to the typical application circuit, TJ = 0 to 85 °C, EN=1,
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R
50 mA, unless otherwise stated. Typical values are referred to T
voltage. See software description section for I²C access to the system register.

Table 8. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

I

I

Supply voltage IO=750mA, VSEL=LLC=1 8 12 15 V

=0 7 15

I

O

Supply current

EN=0 2

AUX=1; IO=50mA 22

= 11 kΩ, DSQIN = LOW, VI = 12 V, IO =

SEL

=0 20 40

O

= 25 °C. VO = V

J

oRX

pin

mAEN=TEN=TTX=1, I

V

=1 IO=750mA

V

O

Output voltage

SEL

LLC=1 18.8 19.5 20.2

LLC=0 12.8 13.4 14

LLC=0 17.8 18.5 19.2

V

=0 IO=750mA

SEL

LLC=1 13.8 14.4 15

VSEL=0 5 40

V

Line regulation VI=8 to 15V

O

V

O

13/18

TR - T

I

MAX

I

SC

T

OFF

T

ON

F

TONE

Load regulation V

13/18V Rise and Fall transition
time by V

F

CTRL

pin

Output current limiting

Output short circuit current V

Dynamic overload protection
OFF time

Dynamic overload protection ON
time

=0 or 1, IO from 50 to750mA 200 mV

SEL

=LLC=1, V

V

SEL

CTRL

HIGH and vice versa, I
450mA, CO from 10 to 330nF

R

=11kΩ 750 1000

SEL

= 22kΩ 300 600

R

SEL

=0/1, AUX=0/1 1000 mA

SEL

PCL=0, Output shorted 900

PCL=0, Output shorted T

Tone frequency DSQIN=HIGH or TEN=1, TTX=1 20 22 24 kHz

VSEL=1 5 60

from LOW to

from 6 to

O

575 µs

/10

OFF

DSQIN=HIGH or TEN=1, TTX=1

Tone amplitude

Tone duty cycle DSQIN=HIGH or TEN=1, TTX=1 43 50 57 %

, tfTone rise or fall time DSQIN=HIGH or TEN=1, TTX=1 5 8 15 µs

r

EXTM frequency V

DC-DC converter efficiency IO=750mA 93 %

DC-DC

DC-DC converter switching freq. 220 kHz

SW

Tone detector freq. capture range 0.4VPP sine wave

D

Eff

F

A

TONE

TONE

t

F

EXTM

F

DETIN

IO from 0 to750mA

from 0 to 750nF

C

O

=3.3V, V

EXTM-H

EXTM-L

(2)

=0V,

(1)

0.4 0.650 0.9 V

20 22 24 kHz

19 22 25 kHz

V

mV

mA

ms

PP

Doc ID 13356 Rev 7 19/32

Electrical characteristics LNBH23

Table 8. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

DETIN

Z

DETIN

V

V

I

T

SHDN

ΔT

1. External signal frequency range in which the EXTM function is guaranteed.

2. Frequency range in which the DETIN function is guaranteed. The V

Tone detector input amplitude Sine wave signal, 22 kHz 0.3 1.5 V

Tone detector input impedance 150 kΩ

DSQOUT pin logic LOW DETIN Tone present, IOL=2mA 0.3 0.5 V

OL

DSQOUT pin leakage current DETIN Tone absent, VOH=6V 10 µA

I

OZ

DSQIN,TTX,13/18, EXTM pin

V

IL

logic Low

DSQIN,TTX,13/18, EXTM pin

IH

logic High

DSQIN,TTX,13/18, EXTM pin

I

IH

input current

Output backward current EN=0, V

OBK

V

=5V 15 µA

IH

=21V -6 -15 mA

OBK

Thermal shut-down threshold 150 °C

Thermal shut-down hysteresis 15 °C

SHDN

level is intended on the LNB bus (before the C12

capacitor. See Figure 4)

PP

TJ from 0 to 85 °C, VI = 12 V

Table 9. I²C electrical characteristics

PP

0.8 V

2V

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

LOW Level input voltage SDA, SCL 0.8 V

IL

HIGH Level input voltage SDA, SCL 2 V

V

IH

Input current SDA, SCL, VI = 0.4 to 4.5V -10 10 µA

I

I

V

f

Low level output voltage SDA (open drain), IOL = 6mA 0.6 V

OL

Maximum clock frequency SCL 400 kHz

MAX

TJ from 0 to 85 °C, VI = 12 V

Table 10. Address pin characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

V

ADDR-1

V

ADDR-2

V

ADDR-3

1. This I²C address is reserved only for internal usage. Do not use this address with other I²C peripherals to avoid address
conflicts.

"0001010(R/W)" Address pin
voltage range

"0001011(RW)" Address pin
voltage range

"0001000(RW)" Address pin

(1)

voltage range

R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)

R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)

R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)

00.8V

25V

05V

20/32 Doc ID 13356 Rev 7

LNBH23 Electrical characteristics

Refer to the typical application circuit, TJ from 0 to 85 °C, EN=1,
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R
mA, unless otherwise stated. Typical values are referred to T
See software description section for I²C

Table 11. Output voltage diagnostic (VMON bit) characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

access to the system register.

=11 kΩ, DSQIN=LOW, VI = 12 V, IO = 50

SEL

= 25 °C. VO=V

J

pin voltage.

oRX

V

V

TH-L

TH-L

Diagnostic low threshold at

=13.4V

V

O

Diagnostic low threshold at
VO=18.5V

EN=1, VSEL=0
LLC=0

EN=VSEL=1
LLC=0

85 90 95 %

84 90 96 %

Note: If the output voltage is lower than the min. value the VMON I²C bit is set to 1.

When VSEL=0: If VMON=0 then V
V

typical.

oRX

When VSEL=1: If VMON=0 then V
V

typical.

oRX

T

from 0 to 85 °C, EN = 1, VSEL=LLC=TEN=PCL=TTX=0, DSQIN=LOW, VI = 12 V, unless

J

>85% of V

oRX

>84% of V

oRX

typical; If VMON=1 then V

oRX

typical; If VMON=1 then V

oRX

oRX

oRX

<95% of

<96% of

otherwise stated. See software description section for I²C access to the system register.

Table 12. Minimum output current diagnostic (IMON bit) characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

I

TH

Minimum current diagnostic
threshold

ITEST=1, AUX=0/1 5 12 20

mA

ITEST=0, AUX=0/1 2.5 6 10

Note: If the output current is lower than the min. threshold limit the IMON I²C bit is set to 1. if the

output current is higher than the max threshold limit the IMON I²C bit is set to 0.

Refer to the typical application circuit, T
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R
50 mA, unless otherwise stated. Typical values are referred to T
voltage. See software description section for I²C

Table 13. 22 kHz tone diagnostic (TMON bit) characteristics

from 0 to 85 °C, EN = 1,

J

= 11 KΩ, DSQIN=LOW, VI = 12 V, IO =

SEL

access to the system register.

=25°C. V

J

oRX=VoRX

pin

Symbol Parameter Test condition Min. Typ. Max. Unit

A

A

F

F

TH-L

TH-H

TH-L

TH-H

Amplitude diagnostic low
threshold

Amplitude diagnostic high
threshold

Frequency diagnostic low
thresholds

Frequency diagnostic high
thresholds

DETIN pin AC coupled 200 300 400 mV

DETIN pin AC coupled 900 1100 1200 mV

DETIN pin AC coupled 13 16.5 20 kHz

DETIN pin AC coupled 24 29.5 38 kHz

Note: If the 22 kHz tone parameters are lower or higher than the above limits the TMON I²C bit is

set to 1.

Doc ID 13356 Rev 7 21/32

Typical performance characteristics LNBH23

9 Typical performance characteristics

(Refer to the typical application circuit, TJ from 0 to 85 °C, EN = 1,
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R
I

= 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO=V

O

voltage. See software description section for I²C access to the system register).

Figure 8. Output voltage vs. temperature Figure 9. Output voltage vs. temperature

14

14

13.8

13.8

13.6

13.6

13.4

13.4

[V]

[V]

O

O

13.2

13.2

V

V

13

13

12.8

12.8

12.6

12.6

VCC=12V, IO=50mA, VO=13V range

VCC=12V, IO=50mA, VO=13V range

EN=1, VSEL=LLC=0

EN=1, VSEL=LLC=0

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

15

15

14.8

14.8

14.6

14.6

14.4

14.4

[V]

[V]

O

O

14.2

14.2

V

V

14

14

13.8

13.8

13.6

13.6

= 11 kΩ, DSQIN=LOW, VI = 12 V,

SEL

VCC=12V, IO=50mA, VO=14V range

VCC=12V, IO=50mA, VO=14V range

EN=LLC=1, VSEL=0

EN=LLC=1, VSEL=0

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

oRX

pin

Figure 10. Output voltage vs. temperature Figure 11. Output voltage vs. temperature

19.2

19.2

VCC=12V, IO=50mA, VO=18V range

VCC=12V, IO=50mA, VO=18V range

19

19

18.8

18.8

18.6

18.6

[V]

[V]

O

O

18.4

18.4

V

V

18.2

18.2

18

18

EN=VSEL=1, LLC=0

EN=VSEL=1, LLC=0

17.8

17.8

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

Figure 12. Load regulation vs. temperature Figure 13. Supply current vs. temperature

0

0

-20

-20

-40

-40

-60

-60

-80

-80

-100

-100

Load [mV]

Load [mV]

-120

-120

VCC=12V

VCC=12V

-140

-140

=From 50 to 750mA

=From 50 to 750mA

I

I

O

O

-160

-160

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

20.3

20.3

VCC=12V, IO=50mA, VO=19.5V range

VCC=12V, IO=50mA, VO=19.5V range

20.1

20.1

19.9

19.9

19.7

19.7

19.5

19.5

[V]

[V]

19.3

19.3

O

O

V

V

19.1

19.1

18.9

18.9

18.7

18.7

EN=VSEL=LLC=1

EN=VSEL=LLC=1

18.5

18.5

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

16

16

VCC=12V, IO=No Load

VCC=12V, IO=No Load

14

14

12

12

10

10

8

8

[mA]

[mA]

IN

IN

I

I

6

6

4

4

2

2

EN=LLC=VSEL=1, TEN=TTX=0

EN=LLC=VSEL=1, TEN=TTX=0

0

0

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

22/32 Doc ID 13356 Rev 7

LNBH23 Typical performance characteristics

Figure 14. Supply current vs. temperature Figure 15. Dynamic overload protection ON

40

40

VCC=12V

VCC=12V

35

35

=No Load

=No Load

I

I

O

O

30

30

25

25

20

20

[mA]

[mA]

I

I

I

I

15

15

10

10

5

5

EN=TEN=TTX=LLC=VSEL=1

EN=TEN=TTX=LLC=VSEL=1

0

0

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

140

140

130

130

120

120

110

110

100

100

[ms]

[ms]

90

90

ON

ON

T

T

80

80

70

70

60

60

50

50

40

40

-10 0 10 20 30 40 50 6 0 70 80 90

-10 0 10 20 30 40 50 6 0 70 80 90

time vs. temperature

VCC=12V, VO=Shorted to GND

VCC=12V, VO=Shorted to GND

T [°C]

T [°C]

Figure 16. Dynamic overload protection OFF

1200

1200

1100

1100

1000

1000

[ms]

[ms]

900

900

OFF

OFF

T

T

800

800

700

700

600

600

time vs. temperature

VCC=12V

VCC=12V

=Shorted to GND

=Shorted to GND

V

V

O

O

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

Figure 18. Output current limiting vs.

1000

1000

950

950

temperature

VCC=12V, R

VCC=12V, R

=11K

=11K

SEL

SEL

Figure 17. Output current limiting vs. R

1.4

1.4

VCC=12V

VCC=12V

1.2

1.2

1

1

0.8

0.8

[mA]

[mA]

0.6

0.6

MAX

MAX

I

I

0.4

0.4

0.2

0.2

0

0

10 12 14 16 18 20 22 24 26 28 30 32

10 12 14 16 18 20 22 24 26 28 30 32

R

[K ]

R

[K ]

SEL

SEL

Figure 19. Output current limiting vs.

temperature

550

550

500

500

VCC=12V, R

VCC=12V, R

=22K

=22K

SEL

SEL

SEL

900

900

[mA]

[mA]

850

850

MAX

MAX

I

I

800

800

750

750

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

450

450

[mA]

[mA]

400

400

MAX

MAX

I

I

350

350

300

300

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

Doc ID 13356 Rev 7 23/32

Typical performance characteristics LNBH23

Figure 20. Tone frequency vs. temperature Figure 21. Tone amplitude vs. temperature

26

26

VCC=12V, IO=50mA

VCC=12V, IO=50mA

25

25

24

24

23

23

[KHz]

[KHz]

22

22

21

21

TONE

TONE

F

F

20

20

19

19

EN=TEN=TTX=1

EN=TEN=TTX=1

18

18

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

Figure 22. Tone duty cycle vs. temperature Figure 23. Tone rise time vs. temperature

55

55

VCC=12V, IO=50mA

VCC=12V, IO=50mA

54

54
53

53
52

52
51

51

[%]

[%]

50

50

TONE

TONE

49

49

D

D

48

48
47

47

EN=TEN=TTX=1

EN=TEN=TTX=1

46

46
45

45

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

T [°C]

T [°C]

1000

1000

VCC=12V, IO=50mA

VCC=12V, IO=50mA

900

900

800

800

[mV]

[mV]

700

700

TONE

TONE

600

600

A

A

500

500

EN=TEN=TTX=1

EN=TEN=TTX=1

400

400

-100 102030405060708090

-100 102030405060708090

T [°C]

T [°C]

14

14

VCC=12V, IO=50mA

VCC=12V, IO=50mA

13

13
12

12
11

11
10

10

9

9

[µs]

[µs]

r

r

t

t

8

8
7

7
6

6

EN=TEN=TTX=1

EN=TEN=TTX=1

5

5
4

4

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

Figure 24. Tone fall time vs. temperature Figure 25. Output backward current vs.

0

14

14

VCC=12V, IO=50mA

VCC=12V, IO=50mA

13

13
12

12
11

11
10

10

9

9

[µs]

[µs]

f

f

t

t

8

8
7

7
6

6

EN=TEN=TTX=1

EN=TEN=TTX=1

5

5
4

4

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

0

-1

-1

[mA]

[mA]

-2

-2

OBK

OBK

I

I

-3

-3

-4

-4

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

24/32 Doc ID 13356 Rev 7

temperature

VCC=12V, V

VCC=12V, V

EN=0

EN=0

=21V externally forced

=21V externally forced

OBK

OBK

T [°C]

T [°C]

LNBH23 Typical performance characteristics

Figure 26. DC-DC Converter efficiency vs.

100

100

90

90

80

80

70

70

Eff [%]

Eff [%]

60

60

50

50

40

40

temperature

VCC=12V, IO=750mA

VCC=12V, IO=750mA

EN=VSEL=LLC=1

EN=VSEL=LLC=1

-10 0 10 20 30 40 50 60 70 80 90

-10 0 10 20 30 40 50 60 70 80 90

T [°C]

T [°C]

Figure 28. DSQIN tone enable transient

DSQIN

response

Figure 27. 22 kHz tone waveform

LNB

OUT

VCC=12V
EN=TEN=TTX=1

Figure 29. DSQIN tone disable transient

response

V

=12V

CC

EN=TTX=1, TEN=0

DSQIN

LNB

OUT

V
EN=TTX=1, TEN=0

LNB

OUT

=12V

CC

Doc ID 13356 Rev 7 25/32

Package mechanical data LNBH23

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

26/32 Doc ID 13356 Rev 7

LNBH23 Package mechanical data

Table 14. QFN32 (5 x 5 mm.) mechanical data

Dim.

Min. Typ. Max.

A 0.80 0.90 1.00

A1 0 0.02 0.05

A3 0.20

b 0.18 0.25 0.30

D 4.85 5.00 5.15

D2 3.20 3.70

E 4.85 5.00 5.15

E2 3.20 3.70

e0.50

L 0.30 0.40 0.50

ddd 0.08

Figure 30. QFN32 package dimensions

(mm.)

7376875/E

Doc ID 13356 Rev 7 27/32

Package mechanical data LNBH23

PowerSSO-24 mechanical data

Dim.

Min. Typ. Max. Min. Typ. Max.

mm. inch.

A 2.15 2.47 0.085 0.097

A2 2.15 2.40 0.085 0.094

a1 0 0.075 0 0.003

b 0.33 0.51 0.013 0.020

c0.23 0.32 0.009 0.013

(1)

D

(1)

E

10.10 10.50 0.398 0.413

7.4 7.6 0.29 1 0.299

e0.8 0.031

e38.8 0.346

G 0.10 0.004

G1 0.06 0.002

H 10.10 10.50 0.398 0.413

h 0.40 0.016

L 0.55 0.85 0.022 0.033

N 10° (max)

X 4.10 4.70 0.161 0.185

Y4.90 5.50 0.193 0.217

(1) “D and E” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15 mm. (0.006”)

28/32 Doc ID 13356 Rev 7

7412818_A

LNBH23 Package mechanical data

Tape & reel PowerSSO-24 mechanical data

Dim.

mm. inch.

Min. Typ. Max. Min. Typ. Max.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N60 2.362

T 30.4 1.197

Ao 10.8 11.0 0.425 0.433

Bo 10.7 10.9 0.421 0.429

Ko 2.65 2.85 0.104 0.112

Po 3.9 4.1 0.154 0.161

P

1

11.9 12.1 0.469 0.476

W23.7 24.3 0.933 0.957

Doc ID 13356 Rev 7 29/32

Package mechanical data LNBH23

Tape & reel QFNxx/DFNxx (5x5 mm.) mechanical data

mm. inch.

Dim.

Min. Typ. Max. Min. Typ. Max.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N 99 101 3.898 3.976

T 14.4 0.567

Ao 5.25 0.207

Bo 5.25 0.207

Ko 1.1 0.043

Po 4 0.157

P 8 0.315

30/32 Doc ID 13356 Rev 7

LNBH23 Revision history

11 Revision history

Table 15. Document revision history

Date Revision Changes

02-Apr-2007 1 Initial release.

15-Nov-2007 2 Added Note 2 on Ta bl e 3 .

11-Jan-2008 3 Added: new package QFN32 and Ta bl e 5 .

26-Mar-2008 4

08-Jan-2009 5 Modified: ESD parameter Table 3 on page 11.

23-Mar-2009 6 Modified: Y dimension mechanical data for PowerSSO-24 on page 28.

29-Nov-2010 7 Modified: Table 10 on page 20.

Modified: mechanical data for QFN32 Figure 30 on page 27 and Table 14 on

page 27.

Doc ID 13356 Rev 7 31/32

LNBH23

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32/32 Doc ID 13356 Rev 7