ST LNBH23 User Manual

LNBs supply and control IC with step-up and I²C interface

Features

■ Complete interface between LNB and I²C bus

■ Built-in DC-DC converter for single 12 V supply

operation and high efficiency (typ. 93% @ 0.75 A), with integrated NMOS

■ Selectable output current limit by external

resistor

■ Compliant with main satellite receiver systems

specifications

■ New accurate built-in 22 kHz tone generator

suits widely accepted standards (patent pending)

■ Fast oscillator start-up facilitates DiSEqC™

encoding

■ Built-in 22 kHz tone detector supports bi-

directional DiSEqC™ 2.0

■ Very low-drop post regulator and high

efficiency step-up PWM with integrated power NMOS allow low power losses

■ Two output pins suitable to by-pass the output

R-L filter and avoid any tone distortion (R-L filter as per DiSEqC™ 2.0 specs, see typ. application circuits)

■ Overload and over-temperature internal

protections with I²C diagnostic bits

■ Output voltage and output current level

diagnostic feedback by I²C bits

■ LNB short circuit dynamic protection

■ ± 4 kV ESD tolerant on output power pins

LNBH23

PowerSSO-24

(Exposed pad)

Description

Intended for analog and digital satellite receivers/sat-TV, sat-PC cards, the LNBH23 is a monolithic voltage regulator and interface IC, assembled in PowerSSO-24 ePAD and QFN32 (5 x 5 mm.) ePAD, specifically designed to provide the 13/18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.

QFN32 (5 x 5 mm.)

(Exposed pad)

Table 1. Device summary

Order code Package Packaging

LNBH23PPR PowerSSO-24 (Exposed pad) Tape and reel

LNBH23QTR QFN32 (Exposed pad) Tape and reel

November 2010 Doc ID 13356 Rev 7 1/32

www.st.com

Contents LNBH23

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 DiSEqC™ data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 DiSEqC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 DiSEqC™ 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 Data encoding by external tone generator (EXTM) . . . . . . . . . . . . . . . . . . 6

2.5 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.6 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.8 Output voltage diagnostic - VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.9 22 kHz tone diagnostic - TMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10 Minimum output current diagnostic - IMON . . . . . . . . . . . . . . . . . . . . . . . . 7

2.11 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.12 Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 8

2.13 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 LNBH23 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.2 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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LNBH23 Contents

7.3 Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.4 Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17

7.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.7 DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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Block diagram LNBH23

1 Block diagram

Figure 1. Block diagram

P-GND

Vup

VoRX

VoTX

EXTM

DSQIN

CTRL

Rsense

TTX

TTXTTX

SDA SCL

ADDR

PWM

Controller

PWM

Controller

VSEL

TTX

ITEST

VOUT Control

TEN

Linear Post-reg

Linear Post-reg +Modulator

+Modulator +Protections

+Protections +Diagnostics

+Diagnostics

22KHz

22KHz Oscill.

Oscill.

LNBH23

TEN

SDA SCL

I²C interface

I²C Diagnostics

22KHz Tone

22KHz Tone Amp. Diagn.

Amp. Diagn.

22KHz Tone

22KHz Tone Freq. Detector

Freq. Detector

BypVcc Vcc-LISEL TTX

BypVcc Vcc-LBypVcc Vcc-LISEL TTX

Preregulator

Preregulator +U.V.lockout

+U.V.lockout +P.ON reset

+P.ON reset

DETIN

DSQOUT

A-GND

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LNBH23 Application information

2 Application information

This IC has a built-in DC-DC step-up converter with integrated NMOS that, from a single source from 8 V to 15 V, generates the voltages (V work at a minimum dissipated power of 0.375 W Typ. @ 500 mA load (the linear postregulator drop voltage is internally kept at V

UP-VORX

circuit will disable the whole circuit when the supplied V V typically).

) that let the linear post-regulator to

=0.75 V typ.). An under voltage lockout

drops below a fixed threshold (6.7

Note: In this document the output voltage (V

post-regulator output (V

ORX

pin).

) is intended as the voltage present at the linear

2.1 DiSEqC™ data encoding and decoding

The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance to the standards, and can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin (DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the 22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) The TTX function must be disabled setting TTX to LOW.

2.2 DiSEqC™ 2.0 implementation

The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC™ 2.0 interfacing (see Note 1). It’s input pin (DETIN) must be AC coupled to the DiSEqC™ BUS, and extracted PWK data are available on the DSQOUT pin. To comply to the bi-directional DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH23 is provided with two output pins, one for the dc voltage output (V tone transmission (V while the V

provides the 13/18 V output voltage. This allows the 22 kHz Tone to pass

oRX

without any losses due to the R-L filter impedance (see Figure 4 typ. application circuit). During the 22 kHz transmission, in DiSEqC™ 2.0 applications, activated by DSQIN pin or by the TEN bit, the V controlled both through the TTX pin and by I²C bit. As soon as the tone transmission is expired, the V

oTX

kHz receiving mode. The 13/18 V power supply is always provided to the LNB from the V pin through the R-L filter.

). The V

oTX

pin must be preventively set ON by the TTX function. This can be

oTX

must be activated only during the tone transmission

oTX

must be disabled by setting the TTX to LOW to set the device in the 22

) and one for the 22 kHz

oRX

2.3 DiSEqC™ 1.X implementation

When the LNBH23 is used in DiSEqC™ 1.x applications the R-L filter is always needed for the proper operation of the new 22 kHz tone generator (patent pending. See application circuit). Also in this case, the TTX function must be preventively enabled before to start the 22 kHz data transmission and disabled as soon as the data transmission has been expired. The tone can be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal circuit activates the 22 kHz tone on the V TTL signal presence on the DSQIN pin, and it stops with 1 cycles ±25 µs delay after the TTL signal is expired.

Doc ID 13356 Rev 7 5/32

oTX

output with 0.5 cycles ±25 µs delay from the

Application information LNBH23

2.4 Data encoding by external tone generator (EXTM)

In order to improve design flexibility an external tone input pin is available (EXTM). The EXTM is a logic input pin which activates the 22 kHz tone output, on the V the LNBH23 integrated tone generator (similarly to the DSQIN pin function). As a matter of fact, the output tone waveform characteristics will be always internally controlled by the LNBH23 tone generator and the EXTM signal will be used just as a timing control of the DiSEqC tone data encoding on the V for the proper control of the EXTM pin function. Before to send the TTL signal on the EXTM pin, the V

tone generator must be previously enabled through the TTX function (TTX pin

oTX

or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal code, it activates the 22 kHz tone on the V TTL signal presence on the EXTM pin, and it stops with 2 cycles ±25 µs delay after the TTL signal is expired. Refer to the below Figure 2

Figure 2. EXTM waveform

output. A TTL compatible 22 kHz signal is required

oTX

output with 1.5 cycles ±25 µs delay from the

oTX

pin, by using

oTX

2.5 I²C interface

The main functions of the IC are controlled via I²C bus by writing 8 bits on the system register (SR 8 bits in write mode). On the same register there are 8 bits that can be read back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF) while, three will report the last output voltage register status (EN, VSEL, LLC) received by the IC (see below diagnostic functions section).

2.6 Output voltage selection

When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by means of the V LNBs. Additionally, the LNBH23 is provided with the LLC I²C bit that increases the selected voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable. The LNBH23 is also compliant to the USA LNB power supply standards. In order to allow fast transition of the output voltage from 18 V to 13 V and vice versa, the LNBH23 is provided with the VCTRL TTL pin which keeps the output to 13 V when it is set LOW and to 18 V when it is set HIGH or floating. V to use the VCTRL pin to switch the output voltage level. If VCTRL=1 or floating V (or 19.5 V if LLC=1). With VCTRL=0 V VCTRL pin controls only the linear regulator V controlled only through the VSEL and LLC I²C bits, that is: Even if VCTRL=0 (keeping

bit (Voltage SELect) for remote controlling of non-DiSEqC

SEL

and, if required, LLC bits must be set HIGH before

SEL

=13.4 V (LLC= either 0 or 1). Be aware that the

oRX

stage while the step-up VUP voltage is

oRX

=18.5 V

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LNBH23 Application information

=13.4 V) you will have VUP=19.25 V typ when V

oRX

=1 and 20.25 V with V

SEL

=LLC=1.

SEL

This means that VCTRL=0 must be used only for short time to avoid the higher power dissipation. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during the stand-by condition).

2.7 Diagnostic and protection functions

The LNBH23 has 5 diagnostic internal functions provided via I²C bus by reading 5 bits on the system register (SR bits in read mode). All the diagnostic bits are, in normal operation (no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature and over-load protections status (OTF and OLF) while, the remaining 3 bits, are dedicated to the output voltage level (VMON), 22 kHz tone (TMON) and to the minimum load current diagnostic function (IMON).

2.8 Output voltage diagnostic - VMON

When V

=0 or 1 and LLC=0, the output voltage pin (V

SEL

) is internally monitored and, as

oRX

long as the output voltage level is below the guaranteed limits the VMON I²C bit is set to "1". The output voltage diagnostic is valid only with LLC=0. Any VMON information with LLC=1 must be disregarded by the MCU.

2.9 22 kHz tone diagnostic - TMON

The 22 kHz tone can be internally detected and monitored if DETIN pin is connected to the LNB output bus (see typical application circuits Figure 4) through a decoupling capacitor. The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude and/or the tone frequency is out of the guaranteed limits (see TMON limits in the electrical characteristics Ta bl e 1 3), the TMON I²C bit is set to "1".

2.10 Minimum output current diagnostic - IMON

In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) the LNBH23 is provided with a minimum output current flag by the IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA typically with ITEST=1 and 6 mA with ITEST=0. The minimum current diagnostic function (IMON) is always active. In order to make it work even in a multi-IRD configuration (multiswitch), where the supply current could be sunk only from the higher supply voltage connected to the multi-switch box, the LNBH23 is provided with the AUX I²C bit which can be set HIGH, in write mode by the MCU, before to read the IMON I²C bit status, to force the LNBH23 output voltage as the highest voltage on the bus (22 V typ.) during the minimum current diagnostic phase. When the AUX bit is set to HIGH, the V V

is set to 22.75 V (V

the AUX function is used to force the V LOW as soon as the minimum current test phase is expired, so that the V controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the IMON function must be used only with the 22 kHz tone transmission deactivated (TEN=TTX=0 and DSQIN=LOW), otherwise the IMON bit could be erroneously set to 0 even if the output current is below the minimum current thresholds (6 mA or 12 mA). Any TMON information with 22 kHz tone enabled must be disregarded by the MCU.

= V

+0.75 V typ.) independently of the VSEL/LLC bits status. If

oRX

to 22 V, it is recommended to set the AUX bit to

oRX

is set to 22 V (typ.) and

oRX

voltage will be

oRX

Doc ID 13356 Rev 7 7/32

Application information LNBH23

2.11 Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to I

pin. The resistor value defines the output current limit by the equation:

SEL

[A] = 10000/R

MAX

where R

SEL

limit threshold is 1.0 A typ with R

SEL

is the resistor connected between I

=10 kΩ. The above equation defines the typical

SEL

and GND. The highest selectable current

SEL

threshold value.

2.12 Over-current and short circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short circuit condition, the device is provided with a dynamic short circuit protection. It is possible to set the short circuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C SR. When the PCL (pulsed current limiting) bit is set lo LOW, the over current protection circuit works dynamically: as soon as an overload is detected, the output current is provided for 90 ms (typ.), after that the output is set in shut-down for a time T typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the system register is set to "1". After this time has elapsed, the output is resumed for a time T (typ.). At the end of T through T

and TON. At the end of a full TON in which no overload is detected, normal

OFF

, if the overload is still detected, the protection circuit will cycle again

=1/10 T

operation is resumed and the OLF diagnostic bit is reset to LOW. Typical T 990 ms and an internal timer determines it. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to "1" when the current clamp limit is reached and returns LOW when the overload condition is cleared.

OFF of

= 90 ms

OFF

ON +TOFF

time is

2.13 Thermal protection and diagnostic

The LNBH23 is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135 °C (typ.).

Note: 1 External components are needed to comply to bidirectional DiSEqC™ bus hardware

requirements. Full compliance of the whole application with DiSEqC™ specifications is not implied by the use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT. I²C is trademark of Philips Semiconductors.

8/32 Doc ID 13356 Rev 7

LNBH23 Pin configuration

3 Pin configuration

Figure 3. Pin connections (top view for PowerSSO-24, bottom view for QFN32)

DETIN

VCTRL

P-GND

SDA

SCL

ADDR

DSQOUT

DSQIN

ISEL

VUP

VoTX

VoRX

A-GND

VCC

VCC-L

BYP

TTX

EXTM

PowerSSO-24

QFN32 (5 x 5 mm.)

Table 2. Pin description

Pin n° for

QFN32

19 17 V

18 16 V

27 22 V

21 19 V

22 20 V

12 12 DSQIN DiSEqC input

14 14 TTX TTX enable

29 1 DETIN

Pin n° for PSSO-24

Symbol Name Function

CC–L

Supply input 8 to 15 V IC DC-DC power supply.

Supply input 8 to 15 V analog power supply.

4 6 LX N-MOS drain Integrated N-Channel power MOSFET drain.

Input of the linear post-regulator. The voltage on this pin is

Step-Up voltage

monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor.

oRX

Output port for 22

oTX

LDO output port

kHz tone TX

Output of the integrated low drop linear post-regulator. See truth tables for voltage selections and description.

TX Output to the LNB. See truth tables for selection.

6 8 SDA Serial data Bi-directional data from/to I²C bus.

9 9 SCL Serial clock Clock from I²C bus.

This pin will accept the DiSEqC code from the main microcontroller. The LNBH23 will use this code to modulate the internally generated 22 kHz carrier. Set to ground if not used.

This pin can be used, as well as the TTX I²C bit of the system register, to control the TTX function enable before to start the 22 kHz tone transmission. Set floating or to GND if not used.

Tone decoder

input

22 kHz tone decoder Input, must be AC coupled to the DiSEqC 2.0 bus.

Doc ID 13356 Rev 7 9/32

Pin configuration LNBH23

Table 2. Pin description (continued)

Pin n° for

QFN32

Pin n° for PSSO-24

Symbol Name Function

Open drain output of the tone decoder to the main

11 11 DSQOUT DiSEqC output

microcontroller for DiSEqC 2.0 data decoding. It is LOW when tone is detected on DETIN pin.

13 13 EXTM

External

modulation

External modulation logic input pin which activates the 22 kHz tone output on the V

Needed for internal pre-regulator filtering. The BYP pin is

15 15 BYP

By-pass

capacitor

intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.

10 10 ADDR Address setting

Two I²C bus addresses available by setting the Address pin level voltage. See address pin characteristics Ta bl e 1 0

The resistor “RSEL” connected between ISEL and GND

28 23 ISEL Current selection

defines the linear regulator current limit threshold by the equation: Imax(typ.)=10000/ RSEL.

13V-18V linear regulator V

30 2 VCTRL

Output voltage

control

only with V

19.5V if LLC=1). If VCTRL=0 than V or 1). Leave floating if not used. Do not connect to ground if

=1. If VCTRL=1 or floating V

SEL

not used.

5 7 P-GND Power ground DC-DC converter power ground.

pin. Set to ground if not used.

oTX

switch control. To be used

oRX

=18.5V (or

oRX

=13.4V (LLC=either 0

Epad Epad Epad Exposed pad

To be connected with power grounds and to the ground layer through vias to dissipate the heat.

20 18 A-GND Analog ground Analog circuits ground.

1, 2, 3, 7, 8, 16, 17,

23, 24, 25, 26,

3, 4, 5,

21, 24

N.C. Not connected Not internally connected pins.

31, 32

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