ST LM833 User Manual

Features

■ Low voltage noise: 4.5 nV/√Hz

■ High gain bandwidth product: 15 MHz

■ High slew rate: 7 V/µs

■ Low distortion: 0.002%

■ Excellent frequency stability

■ ESD protection 2 kV

Applications

LM833

Low noise dual operational amplifier

N

DIP8

(Plastic package)

■ Audio systems

■ Preamplification, filtering

Description

The LM833 is a monolithic dual operational
amplifier particularly well-suited to audio
applications.

It offers low voltage noise (4.5 nV/√Hz) and high
frequency performances (15 MHz gain bandwidth
product, 7 V/µs slew rate).

In addition, the LM833 has a very low distortion
(0.002%) and excellent phase/gain margins.

Inverting input 1

Non-inverting input 1

D

SO-8

(Plastic micropackage)

Pin connections (top view)

-

+

V

8

CC

Output 2

7

6

Inverting input 2

Non-inverting input 2

1

Output 1

2

-

+

3

45

-

V

CC

+

August 2009 Doc ID 2169 Rev 3 1/12

www.st.com

12

Absolute maximum ratings LM833

1 Absolute maximum ratings

Table 1. Key parameters and their absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

id

V

Supply voltage ±18 or +36 V

Differential input voltage

Input voltage

i

Input current

(1)

(1)

(2)

: Vin driven negative

5 mA in DC or 50 mA in

±30 V

±15 V

AC (duty cycle = 10%,

I

in

Input current

(3)

: Vin driven positive above

AMR value

T=1s)

0.4

mA

Output short-circuit duration Infinite s

T

T

stg

Ptot

ESD

1. Either or both input voltages must not exceed the magnitude of Vcc+ or Vcc-.

2. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the
collector-base junction of the input PNP transistor becoming forward-biased and thereby acting as input
diode clamp. In addition to this diode action, there is NPN parasitic action on the IC chip. This transistor
action can cause the output voltages of the Op-amps to go to the V
overdrive) for the time during which an input is driven negative.
This is not destructive and normal output is restored for input voltages above -0.3 V.

3. The junction base/substrate of the input PNP transistor polarized in reverse must be protected by a resistor
in series with the inputs to limit the input current to 400 µA max (R = (Vin - 36 V)/400 µA).

4. Power dissipation must be considered to ensure maximum junction temperature (Tj) is not exceeded.

5. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.

6. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.

7. Charged device model: all pins plus package are charged together to the specified voltage and then
discharged directly to the ground.

Junction temperature +150 °C

j

Storage temperature -65 to +150 °C

Maximum power dissipation

HBM: human body model

MM: machine model

(5)

(6)

CDM: charged device model

(4)

(7)

CC

500 mW

2kV

200 V

1.5 kV

voltage level (or to ground for a large

Table 2. Operating conditions

Symbol Parameter Value Unit

T

V

CC

oper

Supply voltage ±2.5 to ±15 V

Operating free-air temperature range -40 to 105 °C

2/12 Doc ID 2169 Rev 3

LM833 Typical application schematics

2 Typical application schematics

Figure 1. Schematic diagram (1/2 LM833)

V

CC

Inverting

Input

Non-inverting

Input

V

CC

Output

Doc ID 2169 Rev 3 3/12

Electrical characteristics LM833

3 Electrical characteristics

Table 3. V

Symbol Parameter Min. Typ. Max. Unit

= +15 V, V

CC+

= -15 V, T

CC-

= 25° C (unless otherwise specified)

amb

V

DV

V

A

Input offset voltage (Rs = 10 Ω, Vo = 0 V, Vic = 0 V)

io

Input offset voltage drift

I

io

I

ib

icm

io

vd

= 10 Ω, Vo = 0 V, T

R

s

min.

≤ T

amb

≤ T

max.

Input offset current (Vo = 0 V, Vic = 0 V)

Input bias current (Vo = 0 V, Vic = 0 V)

Input common mode voltage range ±12 ±14 V

Large signal voltage gain (RL = 2 kΩ, Vo = ±10 V)

0.3 5 mV

2

25 200 nA

300 1000 nA

90 100 dB

Output voltage swing (Vid = ±1 V)

±V

CMR

SVR

I

CC

SR

GBP

= 2.0 kΩ

R

opp

L

RL = 2.0 kΩ

= 10 kΩ

R

L

RL = 10 kΩ

Common-mode rejection ratio (V

Supply voltage rejection ratio
(V

CC+/VCC-

= +15 V/-15 V to +5 V/-5 V)

Supply current (Vo = 0 V, all amplifiers)

Slew rate (V

= -10 V to +10 V, RL = 2 kΩ, AV = +1)

i

Gain bandwidth product
(R

= 2 kΩ, CL = 100 pF, f = 100 kHz)

L

= ±13 V)

ic

101213.7

-14

-10

13.9

-14.4

-12

80 100 dB

80 105 dB

48 mA

57 V/µs

10 15 MHz

B Unity gain bandwidth (open loop) 9 MHz

µV/°C

V

φm

e

i

THD

V

O1/VO2

FPB

Phase margin (R

Equivalent input noise voltage (RS = 100 Ω, f = 1 kHz)

n

Equivalent input noise current (f = 1 kHz) 0.5

n

Total harmonic distortion

= 2 kΩ, f = 20 Hz to 20 kHz, Vo = 3 V

(R

L

Channel separation (f = 20 Hz to 20 kHz) 120 dB

Full power bandwidth (Vo = 27 Vpp, RL = 2 kΩ, THD ≤ 1%)

= 2 kΩ)

L

4/12 Doc ID 2169 Rev 3

, AV = +1)

rms

60 Degrees

nV

4.5

------------

pA

------------

0.002 %

120 kHz

Hz

Hz