ST LIS3DSH User Manual

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LIS3DSH

MEMS digital output motion sensor

ultra low-power high performance three-axis “nano” accelerometer

Preliminary data

Features

■ Wide supply voltage, 1.71 V to 3.6 V

■ Independent IOs supply (1.8 V) and supply

voltage compatible

■ Ultra low-power consumption

■ ±2g/±4g/±6g/±8g/±16g dynamically selectable

full-scale

■ I

C/SPI digital output interface

■ 16-bit data output

■ Programmable embedded state machines

■ Embedded temperature sensor

■ Embedded self-test

■ Embedded FIFO

■ 10000 g high shock survivability

■ ECOPACK

RoHS and “Green” compliant

of measuring accelerations with output data rates from 3.125 Hz to 1.6 kHz.

The self-test capability allows the user to check the functioning of the sensor in the final application.

The device can be configured to generate interrupt signals activated by user defined motion patterns.

The LIS3DSH has an integrated first in, first out (FIFO) buffer allowing the user to store data for host processor intervention reduction.

LGA-16

(3x3x1 mm)

Applications

■ Motion controlled user interface

■ Gaming and virtual reality

■ Pedometer

■ Intelligent power saving for handheld devices

■ Display orientation

■ Click/double click recognition

■ Impact recognition and logging

■ Vibration monitoring and compensation

Description

The LIS3DSH is an ultra low-power high performance three-axis linear accelerometer belonging to the “nano” family with embedded state machine that can be programmed to implement autonomous applications.

The LIS3DSH has dynamically selectable full scales of ±2g/±4g/±6g/±8g/±16g and it is capable

The LIS3DSH is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

Table 1. Device summary

Order

codes

LIS3DSH -40 to +85 LGA-16 Tray

LIS3DSHTR -40 to +85 LGA-16

Temperature

range [° C]

Package Packaging

Tape and

reel

October 2011 Doc ID 022405 Rev 1 1/53

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

Contents LIS3DSH

1 Contents

1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6.1 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.8 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.9 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.4 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.5 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1 INFO1 (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.2 INFO2 (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.3 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.4 CTRL_REG3 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.5 CTRL_REG4 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.6 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.7 CTRL_REG6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.8 STATUS (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.9 OUT_T (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.10 OFF_X (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.11 OFF_Y (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.12 OFF_Z (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.13 CS_X (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.14 CS_Y (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.15 CS_Z (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.16 LC (16h - 17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.17 STAT (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.18 VFC_1 (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.19 VFC_2 (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.20 VFC_3 (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.21 VFC_4 (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.22 THRS3 (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.23 OUT_X (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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Contents LIS3DSH

8.24 OUT_Y (2Ah - 2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.25 OUT_Z (2Ch - 2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.26 FIFO_CTRL (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.27 FIFO_SRC (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.28 CTRL_REG1 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.29 STx_1 (40h-4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.30 TIM4_1 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.31 TIM3_1 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.32 TIM2_1 (52h - 53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.33 TIM1_1 (54h - 55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.34 THRS2_1 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.35 THRS1_1 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.36 MASK1_B (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.37 MASK1_A (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.38 SETT1 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.39 PR1 (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.40 TC1 (5Dh-5E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.41 OUTS1 (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.42 PEAK1 (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.43 CTRL_REG2 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.44 STx_1 (60h-6Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.45 TIM4_2 (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.46 TIM3_2 (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.47 TIM2_2 (72h - 73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.48 TIM1_2 (74h - 75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.49 THRS2_2 (76h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.50 THRS1_2 (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.51 MASK2_B (79h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.52 MASK2_A (7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.53 SETT2 (7Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.54 PR2 (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.55 TC2 (7Dh-7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.56 OUTS2 (7Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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8.57 PEAK2 (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.58 DES2 (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Doc ID 022405 Rev 1 5/53

List of tables LIS3DSH

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 8. LIS3DSH state machines: sequence of state to execute an algorithm . . . . . . . . . . . . . . . . 15

Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 13. Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 14. Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 19

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19

Table 16. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. INFO1 register default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18. INFO2 register default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. WHO_AM_I register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20. Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21. CTRL_REG3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 22. Control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 23. CTRL_REG4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 24. CTRL4 ODR configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 25. Control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 26. Control register 5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 27. Self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 28. Control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 29. Control register 6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 30. Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 31. Status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 32. OUT_T register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 33. OUT_T register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 34. Offset X default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 35. Offset Y default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 36. Offset Z default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 37. Constant shift X-axis default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 38. Constant shift Y-axis default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 39. Constant shift Y-axis default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 40. LC_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 41. LC_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 42. STAT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 43. STAT register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 44. Vector filter coefficient register 1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 45. Vector filter coefficient register 2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 46. Vector filter coefficient register 3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 47. Vector filter coefficient register 4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 48. Threshold value register 3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6/53 Doc ID 022405 Rev 1

LIS3DSH List of tables

Table 49. OUT_X_L register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 50. OUT_X_H register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 51. OUT_Y_L register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 52. OUT_Y_H register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 53. OUT_Z_L register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 54. OUT_Z_H register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 55. FIFO control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 56. FIFO mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 57. FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 58. FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 59. SM1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 60. SM1 control register structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 61. Timer4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 62. Timer3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 63. TIM2_1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 64. TIM2_1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 65. TIM1_1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 66. TIM1_1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 67. THRS2_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 68. THRS1_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 69. MASK1_B axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 70. MASK1_B register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 71. MASK1_A axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 72. MASK1_A register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 73. SETT1 register structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 74. SETT1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 75. PR1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 76. PR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 77. TC1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 78. TC1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 79. OUTS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 80. OUTS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 81. PEAK1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 82. SM2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 83. SM2 control register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 84. Timer4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 85. Timer3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 86. TIM2_2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 87. TIM2_2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 88. TIM1_2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 89. TIM1_2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 90. THRS2_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 91. THRS1_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 92. MASK2_B axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 93. MASK2_B register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 94. MASK2_A axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 95. MASK2_B register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 96. SETT2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 97. SETT2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 98. PR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 99. PR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 100. TC2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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List of tables LIS3DSH

Table 101. TC2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 102. OUTS2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 103. OUTS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 104. PEAK2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 105. DES2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 106. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8/53 Doc ID 022405 Rev 1

LIS3DSH List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. LIS3DSH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. Multiple bytes SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. Multiple bytes SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Doc ID 022405 Rev 1 9/53

Block diagram and pin description LIS3DSH

2 Block diagram and pin description

2.1 Block diagram

Figure 1. Block diagram

2.2 Pin description

Figure 2. Pin connection

X+

Y+

Z+

MUX

Z-

Y-

X-

CHARGE AMPLIFIER

A/D

CONVERTER

REFERENCESELF TEST

TRIMMING

CIRCUITS

STATE MACHINES

AND CONTROL

LOGIC

FIFO /

TEMP. SENSOR

CLOCK

SCL/SPC

I2C

SDA/SDO/SDI

SPI

SDO/SEL

INT 1/DRDY

INT 2

AM10209V1

GND

Pin 1 indicator

Vdd_IO

SCL/SPC

GND

INT1/DRDY

RES

INT2

Vdd

RES

(TOP VIEW)

DIRECTION OF THE DETECTABLE ACCELERATIONS

10/53 Doc ID 022405 Rev 1

SEL/SDO

SDA/SDI/SDO

(BOTTOM VIEW)

am10210V1

LIS3DSH Block diagram and pin description

Table 2. Pin description

Pin# Name Function

1 Vdd_IO Power supply for I/O pins

2 NC Not connected

3 NC Not connected

SCL

SPC

5 GND 0 V supply

SDA

SDI

SDO

SEL

SDO

8CS

9 INT 2 Interrupt 2

10 Reserved Connect to GND

I2C serial clock (SCL) SPI serial port clock (SPC)

C serial data (SDA)

I SPI serial data input (SDI) 3-wire interface serial data output (SDO)

C address selection

I SPI serial data output (SDO)

SPI enable I2C/SPI mode selection (1: SPI idle mode / I2C communication

enabled; 0: SPI communication mode / I

C disabled)

11 INT 1/DRDY Interrupt 1/ DRDY

12 GND 0 V supply

13 GND 0 V supply

14 Vdd Power supply

15 Reserved Connect to Vdd

16 GND 0 V supply

Doc ID 022405 Rev 1 11/53

Mechanical and electrical specifications LIS3DSH

3 Mechanical and electrical specifications

3.1 Mechanical characteristics

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

Table 3. Mechanical characteristics

Symbol Parameter Test conditions Min. Typ.

FS bit set to 000 ±2.0 g

FS bit set to 001 ±4.0 g

(3)

(2)

FS bit set to 010 ±6.0 g

FS bit set to 011 ±8.0 g

FS bit set to 100 ±16.0 g

FS bit set to 000 0.06 mg/digit

FS bit set to 001 0.12 mg/digit

FS bit set to 010 0.18 mg/digit

FS bit set to 011 0.24 mg/digit

FS bit set to 100 0.73 mg/digit

FS bit set to 00 0.01 %/°C

FS bit set to 00 ±40 mg

Max. delta from 25 °C ±0.5 mg/°C

FS bit set to 00, normal mode, ODR = 100 Hz

± 2g range, X,Y-axis ST2,ST1 = [01] see Figure 24

± 2g range, Z-axis ST2,ST1 = [01] see Figure 24

(CNTL5 ST2, ST1 bits=01)

FS Measurement range

So Sensitivity

TCSo

Ty Of f

TCOff

To p

1. Typical specifications are not guaranteed.

2. Verified by wafer level test and measurement of initial offset and sensitivity.

3. Typical zero-g level offset value after MSL3 preconditioning.

4. Self-test output change” is defined as: OUTPUT[mg]

Sensitivity change vs. temperature

Typical zerooffset accuracy

g level change

Zerovs. temperature

Acceleration noise

density

Self test positive

difference

Operating temperature range

g level

(4)

(a)

-40 +85 °C

- OUTPUT[mg]

(1)

Max. Unit

150

140

590

(CNTL5 ST2, ST1 bits=00)

ug/

sqrt(Hz)

a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

12/53 Doc ID 022405 Rev 1

LIS3DSH Mechanical and electrical specifications

3.2 Electrical characteristics

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

(b)

(3)

(1)

(2)

1.71 Vdd+0.1 V

1.6 kHz ODR 225 µA

3.125 Hz ODR 11 µA

2µA

Max. Unit

Table 4. Electrical characteristics

Symbol Parameter Test conditions Min. Typ.

Vdd Supply voltage 1.71 2.5 3.6 V

Vdd_IO I/O pins supply voltage

IddA

IddPdn

VIH Digital high level input voltage 0.8*Vdd_IO V

VIL Digital low level input voltage 0.2*Vdd_IO V

VOH High level output voltage 0.9*Vdd_IO V

VOL Low level output voltage 0.1*Vdd_IO V

Top Operating temperature range -40 +85

1. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

2. Typical specifications are not guaranteed.

3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication buses, in this condition the measurement chain is powered off.

Current consumption in Active mode

Current consumption in powerdown/standby mode

°C

b. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

Doc ID 022405 Rev 1 13/53

Mechanical and electrical specifications LIS3DSH

3.3 Communication interface characteristics

3.3.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 5. SPI slave timing values

(1)

Val u e

Symbol Parameter

Min. Max.

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz

tsu(CS) CS setup time 6

th(CS) CS hold time 8

tsu(SI) SDI input setup time 5

th(SI) SDI input hold time 15

tv(SO) SDO valid output time 50

th(SO) SDO output hold time 9

tdis(SO) SDO output disable time 50

Unit

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

(c)

c(SP C)

h(CS)

LSB IN

h(SO )

LSB OUT

dis(SO )

Figure 3. SPI slave timing diagram

(2)

su (CS)

SPC

(2)

su (SI)

(2)

SD I

(2)

SD O

2. When no communication is on-going, data on SDO is driven by internal pull-up resistor.

h(SI)

MSB IN

v(SO )

MSB OUT

(2)

c. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

14/53 Doc ID 022405 Rev 1

LIS3DSH Mechanical and electrical specifications

3.3.2 I2C - inter IC control interface

Subject to general operating conditions for Vdd and Top.

Table 6. I2C slave timing values

Symbol Parameter

I2C standard mode

(1)

I2C fast mode

(1)

Unit

Min. Max. Min. Max.

(SCL)

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA) tr(SCL)

f(SDA) tf(SCL)

h(ST)

su(SR)

su(SP)

w(SP:SR)

SCL clock frequency 0 100 0 400 kHz

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100 ns

SDA data hold time 0.01 3.45 0.01 0.9 µs

SDA and SCL rise time 1000

SDA and SCL fall time 300

START condition hold time 4 0.6

Repeated START condition setup time

4.7 0.6

STOP condition setup time 4 0.6

Bus free time between STOP and START condition

4.7 1.3

1. Data based on standard I2C protocol requirement, not tested in production.

2. Cb = total capacitance of one bus line, in pF.

Figure 4. I2C slave timing diagram

(d)

20 + 0.1C

µs

(2)

300

µs

START

SDA

f(SDA)

r(SDA)

su(SDA)

h(SDA)

SCL

w(SCLL)

w(SCLH)

r(SCL)

f(SCL)

h(ST)

d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

Doc ID 022405 Rev 1 15/53

su(SR)

su(SP)

w(SP:SR)

REPEATED

START

STOP

Mechanical and electrical specifications LIS3DSH

3.4 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 7. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 4.8 V

Vdd_IO I/O pins supply voltage -0.3 to 4.8 V

Vin

POW

UNP

STG

ESD Electrostatic discharge protection 2 (HBM) kV

Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO, SDO/SEL)

Acceleration (any axis, powered, Vdd = 2.5 V)

Acceleration (any axis, unpowered)

Operating temperature range -40 to +85 °C

Storage temperature range -40 to +125 °C

-0.3 to Vdd_IO +0.3 V

3000 for 0.5 ms g

10000 for 0.1 ms g

3000 for 0.5 ms g

10000 for 0.1 ms g

Note: Supply voltage on any pin should never exceed 4.8 V

This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part.

This is an ESD sensitive device, improper handling can cause permanent damage to the part.

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LIS3DSH Mechanical and electrical specifications

3.5 Terminology

3.5.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.

3.5.2 Zero-g level

Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady-state on a horizontal surface measures 0 g in X axis and 0 g in Y axis, whereas the Z axis measures 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level tolerance (TyOff) describes the standard deviation of the range of Zero-g levels of a population of sensors.

3.6 Functionality

3.6.1 Self-test

Self-test allows to check the sensor functionality without moving it. The self-test function is off when the self-test bit (ST) is programmed to ‘0‘. When the self-test bit is programmed to ‘1’, an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs exhibit a change in their DC levels which are related to the selected full-scale through the device sensitivity. When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.

3.7 Sensing element

A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation.

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Mechanical and electrical specifications LIS3DSH

When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.

At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.

3.8 IC interface

The complete measurement chain is made up of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user through an analog-to-digital converter.

The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller.

The LIS3DSH features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device.

C/SPI interface, therefore making the

3.9 Factory calibration

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).

The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows to use the device without further calibration.

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LIS3DSH Application hints

4 Application hints

Figure 5. LIS3DSH electrical connection

Vdd

TOP VIEW

SDA/SDI/SDO

1416

SEL/SDO

INT1/DRDY

INT 2

AM10211V1

10µF

100nF

GND

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

Vdd_IO

SCL/SPC

The device core is supplied through the Vdd line while the I/O pins are supplied through the Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF) should be placed as near as possible to pin 14 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.

The functionality of the device and the measured acceleration data is selectable and accessible through the I

C or SPI interfaces. When using the I2C, CS must be tied high.

4.1 Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com

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Digital main blocks LIS3DSH

5 Digital main blocks

5.1 State machine

The LIS3DSH embeds two state machines able to run a user defined program.

The program is made up of a set of instructions that define the transition to successive states. Conditional branches are possible.

From each state (n) it is possible to have transition to the next state (n+1) or to reset state. Transition to reset point happens when “RESET condition” is true; Transition to the next step happens when “NEXT condition” is true.

Interrupt is triggered when output/stop/continue state is reached.

Each state machine allows to implement gesture recognition in a flexible way, free-fall, wake-up, 4D/6D orientation, pulse counter and step recognition, click/double click, shake/double shake, face-up/face-down, turn/double turn:

● Code and parameters are loaded by the host into dedicated memory areas for the state

program

● State program with timing based on ODR or decimated time

● Possibility of conditional branches

Table 8. LIS3DSH state machines: sequence of state to execute an algorithm

START

State 1

reset

State 2

reset

State 3

reset

State n

OUTPUT/STOP/CONTINUE

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INT set

AM10212V1

LIS3DSH Digital main blocks

5.2 FIFO

LIS3DSH embeds an acceleration data FIFO for each of the three output channels, X, Y, and Z. This allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work according to four different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits. Programmable Watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on the INT1/2 pin.

5.2.1 Bypass mode

In Bypass mode, the FIFO is not operational and for this reason it remains empty. For each channel only the first address is used. The remaining FIFO slots are empty.

5.2.2 FIFO mode

In FIFO mode, data from X, Y, and Z channels are stored in the FIFO. A Watermark interrupt can be enabled in order to be raised when the FIFO is filled to the level specified by the internal register. The FIFO continues filling until it is full. When full, the FIFO stops collecting data from the input channels.

5.2.3 Stream mode

In Stream mode, data from the X, Y, and Z measurement are stored in the FIFO. A Watermark interrupt can be enabled and set as in the FIFO mode. The FIFO continues filling until it’s full. When full, the FIFO discards the older data as the new arrive.

5.2.4 Stream-to-FIFO mode

In Stream-to_FIFO mode, data from the X, Y, and Z measurement are stored in the FIFO. A Watermark interrupt can be enabled in order to be raised when the FIFO is filled to the level specified by the internal register. The FIFO continues filling until it’s full. When full, the FIFO discards the older data as the new arrive. Once trigger event occurs, the FIFO starts operating in FIFO mode.

5.2.5 Retrieve data from FIFO

FIFO data is read through the OUT_X, OUT_Y and OUT_Z registers. When the FIFO is in Stream, Trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y, and Z data are placed in the OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst operations can be used.

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Digital interfaces LIS3DSH

6 Digital interfaces

The registers embedded inside the LIS3DSH may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.

The serial interfaces are mapped onto the same pins. To select/exploit the I CS line must be tied high (i.e. connected to Vdd_IO).

Table 9. Serial interface pin description

Pin name Pin description

SPI enable

SCL SPC

SDA

SDI

SDO

I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled)

C serial clock (SCL)

SPI serial port clock (SPC)

C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO)

C interface, the

SEL

SDO

I2C address selection SPI serial data output (SDO)

6.1 I2C serial interface

The LIS3DSH I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back.

The relevant I

Table 10. Serial interface pin description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master

There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bi-directional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both lines are high.

The I

C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal

mode.

C terminology is given in the table below.

Term Description

The device which initiates a transfer, generates clock signals and terminates a transfer

Slave The device addressed by the master

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LIS3DSH Digital interfaces

6.1.1 I2C operation

The transaction on the bus is started through a start (ST) signal. A start condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The slave address (SAD) associated to the LIS3DSH is 00111xxb whereas the xx bits are modified by the SEL/SDO pin in order to modify the device address. If the SEL pin is connected to the voltage supply, the address is 0011101b, otherwise the address is 0011110b if the SEL pin is connected to ground. This solution permits to connect and address two different accelerometers to the same I

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I

C embedded inside the LIS3DSH behaves as a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSb represents the actual register address while the ADD_INC bit (CTRL_REG6) defines the address increment.

C lines.

The slave address is completed with a read/write bit. If the bit is ‘1’ (Read), a repeated start (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write), the master transmits to the slave with direction unchanged. Table 11 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 11. SAD+Read/Write patterns

Command SAD[6:2] SAD[1] = SEL SAD[0] = SEL R/W SAD+R/W

Write 00111 1 0 0 00111100

Write 00111 0 1 0 00111010

Table 12. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP

Slave SAK SAK SAK

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Digital interfaces LIS3DSH

Table 13. Transfer when master is writing multiple bytes to slave:

Master ST SAD + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

Table 14. Transfer when master is receiving (reading) one byte of data from slave:

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW, to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In the presented communication format, MAK is Master acknowledge and NMAK is No Master Acknowledge.

6.2 SPI bus interface

The LIS3DSH SPI is a bus slave. The SPI allows to write and read the registers of the device.

The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

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LIS3DSH Digital interfaces

Figure 6. Read and write protocol

SPC

SDI

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AM10129V1

SDO

AD5 AD4 AD3 AD2 AD1 AD0

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS.

bit 0: RW

bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)

from the device is read. In the latter case, the chip drives SDO at the start of bit 8.

bit 1-7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods are added. When the ADD_INC(CTRL_REG6) bit is ‘0’, the address used to read/write data remains the same for every block. When the ADD_INC bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

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Digital interfaces LIS3DSH

6.2.1 SPI read

Figure 7. SPI read protocol

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD0

SDO

DO7 DO6 DO5 DO4 DO3DO2 DO1 DO0

AM10130V1

The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one.

bit 0: READ bit. The value is 1.

bit 1-7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

bit 16-... : data DO(...-8). Further data in multiple byte reading.

Figure 8. Multiple bytes SPI read protocol (2-byte example)

C S

SPC

SDI

AD5 AD4AD3 AD2 AD1 AD0

M S

SDO

DO7 DO6DO5DO4DO3 DO 2 DO 1 DO 0

DO15 DO 14 DO 13 DO 12 DO11 DO 10 D O9 DO8

AM10131V1

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LIS3DSH Digital interfaces

6.2.2 SPI write

Figure 9. SPI write protocol

SPC

SDI

AD5 AD 4 AD 3 AD2 AD1 AD0MS

The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one.

bit 0: WRITE bit. The value is 0.

bit 1 -7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb

first).

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

AM10132V1

bit 16-... : data DI(...-8). Further data in multiple byte writing.

Figure 10. Multiple bytes SPI write protocol (2-byte example)

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD0

6.2.3 SPI read in 3-wire mode

3-wire mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) by internal register.

DI7 DI6 DI 5 D I4 DI3 DI 2 DI1 DI 0 DI 15 D I1 4 DI 13 DI12 DI11 DI 10 DI9 DI 8

AM10133V1

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Digital interfaces LIS3DSH

Figure 11. SPI read protocol in 3-wire mode

SPC

SDI/O

AD5 AD 4 AD 3 AD2 AD1 AD 0MS

The SPI read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.

bit 1-7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

Multiple read command is also available in 3-wire mode.

DO7 DO6 DO5 DO4 DO3 DO2 DO 1 DO 0

AM10134V1

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LIS3DSH Register mapping

7 Register mapping

Table 16 provides a list of the 8/16-bit registers embedded in the device and the related

address:

Table 16. Register address map

Name Type

Hex Binary

INFO1 r 0D 00001101 0010 0001 Information register 1

INFO2 r 0E 00001110 0000 0000 Information register 2

WHO_AM_I r OF 00001111 0011 1111 Who I am ID

CTRL_REG3 r/w 23 00100011 -

CTRL_REG4 r/w 20 00100000 -

CTRL_REG5 r/w 24 00100100 -

CTRL_REG6 r/w 25 00100101 -

STATUS r 27 00100111 - Status data register

OUT_T r 0C 00001100 - Temperature output

OFF_X r/w 10 00010000 0000 0000 X-axis offset correction

Default Comment

Control registers

OFF_Y r/w 11 00010001 0000 0000 Y-axis offset correction

OFF_Z r/w 12 00010010 0000 0000 Z-axis offset correction

CS_X r/w 13 00010011 0000 0000 Constant shift X

CS_Y r/w 14 00010100 0000 0000 Constant shift Y

CS_Z r/w 15 00010101 0000 0000 Constant shift Z

LC_L r/w 16 00010110 0000 0001

LC_H r/w 17 00010111 0000 0000

STAT r 18 00011000 - Interrupt synchronization

VFC_1 r/w 1B 00011011 - Vector filter coefficient 1

VFC_2 r/w 1C 00011100 - Vector filter coefficient 2

VFC_3 r/w 1D 00011101 - Vector filter coefficient 3

VFC_4 r/w 1E 00011110 - Vector filter coefficient 4

THRS3 r/w 1F 00011111 - Threshold value 3

OUT_X_L r 28 00101000

OUT_X_H r 29 00101001

OUT_Y_L r 2A 00101010

0000 0000 Output registers

OUT_Y_H r 2B 00101011

OUT_Z_L r 2C 00101100

Long counter registers

OUT_Z_H r 2D 00101101

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Table 16. Register address map (continued)

Name Type

Hex Binary

Default Comment

FIFO_CTRL r/w 2E 00101110 0000 0000

FIFO_SRC r 2F 00101111 -

CTRL_REG1 r/w 21 00100001 0000 0000 SM1 control register

ST1_X w 40-4F

TIM4_1 w 50 01010000 -

TIM3_1 w 51 01010001 -

TIM2_1 w 52-53

TIM1_1 w 54-55

THRS2_1 w 56 01010110 - SM1 threshold value 1

THRS1_1 w 57 01010111 - SM1 threshold value 2

MASK1_B w 59 01011001 - SM1 axis and sign mask

MASK1_A w 5A 01011010 - SM1 axis and sign mask

SETT1 w 5B 01011011 - SM1 detection settings

PR1 r 5C 01011100 - Program-reset pointer

TC1 r 5D-5E

OUTS1 r 5F 01011111 - Main set flag

01000000 01001111

01010010 01010011

01010100 01010101

01011101 01011110

- Timer counter

FIFO registers

SM1 code register

(X =1-16)

SM1 general timer

PEAK1 r 19 00011001 - Peak value

CTRL_REG2 r/w 22 00100010 - SM2 control register

ST2_X w 60-6F

TIM4_2 w 70 01110000 -

TIM3_2 w 71 01110001 -

TIM2_2 w 72-73

TIM1_2 w 74-75

THRS2_2 w 76 01110110 - SM2 threshold value 1

THRS1_2 w 77 01110111 - SM2 threshold value 2

MASK2_B w 79 01111001 - SM2 axis and sign mask

MASK2_A w 7A 01111010 SM2 axis and sign mask

SETT2 w 7B 01111011 - SM2 detection settings

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01100000 01101111

01110010 01110011

01110100 01110101

SM2 code register

(X =1-16)

SM2 general timer

LIS3DSH Register mapping

Table 16. Register address map (continued)

Name Type

Hex Binary

PR2 r 7C 01111100 - Program-reset pointer

Default Comment

TC2 r 7D-7E

OUTS2 r 7F 01111111 Main set flag

PEAK2 r 1A 00011010 - Peak value

DES2 w 78 01111000 - Decimation factor

01111101 01111110

- Timer counter

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8 Register description

8.1 INFO1 (0Dh)

Read only information register.

Table 17. INFO1 register default value

00100001

8.2 INFO2 (0Eh)

Read only information register.

Table 18. INFO2 register default value

00000000

8.3 WHO_AM_I (0Fh)

Who_AM_I register.

Table 19. WHO_AM_I register default value

00111111

8.4 CTRL_REG3 (23h)

Control register 3.

Table 20. Control register 3

DR_EN IEA IEL INT2_EN INT1_EN VFILT - STRT

Table 21. CTRL_REG3 register description

DR_EN

IEA

IEL

INT2_EN

INT1_EN

DRDY signal enable to INT1. Default value:0 0 = data ready signal not connected, 1 = data ready signal connected to INT1

Interrupt signal polarity. Default value:0 0 = interrupt signals active LOW, 1 = interrupt signals active HIGH

Interrupt signal latching. Default value:0 0 = interrupt signals latched, 1 = interrupt signal pulsed

Interrupt 2 enable/disable. Default value:0 0 = INT2 signal disabled, 1 = INT2 signal enabled

Interrupt 2 enable/disable. Default Value:0 0 = INT1/DRDY signal disabled, 1 = INT1/DRDY signal enabled

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LIS3DSH Register description

Table 21. CTRL_REG3 register description (continued)

VFILT

STRT

Vector filter enable/disable. Default value:0 0 = vector filter disabled, 1 = vector filter enabled

Soft reset bit 0 = no soft reset, 1 = soft reset (POR function)

8.5 CTRL_REG4 (20h)

Control register 4.

Table 22. Control register 4

ODR3 ODR2 ODR1 ODR0 BDU ZEN YEN XEN

Table 23. CTRL_REG4 register description

ODR 3:0 Output data rate and power mode selection. Default value:0000 (see Table 24)

BDU

Zen

Ye n

Xen

Block data update. Default value:0 0:continuos update,1:output registers not updated until MSB and LSB reading)

Z axis enable. Default value:1 (0:Z axis disabled; 1:Z axis enabled)

Y axis enable. Default value:1 (0:Y axis disabled; 1:Y axis enabled)

X axis enable. Default value:1 0=X axis disabled; 1=X axis enabled

ODR<3:0> is used to set Power Mode and ODR selection. In Table 24 (output data rate selection Table 22) all frequencies available are reported.

Table 24. CTRL4 ODR configuration

ODR3 ODR2 ODR1 ODR0 ODR selection

0000Power down

00013.125 Hz

00106.25 Hz

0 0 1 1 12.5 Hz

010025 Hz

010150 Hz

0110100 Hz

0111400 Hz

1000800 Hz

1 0 0 1 1600 Hz

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The BDU bit is used to inhibit the output registers update until both upper and lower register parts are read. In default mode (BDU=‘0’) the output register values are updated continuously. If for any reason it is not sure whether to read faster than the output data rate it is recommended to set the BDU bit to ‘1’. In this way the content of output registers is not updated until both MSb and LSb are read avoiding the reading of values related to a different sample time.

8.6 CTRL_REG5 (24h)

Control register 5.

Table 25. Control register 5

BW2 BW1 FSCALE2 FSCALE1 FSCALE0 ST2 ST1 SIM

Table 26. Control register 5 description

BW2:BW1 Anti-aliasing filter bandwidth. Default value: 00

00=800 Hz; 01=400 Hz; 10:=200 Hz; 11:=50 Hz)

FSCALE2:0 Full-scale selection. Default value: 00

000=+/- 2G; 001=+/- 4G; 010=+/- 6G; 011=+/- 8G; 100=+/- 16G

ST2:1 Self-test enable. Default value: 00

00=self-test disabled;

SIM SPI serial interface mode selection. Default value: 0

0=4-wire interface; 1:=3-wire interface

Table 27. Self-test mode selection

ST2 ST1 Self test mode

0 0 Normal mode

0 1 Positive sign self-test

1 0 Negative sign self-test

1 1 Not allowed

8.7 CTRL_REG6 (25h)

Control register 6.

Table 28. Control register 6

BOOOT FIFO_EN WTM_EN

ADD_

INC

P1_

EMPTY

P1_WTM

P1_OVER

RUN

P2_

BOOT

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LIS3DSH Register description

Table 29. Control register 6 description

BOOT Force reboot, cleared as soon as the reboot is finished. Active high.

FIFO_EN FIFO enable. Default value 0.

0=disable; 1=enable

WTM_EN Enable FIFO Watermark level use. Default value 0.

0=disable; 1=enable

ADD_INC Register address automatically incremented during a multiple byte access with a

serial interface (I 0=disable; 1=enable

P1_EMPTY Enable FIFO Empty indication on int1. Default value 0.

0=disable; 1=enable

P1_WTM FIFO Watermark interrupt on int1. Default value 0.

0:=disable; 1=enable

P1_OVERRUN FIFO overrun interrupt on int1. Default value 0.

0=disable; 1=enable

P2_BOOT BOOT interrupt on int2. Default value 0.

0=disable; 1=enable

8.8 STATUS (27h)

Status register.

Table 30. Status register

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 31. Status register description

ZYXOR X, Y, and Z axis data overrun. Default value: 0

0=no overrun has occurred; 1=a new set of data has overwritten the previous ones

ZOR Z axis data overrun. Default value: 0

0=no overrun has occurred; 1=a new set of data for the Z-axis has overwritten the previous one

YOR Y axis data overrun. Default value: 0

0=no overrun has occurred; 1=a new data for the Y-axis has overwritten the previous one

XOR X axis data overrun. Default value: 0

0=no overrun has occurred; 1=a new data for the X-axis has overwritten the previous one

ZYXDA X, Y, and Z axis new data available. Default value: 0

0=a new set of data is not yet available; 1=a new set of data is available

C or SPI).

ZDA Z axis new data available. Default value: 0

0=a new data for the Z-axis is not yet available; 1=a new data for the Z-axis is available

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Table 31. Status register description (continued)

YDA Y axis new data available. Default value: 0

0=a new data for the Y-axis is not yet available; 1=a new data for the Y-axis is available

XDA X axis new data available. Default value: 0

0=a new data for the X-axis is not yet available; 1=a new data for the X-axis is available

8.9 OUT_T (0Ch)

Temperature output register. Temperature data (1LSB/deg - 8-bit resolution). The value is expressed as two's complement.

Table 32. OUT_T register

Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0

Table 33. OUT_T register description

Temp7-Temp0 Temperature data.

8.10 OFF_X (10h)

Offset correction X-axis register,signed value.

Table 34. Offset X default value

00000000

8.11 OFF_Y (11h)

Offset correction Y-axis register, signed value.

Table 35. Offset Y default value

00000000

8.12 OFF_Z (12h)

Offset correction Z-axis register, signed value.

Table 36. Offset Z default value

00000000

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8.13 CS_X (13h)

Constant shift signed value X-axis register - state machine only.

Table 37. Constant shift X-axis default value

00000000

8.14 CS_Y (14h)

Constant shift signed value Y-axis register - state machine only.

Table 38. Constant shift Y-axis default value

00000000

8.15 CS_Z (15h)

Constant shift signed value Y-axis register - state machine only.

Table 39. Constant shift Y-axis default value

00000000

8.16 LC (16h - 17h)

16-bit long-counter register for interrupt state machine programs timing.

Table 40. LC_L default value

00000001

Table 41. LC_H default value

00000000

01h=counting stopped, 00h=counter full:interrupt available and counter is set to default. Values higher than 00h:counting

8.17 STAT (18h)

Interrupt status - interrupt synchronization register.

Table 42. STAT register

LONG SYNCW SYNC1 SYNC2 INT_SM1 INT_SM2 DOR DRDY

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Table 43. STAT register description

LONG 0=no interrupt, 1=long counter (LC) interrupt flag common for both SM

SYNCW

SYNC1 0=SM1 running normally, 1=SM1 stopped and await restart request from SM2

SYNC2 0=SM2 running normally, 1=SM2 stopped and await restart request from SM1

INT_SM1 SM1 - Interrupt Selection - 1=SM1 interrupt enable; 0: SM1 interrupt disable

NT_SM2 SM2 - Interrupt Selection - 1=SM2 interrupt enable; 0: SM2 interrupt disable

DOR

Synchronization for external Host Controller interrupt based on output data 0=no action waiting from host; 1=action from host based on output data

Data overrun indicates not read data from output register when next data samples measure start; 0=no overrun, 1=data overrun data overrun bit is reset when next sample is ready

DRDY

data ready from output register 0=data not ready, 1=data ready

8.18 VFC_1 (1Bh)

Vector coefficient register 1 for DIff filter.

Table 44. Vector filter coefficient register 1 default value

00000000

8.19 VFC_2 (1Ch)

Vector coefficient register 2 for DIff filter.

Table 45. Vector filter coefficient register 2 default value

00000000

8.20 VFC_3 (1Dh)

Vector coefficient register 3 for FSM2 filter.

Table 46. Vector filter coefficient register 3 default value

00000000

8.21 VFC_4 (1Eh)

Vector coefficient register 4 for DIff filter.

Table 47. Vector filter coefficient register 4 default value

00000000

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8.22 THRS3 (1Fh)

Threshold value e register.

Table 48. Threshold value register 3 default value

00000000

8.23 OUT_X (28h - 29h)

X-axis output register.

Table 49. OUT_X_L register default value

00000000

Table 50. OUT_X_H register default value

00000000

8.24 OUT_Y (2Ah - 2Bh)

Y-axis output register.

Table 51. OUT_Y_L register default value

00000000

Table 52. OUT_Y_H register default value

00000000

8.25 OUT_Z (2Ch - 2Dh)

Z-axis output register.

Table 53. OUT_Z_L register default value

00000000

Table 54. OUT_Z_H register default value

00000000

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8.26 FIFO_CTRL (2Eh)

FIFO control register.

Table 55. FIFO control register

FMODE2 FMODE1 FMODE0 WTMP4 WTMP3 WTMP2 WTMP1 WTMP4

FMODE2:FMODE0 = FIFO Mode Selection.

WTMP4:WTMP0 = FIFO Watermark pointer; FIFO deep if the Watermark is enabled.

Table 56. FIFO mode selection

FMODE2 FMODE1 FMODE0 Mode

0 0 0 Bypass Mode. FIFO turned off

0 0 1 FIFO Mode. Stop collecting data

when FIFO is full.

0 1 0 Stream Mode. If the FIFO is full

the new sample overwrites the older one

0 1 1 Stream mode until trigger is de-

1 0 0 Bypass mode until trigger is de-

101Not Used

110Not Used.

1 1 1 Bypass mode until trigger is de-

The FIFO trigger is the INT2 source.

8.27 FIFO_SRC (2Fh)

FIFO SRC control register.

Table 57. FIFO_SRC register

WTM

OVRN_

FIFO

asserted, then FIFO mode

asserted, then Stream mode

asserted, then FIFO mode

EMPTY FSS4 FSS3 FSS2 FSS1 FSS0

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Table 58. FIFO_SRC register description

WTM Watermark status.

0=FIFO filling is lower than WTM level; 1=FIFO filling is equal or higher than WTM level

OVRN_FIFO Overrun bit status. 0=FIFO is not completely filled; 1=FIFO is completely filled

EMPTY FIFO empty bit.

0=FIFO not empty; 1=FIFO empty)

FSS4-FSS0 FIFO stored data level

8.28 CTRL_REG1 (21h)

SM1 control register.

Table 59. SM1 control register

HYST2_1 HYST1_1 HYST0_1 - SM1_PIN - - SM1_EN

Table 60. SM1 control register structure

HYST2_1 HYST1_1 HYST0_1

SM1_PIN

SM1_EN

Hysteresis unsigned value to be added or subtracted from threshold value in SM1 Default value=000

0=SM1 interrupt routed to INT1, 1=SM1 interrupt routed to INT2 pin Default value=0

0=SM1 disabled, 1=SM1 enabled Default value=0

8.29 STx_1 (40h-4Fh)

State machine 1 code register STx_1 (x = 1-16).

State machine 1 system register is made up of 16, 8- bit registers to implement 16-step opcode.

8.30 TIM4_1 (50h)

8-bit general timer (unsigned value) for SM1 operation timing.

Table 61. Timer4 default value

00000000

8.31 TIM3_1 (51h)

8-bit general timer (unsigned value) for SM1 operation timing.

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Table 62. Timer3 default value

00000000

8.32 TIM2_1 (52h - 53h)

16-bit general timer (unsigned value) for SM1 operation timing.

Table 63. TIM2_1_L default value

00000000

Table 64. TIM2_1_H default value

00000000

8.33 TIM1_1 (54h - 55h)

16-bit general timer (unsigned value) for SM1 operation timing.

Table 65. TIM1_1_L default value

00000000

Table 66. TIM1_1_H default value

00000000

8.34 THRS2_1 (56h)

Threshold value for SM1 operation.

Table 67. THRS2_1 default value

00000000

8.35 THRS1_1 (57h)

Threshold value for SM1 operation.

Table 68. THRS1_1 default value

00000000

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8.36 MASK1_B (59h)

Axis and sign mask (swap) for SM1 motion detection operation.

Table 69. MASK1_B axis and sign mask register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Table 70. MASK1_B register structure

P_X

N_X 0=X - disabled, 1=X – enabled

0=X + disabled, 1=X + enabled

P_Y

N_Y 0=Y- disabled, 1=Y – enabled

P_Z

N_Z 0=Z - disabled, 1=Z – enabled

P_V

N_V 0=V - disabled, 1=V – enabled

0=Y+ disabled, 1=Y + enabled

0=Z + disabled, 1=Z + enabled

0=V + disabled, 1=V + enabled

8.37 MASK1_A (5Ah)

Axis and sign mask (default) for SM1 motion detection operation.

Table 71. MASK1_A axis and sign mask register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Table 72. MASK1_A register structure

P_X

N_X 0=X - disabled, 1=X – enabled

P_Y

N_Y 0=Y - disabled, 1=Y – enabled

0=X + disabled, 1=X + enabled

0=Y + disabled, 1=Y + enabled

P_Z

N_Z 0=Z - disabled, 1= Z – enabled

P_V

N_V 0=V - disabled, 1=V – enabled

0=Z + disabled, 1=Z + enabled

0=V + disabled, 1=V + enabled

8.38 SETT1 (5Bh)

Setting of threshold, peak detection and flags for SM1 motion detection operation.

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Table 73. SETT1 register structure

P_DET THR3_SA ABS - - THR3_MA R_TAM SITR

Table 74. SETT1 register description

P_DET

THR3_SA

ABS

THR3_MA

R_TAM

SITR

8.39 PR1 (5Ch)

Program and reset pointer for SM1 motion detection operation.

Table 75. PR1 register

PP3 PP2 PP1 PP0 RP3 RP2 RP1 RP0

SM1 peak detection. Default value:0

0=peak detection disabled, 1=peak detection enabled

Default value:0 0=no action, 1=threshold 3 limit value for axis and sign mask reset (MASKB_1)

Default value:0

0=unsigned thresholds, 1=signed thresholds

Default value:0 0=no action, 1=threshold 3 limit value for axis and sign mask reset (MASKA_1)

Next condition validation flag. Default value:0

0=no valid next condition found, 1=valid next condition found and reset

Default value:0 0=no actions, 1=program flow can be modified by STOP and CONT commands

Table 76. PR1 register description

PP3-PP0 SM1 program pointer address

RP3-RP0 SM1 reset pointer address

8.40 TC1 (5Dh-5E)

16-bit general timer (unsigned output value) for SM1 operation timing.

Table 77. TC1_L default value

00000000

Table 78. TC1_H default value

00000000

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8.41 OUTS1 (5Fh)

Output flags on axis for interrupt SM1 management.

Table 79. OUTS1 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Read action of this register, depending on the flag affects SM1 interrupt functions.

Table 80. OUTS1 register description

P_X 0=X + no show, 1=X+ show

N_X 0=X - no show, 1=X – show

P_Y 0=Y + no show, 1=Y + show

N_Y 0=Y - no show, 1=Y – show

P_Z 0=Z + no show, 1=Z + show

N_Z 0=Z - no show, 1=Z – show

P_V 0=V + no show, 1=V + show

N_V 0=V - no show, 1=V – show

8.42 PEAK1 (19h)

Peak detection value register for SM1 operation.

Table 81. PEAK1 default value

00000000

Peak detected value for next condition SM1.

8.43 CTRL_REG2 (22h)

State program 2 interrupt MNG - SM2 control register.

Table 82. SM2 control register

HYST2_2 HYST1_2 HYST0_2 - SM2_PIN - - SM2_EN

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Table 83. SM2 control register description

HYST2_2 HYST1_2 HYST0_2

Hysteresis unsigned value to be added or subtracted from threshold value in SM2. Default value=000

SM2_PIN

SM2_EN

0=SM2 interrupt routed to INT1, 1=SM2 interrupt routed to INT1 pin. Default value=0

0=SM2 disabled, 1=SM2 enabled. Default value=0

8.44 STx_1 (60h-6Fh)

State Machine 2 code register STx_1 (x = 1-16).

State machine 2 system register is made up of 16 8-bit registers, to implement 16-step opcode.

8.45 TIM4_2 (70h)

8-bit general timer (unsigned value) for SM2 operation timing.

Table 84. Timer4 default value

00000000

8.46 TIM3_2 (71h)

8-bit general timer (unsigned value) for SM2 operation timing.

Table 85. Timer3 default value

00000000

8.47 TIM2_2 (72h - 73h)

16-bit general timer (unsigned value) for SM2 operation timing.

Table 86. TIM2_2_L default value

00000000

Table 87. TIM2_2_H default value

00000000

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8.48 TIM1_2 (74h - 75h)

16-bit general timer (unsigned value) for SM2 operation timing.

Table 88. TIM1_2_L default value

00000000

Table 89. TIM1_2_H default value

00000000

8.49 THRS2_2 (76h)

Threshold signed value for SM2 operation.

Table 90. THRS2_2 default value

00000000

8.50 THRS1_2 (77h)

Threshold signed value for SM2 operation.

Table 91. THRS1_2 default value

00000000

8.51 MASK2_B (79h)

Axis and sign mask (swap) for SM2 motion detection operation.

Table 92. MASK2_B axis and sign mask register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Table 93. MASK2_B register description

P_X 0=X + disabled, 1=X + enabled

N_X 0=X - disabled, 1=X – enabled

P_Y 0=Y + disabled, 1=Y + enabled

N_Y 0=Y - disabled, 1=Y – enabled

P_Z 0=Z + disabled, 1=Z + enabled

N_Z 0=Z - disabled, 1=Z – enabled

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Table 93. MASK2_B register description

P_V 0=V + disabled, 1=V + enabled

N_V 0=V - disabled, 1=V – enabled

8.52 MASK2_A (7Ah)

Axis and sign mask (default) for SM2 motion detection operation.

Table 94. MASK2_A axis and sign mask register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Table 95. MASK2_B register description

P_X

N_X 0=X - disabled, 1=X – enabled

0=X + disabled, 1=X + enabled

P_Y

N_Y 0=Y - disabled, 1=Y – enabled

P_Z

N_Z 0=Z - disabled, 1=Z – enabled

P_V

N_V 0=V - disabled, 1=V – enabled

0=Y + disabled, 1=Y + enabled

0=Z + disabled, 1=Z + enabled

0=V + disabled, 1=V + enabled

8.53 SETT2 (7Bh)

Setting of threshold, peak detection and flags for SM2 motion detection operation.

Table 96. SETT2 register

P_DET THR3_SA ABS - - THR3_MA R_TAM SITR

Table 97. SETT2 register description

P_DET

THR3_SA

ABS

THR3_MA

SM2 peak detection. Default value: 0 0=peak detection disabled, 1=peak detection enabled

Default value: 0 0=no action, 1=threshold 3 limit value for axis and sign mask reset (MASK2_B)

Default value: 0 0=unsigned thresholds, 1=signed thresholds

Default value: 0 0=no action, 1=threshold 3 limit value for axis and sign mask reset (MASK2_A)

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Table 97. SETT2 register description

R_TAM

SITR

Next condition validation flag. Default value:0 0=no valid next condition found, 1=valid next condition found and reset

Default value: 0 0=no actions, 1=program flow can be modified by STOP and CONT commands

8.54 PR2 (7Ch)

Program and reset pointer for SM2 motion detection operation.

Table 98. PR2 register

PP3 PP2 PP1 PP0 RP3 RP2 RP1 RP0

Table 99. PR2 register description

PP3-PP0

RP3-RP0 SM2 reset pointer address

SM2 program pointer address

8.55 TC2 (7Dh-7E)

16-bit general timer (unsigned output value) for SM2 operation timing.

Table 100. TC2_L default value

00000000

Table 101. TC2_H default value

00000000

8.56 OUTS2 (7Fh)

Output flags on axis for interrupt SM2 management.

Table 102. OUTS2 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Read action of this register, depending on the flag affects SM2 interrupt functions.

Table 103. OUTS2 register description

P_X

N_X 0=X - no show, 1=X – show

0=X + no show, 1=X + show

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Table 103. OUTS2 register description

P_Y

N_Y 0=Y - no show, 1=Y – show

0=Y + no show, 1=Y + show

P_Z

N_Z 0=Z - no show, 1=Z – show

P_V

N_V 0=V - no show, 1=V – show

0=Z + no show, 1=Z + show

0=V + no show, 1=V + show

8.57 PEAK2 (1Ah)

Peak detection value register for SM2 operation.

Table 104. PEAK2 default value

00000000

Peak detected value for next condition SM2.

8.58 DES2 (78h)

Decimation counter value register for SM2 operation.

Table 105. DES2 default value

00000000

Registers marked as ‘Reserved’ must not be changed. The writing to those registers may cause permanent damages to the device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

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LIS3DSH Package information

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK

packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Figure 12. LGA-16: mechanical data and package dimensions

Dimensions

Ref.

A1 1.000 0.0394

A2 0.7850.0309

A3 0.200 0.0079

D1 2.850 3.000 3.150 0.1122 0.1181 0.1240

E1 2.850 3.000 3.150 0.1122 0.1181 0.1240

L1 1.000 1.060 0.0394 0.0417

L2 2.000 2.060 0.07870.0811

N1 0.500 0.0197

N2 1.000 0.0394

M 0.040 0.100 0.160 0.0016 0.0039 0.0063

P1 0.875 0.0344

P2 1.275 0.0502

T1 0.2900.350 0.410 0.0114 0.0138 0.0161

T2 0.190 0.250 0.310 0.0075 0.0098 0.0122

d 0.150 0.0059

k 0.050 0.0020

mm inch

Min. Typ. M ax. M in. Typ. M ax.

Land Grid Array Package

Outline and

mechanical data

LGA-16 (3x3x1.0mm)

7983231

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Revision history LIS3DSH

10 Revision history

Table 106. Document revision history

Date Revision Changes

26-Oct-2011 1 Initial release.

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LIS3DSH

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Doc ID 022405 Rev 1 53/53

ST LIS3DSH User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Contents

2 Block diagram and pin description

2.1 Block diagram

Figure 1. Block diagram

2.2 Pin description

Figure 2. Pin connection

Table 2. Pin description

3 Mechanical and electrical specifications

3.1 Mechanical characteristics

Table 3. Mechanical characteristics

3.2 Electrical characteristics

Table 4. Electrical characteristics

3.3 Communication interface characteristics

3.3.1 SPI - serial peripheral interface

Table 5. SPI slave timing values

Figure 3. SPI slave timing diagram

3.3.2 I2C - inter IC control interface

Table 6. I2C slave timing values

Figure 4. I2C slave timing diagram

3.4 Absolute maximum ratings

Table 7. Absolute maximum ratings

3.5 Terminology

3.5.1 Sensitivity

3.5.2 Zero-g level

3.6 Functionality

3.6.1 Self-test

3.7 Sensing element

3.8 IC interface

3.9 Factory calibration

4 Application hints

Figure 5. LIS3DSH electrical connection

4.1 Soldering information

5 Digital main blocks

5.1 State machine

Table 8. LIS3DSH state machines: sequence of state to execute an algorithm

5.2 FIFO

5.2.1 Bypass mode

5.2.2 FIFO mode

5.2.3 Stream mode

5.2.4 Stream-to-FIFO mode

5.2.5 Retrieve data from FIFO

6 Digital interfaces

Table 9. Serial interface pin description

6.1 I2C serial interface

Table 10. Serial interface pin description

6.1.1 I2C operation

Table 11. SAD+Read/Write patterns

Table 12. Transfer when master is writing one byte to slave

Table 13. Transfer when master is writing multiple bytes to slave:

Table 14. Transfer when master is receiving (reading) one byte of data from slave:

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

6.2 SPI bus interface

Figure 6. Read and write protocol

6.2.1 SPI read

Figure 7. SPI read protocol

Figure 8. Multiple bytes SPI read protocol (2-byte example)

6.2.2 SPI write

Figure 9. SPI write protocol

Figure 10. Multiple bytes SPI write protocol (2-byte example)

6.2.3 SPI read in 3-wire mode

Figure 11. SPI read protocol in 3-wire mode

7 Register mapping

Table 16. Register address map

8 Register description

8.1 INFO1 (0Dh)

Table 17. INFO1 register default value

8.2 INFO2 (0Eh)

Table 18. INFO2 register default value

8.3 WHO_AM_I (0Fh)

Table 19. WHO_AM_I register default value

8.4 CTRL_REG3 (23h)

Table 20. Control register 3

Table 21. CTRL_REG3 register description

8.5 CTRL_REG4 (20h)

Table 22. Control register 4