ST LIS3DH User Manual

LIS3DH

MEMS digital output motion sensor ultra low-power high performance 3-axes “nano” accelerometer

Features

■Wide supply voltage, 1.71 V to 3.6 V

■Independent IOs supply (1.8 V) and supply voltage compatible

■Ultra low-power mode consumption down to 2 µA

■±2g/±4g/±8g/±16g dynamically selectable fullscale

■I2C/SPI digital output interface

■16 bit data output

■2 independent programmable interrupt generators for free-fall and motion detection

■6D/4D orientation detection

■Free-fall detection

■Motion detection

■Embedded temperature sensor

■Embedded self-test

■Embedded 96 levels of 16 bit data output FIFO

■10000 g high shock survivability

■ECOPACK® RoHS and “Green” compliant

Applications

■Motion activated functions

■Free-fall detection

■Click/double click recognition

■Intelligent power saving for handheld devices

■Pedometer

■Display orientation

■Gaming and virtual reality input devices

■Impact recognition and logging

■Vibration monitoring and compensation

Description

The LIS3DH is an ultra low-power high performance three axes linear accelerometer

LGA-16 (3x3x1 mm)

belonging to the “nano” family, with digital I2C/SPI serial interface standard output. The device features ultra low-power operational modes that allow advanced power saving and smart embedded functions.

The LIS3DH has dynamically user selectable full scales of ±2g/±4g/±8g/±16g and it is capable of measuring accelerations with output data rates from 1 Hz to 5 kHz. The self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself. Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS3DH has an integrated 32-level first in, first out (FIFO) buffer allowing the user to store data for host processor intervention reduction. The LIS3DH is available in small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

Table 1.	Device summary
Order codes		Temp.	Package	Packaging
		range [°C]
LIS3DH		-40 to +85	LGA-16	Tray
LIS3DHTR		-40 to +85	LGA-16	Tape and reel

May 2010

Doc ID 17530 Rev 1

1/42

www.st.com

Contents	LIS3DH

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
	1.1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	1.2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
2	Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . .		10
	2.1	Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2	Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.4	Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . .	12

2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3	Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	3.1	Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15

3.1.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.1 Normal mode, low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.3 6D / 4D orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4	Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	4.1	Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
5	Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19

5.1 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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5.1.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.4 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.5 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6	Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	6.1	I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

6.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

	6.2.1	SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	6.2.2	SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	6.2.3	SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
7	Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
8	Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28

8.1 STATUS_AUX (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.2 OUT_1_L (08h), OUT_1_H (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.3 OUT_2_L (0Ah), OUT_2_H (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.4 OUT_3_L (0Ch), OUT_3_H (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.5 INT_COUNTER (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.6 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.7 TEMP_CFG_REG (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.8 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.9 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.10 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.11 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.12 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.13 CTRL_REG6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.14 REFERENCE/DATACAPTURE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.15 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.16 OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.17 OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.18 OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.19 FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 17530 Rev 1

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Contents			LIS3DH
	8.20	FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 34
	8.21	INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 34
	8.22	INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 35
	8.23	INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 36
	8.24	INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 36
	8.25	CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 36
	8.26	CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 37
	8.27	CLICK_THS (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 38
	8.28	TIME_LIMIT (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 38
	8.29	TIME_LATENCY (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 38
	8.30	TIME WINDOW(3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 38
9	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . 39
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . 41

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LIS3DH	List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. LIS3DH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12. LGA-16: Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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List of tables	LIS3DH

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Operating mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 14. Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 22 Table 16. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22 Table 17. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 18. STATUS_REG_AUX register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 19. STATUS_REG_AUX description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 20. INT_COUNTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 21. WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 22. TEMP_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 23. TEMP_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 24. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 25. CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 26. Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 27. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 28. CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 29. High pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 30. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 31. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 32. CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 33. CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 34. Self test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 35. CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 36. CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 37. CTRL_REG6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 38. REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 39. REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 40. STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 41. STATUS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 42. REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 43. REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 44. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 45. FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 46. INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 47. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 48. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Table 49. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 50. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 51. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 52. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 53. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 54. INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 55. CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 56. CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 57. CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 58. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 59. CLICK_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 60. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 61. TIME_LIMIT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 62. TIME_LIMIT description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 63. TIME_LATENCY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 64. TIME_LATENCY description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 65. TIME_WINDOW register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 66. TIME_WINDOW description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 67. LGA-16: Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 68. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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Block diagram and pin description	LIS3DH

1 Block diagram and pin description

1.1Block diagram

Figure 1. Block diagram

	X+
	Y+	CHARGE
	Z+	AMPLIFIER
a	MUX		A/D
			CONVERTER 1			CS
	Z-
	Y-			CONTROL	I2C	SCL/SPC
	X-			LOGIC		SDA/SDO/SDI
					SPI
						SDO/SA0
ADC1 - ADC Input1
ADC2 - ADC Input2
ADC3 - ADC Input3			A/D
			CONVERTER 2
	TEMPERATURE
	SENSOR
		TRIMMING		96 Level	CONTROL LOGIC		INT 1
SELF TEST	REFERENCE		CLOCK			&
		CIRCUITS		FIFO
					INTERRUPT GEN.		INT 2

1.2Pin description

Figure 2. Pin connection

Z

1

X

Y

(TOP VIEW)

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

				Vdd		ADC2		ADC1			Pin 1 indicator
ADC3											Vdd_IO
		13								1
GND											NC
INT1											NC
RES											SCL/SPC
INT2											GND
		9								5
				CS		SDO/SA0	SDA/SDI/SDO

(BOTTOM VIEW)

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LIS3DH				Block diagram and pin description
	Table 2.	Pin description
	Pin#		Name	Function
	1		Vdd_IO	Power supply for I/O pins
	2		NC	Not connected
	3		NC	Not connected
	4		SCL	I2C serial clock (SCL)
			SPC	SPI serial port clock (SPC)
	5		GND	0V supply
			SDA	I2C serial data (SDA)
	6		SDI	SPI serial data input (SDI)
			SDO	3-wire interface serial data output (SDO)
	7		SDO	SPI serial data output (SDO)
			SA0	I2C less significant bit of the device address (SA0)
	8		CS	SPI enable
				I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
	9		INT2	Inertial interrupt 2
	10		RES	Connect to GND
	11		INT1	Inertial interrupt 1
	12		GND	0 V supply
	13		ADC3	Analog to digital converter input 3
	14		Vdd	Power supply
	15		ADC2	Analog to digital converter input 2
	16		ADC1	Analog to digital converter input 1

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Mechanical and electrical specifications	LIS3DH

2 Mechanical and electrical specifications

2.1Mechanical characteristics

Vdd = 2.5 V, T = 25 °C unless otherwise noted (a)

Table 3.	Mechanical characteristics
Symbol	Parameter	Test conditions	Min.	Typ.(1)	Max.	Unit
		FS bit set to 00		±2.0
	(2)	FS bit set to 01		±4.0
FS	Measurement range
		FS bit set to 10		±8.0
		FS bit set to 11		±16.0		g
		FS bit set to 00		1		mg/digit
So	Sensitivity	FS bit set to 01		2		mg/digit
		FS bit set to 10		4		mg/digit
		FS bit set to 11		12		mg/digit
TCSo	Sensitivity change vs	FS bit set to 00		0.01		%/°C
	temperature
TyOff	Typical zero-g level	FS bit set to 00		±40		mg
	offset accuracy(3),(4)
TCOff	Zero-g level change	Max delta from 25 °C		±0.5		mg/°C
	vs temperature
An	Acceleration noise	FS bit set to 00, Normal Mode		220		ug/sqrt(H
	density	(Table 9), ODR = 100Hz				z)
		FS bit set to 00		276		LSb
		X axis
Vst	Self-test	FS bit set to 00		276		LSb
	output change(5),(6),(7)	Y axis
		FS bit set to 00		984		LSb
		Z axis
Top	Operating		-40		+85	°C
	temperature range

1.Typical specifications are not guaranteed.

2.Verified by wafer level test and measurement of initial offset and sensitivity.

3.Typical zero-g level offset value after MSL3 preconditioning.

4.Offset can be eliminated by enabling the built-in high pass filter.

5.The sign of “Self-test output change” is defined by CTRL_REG4 STsign bit, for all axes.

6.Self-test output changes with the power supply. “Self-test output change” is defined as OUTPUT[LSb](CTRL_REG4 ST bit=1) - OUTPUT[LSb](CTRL_REG4 ST bit=0). 1LSb=1mg, ±2 g Full-scale.

7.Output data reach 99% of final value after 1 ms when enabling self-test mode, due to device filtering.

a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71V to 3.6 V.

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LIS3DH	Mechanical and electrical specifications

2.2Temperature sensor characteristics

Vdd =2.5 V, T=25 °C unless otherwise noted (b)

Table 4.	Temperature sensor characteristics
Symbol	Parameter	Test condition	Min.	Typ.(1)	Max.	Unit
TSDr	Temperature sensor output change vs			1		digit/°C(2)
	temperature
TODR	Temperature refresh rate			ODR		Hz
Top	Operating temperature range		-40		+85	°C

1.Typical specifications are not guaranteed.

2.8-bit resolution.

2.3Electrical characteristics

Vdd = 2.5 V, T = 25 °C unless otherwise noted (c)

Table 5.	Electrical characteristics
Symbol	Parameter	Test conditions	Min.	Typ.(1)	Max.	Unit
Vdd	Supply voltage		1.71	2.5	3.6	V
Vdd_IO	I/O pins supply voltage(2)		1.71		Vdd+0.1	V
Idd	Current consumption in normal mode	50 Hz ODR		11		µA
Idd	Current consumption in normal mode	1 Hz ODR		2		µA
IddLP	Current consumption in low-power mode	50 Hz ODR		6		µA
IddPdn	Current consumption in power-down			0.5		µA
	mode
VIH	Digital high level input voltage		0.8*Vdd_IO			V
VIL	Digital low level input voltage				0.2*Vdd_IO	V
VOH	High level output voltage		0.9*Vdd_IO			V
VOL	Low level output voltage				0.1*Vdd_IO	V
BW	System bandwidth(3)			ODR/2		Hz
Ton	Turn-on time(4)	ODR = 100 Hz		1		ms
Top	Operating temperature range		-40		+85	°C

1.Typical specification are not guaranteed.

2.It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.

3.Referred to Table 25 for the ODR value and configuration.

4.Time to obtain valid data after exiting power-down mode.

b.The product is factory calibrated at 2.5 V.

c.The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

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Mechanical and electrical specifications	LIS3DH

2.4Communication interface characteristics

2.4.1SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 6.	SPI slave timing values
Symbol		Parameter		Value (1)		Unit
			Min		Max
tc(SPC)		SPI clock cycle	100			ns
fc(SPC)		SPI clock frequency			10	MHz
tsu(CS)		CS setup time	6
th(CS)		CS hold time	8
tsu(SI)		SDI input setup time	5
th(SI)		SDI input hold time	15			ns
tv(SO)		SDO valid output time			50
th(SO)		SDO output hold time	9
tdis(SO)		SDO output disable time			50

Figure 3. SPI slave timing diagram
CS	(3)				(3)
	tsu(CS)		tc(SPC)	th(CS)
SPC	(3)				(3)
	tsu(SI)	th(SI)
SDI	(3)	MSB IN		LSB IN	(3)
		tv(SO)	th(SO)		tdis(SO)
SDO	(3)	MSB OUT		LSB OUT	(3)

Note: 1 Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

2Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port.

3When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors.

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2.4.2I2C - Inter IC control interface

Subject to general operating conditions for Vdd and top.

Table 7.	I2C slave timing values
Symbol		Parameter	I2C standard mode (1)		I2C fast mode (1)			Unit
			Min	Max	Min		Max
f(SCL)		SCL clock frequency	0	100	0		400	kHz
tw(SCLL)		SCL clock low time	4.7		1.3			µs
tw(SCLH)		SCL clock high time	4.0		0.6
tsu(SDA)		SDA setup time	250		100			ns
th(SDA)		SDA data hold time	0.01	3.45	0.01		0.9	µs
tr(SDA) tr(SCL)		SDA and SCL rise time		1000	20 + 0.1C	(2)	300
						b		ns
tf(SDA) tf(SCL)		SDA and SCL fall time		300	20 + 0.1C	(2)	300
						b
th(ST)		START condition hold time	4		0.6
tsu(SR)		Repeated START condition	4.7		0.6
		setup time
								µs
tsu(SP)		STOP condition setup time	4		0.6
tw(SP:SR)		Bus free time between STOP	4.7		1.3
		and START condition

1.Data based on standard I2C protocol requirement, not tested in production.

2.Cb = total capacitance of one bus line, in pF.

Figure 4. I2C Slave timing diagram

					REPEATED
					START
	START
				tsu(SR)	START
SDA					tw(SP:SR)
f(SDA)	tr(SDA)		tsu(SDA)	th(SDA)
				tsu(SP)	STOP
SCL
th(ST)	tw(SCLL)	tw(SCLH)	tr(SCL)	tf(SCL)

Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port.

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