ST LIS331HH User Manual
ultra low-power high full-scale 3-axes “nano” accelerometer
Features
■ Wide supply voltage, 2.16 V to 3.6 V
■ Low voltage compatible IOs, 1.8 V
■ Ultra low-current mode consumption
down to 10 µA
■ ±6g/±12g/±24g dynamically selectable full-
scale
2
■ I
C/SPI digital output interface
■ 16 bit data output
■ 2 independent programmable interrupt engines
■ Sleep to wake-up function
■ 6D orientation detection
■ Embedded self-test
■ 10000 g high shock survivability
■ ECOPACK
Section 8)
®
RoHS and “Green” compliant (see
LIS331HH
MEMS digital output motion sensor
Preliminary data
LGA16
accelerometer belonging to the “nano” family, with
digital I
2
C/SPI serial interface standard output.
The device features ultra low-power operational
modes that allow advanced power saving and
smart sleep to wake-up functions.
The LIS331HH has dynamically user selectable
full scales of ±6g/±12g/±24g and it is capable of
measuring accelerations with output data rates
from 0.5 Hz to 1 kHz. The self-test capability
allows the user to check the functioning of the
sensor in the final application.
(3x3x1 mm)
Applications
The device contains 2 indipendent interrupt
engines able to recognize dedicated inertial
■ Pedometer
■ Gaming and virtual reality input devices
■ Motion activated functions
■ Impact recognition and logging
■ Intelligent power saving for handheld devices
■ Vibration monitoring and compensation
events.
Thresholds and timing of interrupt generators are
programmable by the end user on the fly.
The LIS331HH is available in small thin plastic
land grid array package (LGA) and it is
guaranteed to operate over an extended
temperature range from -40 °C to +85 °C.
Description
The LIS331HH is an ultra low-power high
performance high full-scale three axes linear
Table 1. Device summary
Order codes Temperature range [°C] Package Packaging
LIS331HH -40 to +85 LGA16 Tray
LIS331HHTR -40 to +85 LGA16 Tape and reel
October 2009 Doc ID 16366 Rev 1 1/37
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
37
Contents LIS331HH
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.3 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.4 Sleep to wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.3 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/37 Doc ID 16366 Rev 1
LIS331HH Contents
6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 26
7.4 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 HP_FILTER_RESET (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.7 REFERENCE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.8 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.9 OUT_X_L (28h), OUT_X_H (29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.10 OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.11 OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.12 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.13 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.14 INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.15 INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.16 INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.17 INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.18 INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.19 INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 16366 Rev 1 3/37
List of tables LIS331HH
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted . . . . . . . . . . 9
Table 4. Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted . . . . . . . . . . . 10
Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 19
Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19
Table 15. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. Normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 25
Table 20. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. High-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 24. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 25. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 26. Data signal on INT 1 and INT 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 27. CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 28. CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 29. CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 30. CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 31. Sleep to wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 32. REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 33. REFERENCE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 34. STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 35. STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 36. INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 37. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 38. Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 39. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 40. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 41. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 42. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 43. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 44. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 45. INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 46. INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 47. Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 48. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/37 Doc ID 16366 Rev 1
LIS331HH List of tables
Table 49. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 50. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 51. INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 52. INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 53. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 16366 Rev 1 5/37
List of figures LIS331HH
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. I2C slave timing diagram (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. LIS331HH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. LGA16: Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6/37 Doc ID 16366 Rev 1
LIS331HH Block diagram and pin description
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
X+
Y+
Z+
a
Z-
Y-
X-
REFERENCESELF TEST
1.2 Pin description
MUX
CHARGE
AMPLIFIER
TRIMMING
CIRCUITS
A/D
CONVERTER
CONTROL LOGIC
CLOCK
CONTROL
INTERRUPT
LOGIC
&
CS
SCL/SPC
I2C
SDA/SDO/SDI
SPI
SDO/SA0
INT 1
GEN
.
INT 2
Figure 2. Pin connection
Z
X
1
Y
(TOP VIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
13
9
(BOTTOM VIEW)
Pin 1 indicator
1
5
Doc ID 16366 Rev 1 7/37
Block diagram and pin description LIS331HH
Table 2. Pin description
Pin# Name Function
1 Vdd_IO Power supply for I/O pins
2 NC Not connected
3 NC Not connected
4
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
5 GND 0V supply
SDA
6
SDI
SDO
7
SDO
SA0
8CS
2
I
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
I2C less significant bit of the device address (SA0)
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
9 INT 2 Inertial interrupt 2
10 Reserved Connect to GND
11 INT 1 Inertial interrupt 1
12 GND 0 V supply
13 GND 0 V supply
14 Vdd Power supply
15 Reserved Connect to Vdd
16 GND 0 V supply
8/37 Doc ID 16366 Rev 1
LIS331HH Mechanical and electrical specifications
z
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted
12
(2)
Max. Unit
3
6
Symbol Parameter Test conditions Min. Typ.
FS bit set to 00 ±6
FS Measurement range
(3)
FS bit set to 11 ±24
FS bit set to 00
12 bit representation
So Sensitivity
FS bit set to 01
12 bit representation
FS bit set to 11
12 bit representation
TCSo
Ty Of f
TCOff
Sensitivity change vs
temperature
Typical zeroaccuracy
Zero-
g level offset
(4),(5)
g level change vs
temperature
FS bit set to 00 ±0.01 %/°C
FS bit set to 00 ±70 mg
Max delta from 25 °C ±0.4 m
An Acceleration noise density FS bit set to 00 650 µ
Vst
Self-test
output change
(6),(7),(8)
FS bit set to 00
X axis
FS bit set to 00
Y axis
FS bit set to 00
Z axis
50 110 180 LSb
-50 -100 -180 LSb
220 290 370 LSb
Top Operating temperature range -40 +85 °C
Wh Product weight 20 mgram
1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
2. Typical specifications are not guaranteed
3. Verified by wafer level test and measurement of initial offset and sensitivity
4. Typical zero-g level offset value after MSL3 preconditioning
5. Offset can be eliminated by enabling the built-in high pass filter
6. The sign of “Self-test output change” is defined by CTRL_REG4 STsign bit (Table 27), for all axes.
Self-test output changes with the power supply. “Self-test output change” is defined as
7.
OUTPUT[LSb]
scale
8. Output data reach 99% of final value after 1/ODR+1ms when enabling self-test mode, due to device filtering
(CTRL_REG4 ST bit=1)
- OUTPUT[LSb]
(CTRL_REG4 ST bit=0)
. 1LSb=12g/4096 at 12bit representation, ±6 g Full-
(1)
g/digit
m
g/
gFS bit set to 01 ±12
g/°C
H
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Mechanical and electrical specifications LIS331HH
2.2 Electrical characteristics
Table 4. Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted
Symbol Parameter Test conditions Min. Typ.
Vdd Supply voltage 2.16 2.5 3.6 V
Vdd_IO I/O pins supply voltage
Idd
IddLP
IddPdn
VIH
Current consumption
in normal mode
Current consumption
in low-power mode
Current consumption in
power-down mode
Digital high level input
voltage
(3)
1.71 Vdd+0.1 V
0.8*Vdd_IO V
VIL Digital low level input voltage 0.2*Vdd_IO V
VOH High level output voltage 0.9*Vdd_IO V
VOL Low level output voltage 0.1*Vdd_IO V
DR bit set to 00 50
ODR
Output data rate
in normal mode
DR bit set to 01 100
DR bit set to 10 400
DR bit set to 11 1000
(2)
Max. Unit
250 µA
10 µA
1µA
(1)
Hz
PM bit set to 010 0.5
PM bit set to 011 1
ODR
Output data rate
LP
in low-power mode
PM bit set to 100 2
PM bit set to 101 5
PM bit set to 110 10
(5)
(4)
ODR = 100 Hz
ODR/2 Hz
1/ODR+1ms
BW System bandwidth
Ton Turn-on time
Top Operating temperature range -40 +85
1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
2. Typical specification are not guaranteed
3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
4. Refer to Table 19 for filter cut-off frequency
5. Time to obtain valid data after exiting power-down mode
Hz
s
°C
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2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values
(1)
Val u e
Symbol Parameter
Unit
Min Max
tc(SPC) SPI clock cycle 100 ns
fc(SPC) SPI clock frequency 10 MHz
tsu(CS) CS setup time 6
th(CS) CS hold time 8
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15
ns
tv(SO) SDO valid output time 50
th(SO) SDO output hold time 9
tdis(SO) SDO output disable time 50
(2)
h(SI)
MSB OUT
c(SPC)
h(CS)
LSB IN
v(SO)
h(SO)
LSB OUT
dis(SO)
Figure 3. SPI slave timing diagram
CS
(3)
su(CS)
SPC
(3)
su(SI)
(3)
SDI
(3)
SDO
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
MSB IN
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors
(3)
(3)
(3)
(3)
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Mechanical and electrical specifications LIS331HH
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2.3.2 I2C - inter IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I2C slave timing values
Symbol Parameter
I2C standard mode
(1)
I2C fast mode
(1)
Unit
Min Max Min Max
f
(SCL)
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA) tr(SCL)
t
f(SDA) tf(SCL)
t
h(ST)
t
su(SR)
t
su(SP)
t
w(SP:SR)
SCL clock frequency 0 100 0 400 KHz
SCL clock low time 4.7 1.3
SCL clock high time 4.0 0.6
SDA setup time 250 100 ns
SDA data hold time 0 3.45 0.01 0.9 µs
SDA and SCL rise time 1000
SDA and SCL fall time 300
START condition hold time 4 0.6
Repeated START condition
setup time
STOP condition setup time 4 0.6
Bus free time between STOP
and START condition
Figure 4. I2C slave timing diagram
START
(3)
20 + 0.1C
20 + 0.1C
4.7 0.6
4.7 1.3
µs
2)
(
b
2)
(
b
300
ns
300
µs
REPEATED
START
SDA
f(SDA )
r(SDA)
su(SDA)
h(SDA)
SCL
h(ST)
w(SCLL)
1. Data based on standard I
w(SCLH)
2
C protocol requirement, not tested in production
r(SCL)
f(SCL )
2. Cb = total capacitance of one bus line, in pF
3. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
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su(SR)
su(SP)
w(SP:SR)
START
STOP
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