ST LIS2DW12 Application note

AN5038

Application note

LIS2DW12: always-on 3D accelerometer

Introduction

This document is intended to provide usage information and application hints related to ST’s LIS2DW12 motion sensor.

The LIS2DW12 is a 3D digital accelerometer system-in-package with a digital I²C/SPI serial interface standard output, performing at 90 µA in high-resolution mode and below 1 µA in low-power mode. Thanks to the ultra-low noise performance of the accelerometer, the device combines always-on low-power features with superior sensing precision for an optimal motion experience for the consumer. Furthermore, the accelerometer features smart sleep-to-wakeup (activity) and return-to-sleep (inactivity) functions that allow advanced power saving.

The device has a dynamic user-selectable full-scale acceleration range of ±2/±4/±8/±16 g and is capable of measuring accelerations with output data rates from 1.6 Hz to 1600 Hz. The LIS2DW12 can be configured to generate interrupt signals by using hardware recognition of free-fall events, 6D orientation, tap and double-tap sensing, activity or inactivity, and wake-up events.

The LIS2DW12 has an integrated 32-level first-in, first-out (FIFO) buffer allowing the user to store data in order to limit intervention by the host processor.

The LIS2DW12 is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

The ultra-small size and weight of the SMD package make it an ideal choice for handheld portable applications such as smartphones, IoT connected devices, and wearables or any other application where reduced package size and weight are required.

AN5038 - Rev 5 - January 2021	www.st.com
For further information contact your local STMicroelectronics sales office.

AN5038

Pin description

1Pin description

Figure 1. Pin connections

Table 1. Internal pin status

	Pin #	Name	Function	Pin status
	1	SCL	I²C serial clock (SCL)	Default: input without internal pull-up
		SPC	SPI serial port clock (SPC)
			SPI enable
	2	CS	I²C/SPI mode selection	Default: input with internal pull-up(1)
			1: SPI idle mode / I²C communication enabled
			0: SPI communication mode / I²C disabled
	3	SDO	Serial data output (SDO)	Default: input with internal pull-up(2)
		SA0	I²C less significant bit of the device address (SA0)
		SDA	I²C serial data (SDA)
	4	SDI	SPI serial data input (SDI)	Default: (SDA) input without internal pull-up
		SDO	3-wire interface serial data output (SDO)
	5	NC	Internally not connected. Can be tied to VDD, VDDIO, or GND.
	6	GND	0 V supply
	7	RES	Connect to GND
	8	GND	0 V supply
	9	VDD	Power supply
	10	VDD_IO	Power supply for I/O pins
	11	INT2	Interrupt pin 2	Default: push-pull output forced to ground
			Clock input when selected in single data conversion on demand.
	12	INT1	Interrupt pin 1	Default: push-pull output forced to ground

1.In order to disable the internal pull-up on the CS pin, write '1' to the CS_PU_DISC bit in CTRL2 (21h).

2.Internal pull-up on SDO/SA0 pin cannot be disabled: do not connect this pin to GND in low-power applications.

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2Registers

Table 2. Registers

Register name

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

OUT_T_L(1)

0Dh

TEMP3

TEMP2

TEMP1

TEMP0

0

0

0

0

OUT_T_H(1)

0Eh

TEMP11

TEMP10

TEMP9

TEMP8

TEMP7

TEMP6

TEMP5

TEMP4

WHO_AM_I(1)

0Fh

0

1

0

0

0

1

0

0

CTRL1

20h

ODR3

ODR2

ODR1

ODR0

MODE1

MODE0

LP_MODE1

LP_MODE0

CTRL2

21h

BOOT

SOFT_RESET

0

CS_PU_DISC

BDU

IF_ADD_INC

I2C_DISABLE

SIM

CTRL3

22h

ST2

ST1

PP_OD

LIR

H_LACTIVE

0

SLP_MODE

SLP_MODE_1

_SEL

CTRL4_INT1_PAD_CTRL

23h

INT1_6D

INT1_

INT1_WU

INT1_FF

INT1_TAP

INT1_DIFF5

INT1_FTH

INT1_DRDY

SINGLE_TAP

CTRL5_INT2_PAD_CTRL

24h

INT2_

INT2_

INT2_BOOT

INT2_

INT2_OVR

INT2_DIFF5

INT2_FTH

INT2_DRDY

SLEEP_ STATE

SLEEP_CHG

DRDY_T

CTRL6

25h

BW_FILT1

BW_FILT0

FS1

FS0

FDS

LOW_NOISE

0

0

OUT_T(1)

26h

TEMP7

TEMP6

TEMP5

TEMP4

TEMP3

TEMP2

TEMP1

TEMP0

STATUS(1)

27h

FIFO_THS

WU_IA

SLEEP_STATE

DOUBLE_TAP

SINGLE_TAP

6D_IA

FF_IA

DRDY

OUT_X_L(1)

28h

X_L7

X_L6

X_L5

X_L4

X_L3(2)

X_L2(2)

0

0

OUT_X_H(1)

29h

X_H7

X_H6

X_H5

X_H4

X_H3

X_H2

X_H1

X_H0

OUT_Y_L(1)

2Ah

Y_L7

Y_L6

Y_L5

Y_L4

Y_L3(2)

Y_L2(2)

0

0

OUT_Y_H(1)

2Bh

Y_H7

Y_H6

Y_H5

Y_H4

Y_H3

Y_H2

Y_H1

Y_H0

OUT_Z_L(1)

2Ch

Z_L7

Z_L6

Z_L5

Z_L4

Z_L3(2)

Z_L2(2)

0

0

OUT_Z_H(1)

2Dh

Z_H7

Z_H6

Z_H5

Z_H4

Z_H3

Z_H2

Z_H1

Z_H0

FIFO_CTRL

2Eh

FMode2

FMode1

FMode0

FTH4

FTH3

FTH2

FTH1

FTH0

FIFO_SAMPLES(1)

2Fh

FIFO_FTH

FIFO_OVR

Diff5

Diff4

Diff3

Diff2

Diff1

Diff0

TAP_THS_X

30h

4D_EN

6D_THS1

6D_THS0

TAP_THSX_4

TAP_THSX_3

TAP_THSX_2

TAP_THSX_1

TAP_THSX_0

TAP_THS_Y

31h

TAP_PRIOR_2

TAP_PRIOR_1

TAP_PRIOR_0

TAP_THSY_4

TAP_THSY_3

TAP_THSY_2

TAP_THSY_1

TAP_THSY_0

TAP_THS_Z

32h

TAP_X_EN

TAP_Y_EN

TAP_Z_EN

TAP_THSZ_4

TAP_THSZ_3

TAP_THSZ_2

TAP_THSZ_1

TAP_THSZ_0

INT_DUR

33h

LATENCY3

LATENCY2

LATENCY1

LATENCY0

QUIET1

QUIET0

SHOCK1

SHOCK0

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WAKE_UP_THS

34h

SINGLE_

SLEEP_ON

WK_THS5

WK_THS4

WK_THS3

WK_THS 2

WK_THS 1

WK_THS 0

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DOUBLE_TAP

WAKE_UP_DUR

35h

FF_DUR5

WAKE_DUR1

WAKE_DUR0

STATIONARY

SLEEP_DUR3

SLEEP_DUR2

SLEEP_DUR1

SLEEP_DUR0

<![if ! IE]> <![endif]>AN5038	FREE_FALL	36h	FF_DUR4	FF_DUR3	FF_DUR2	FF_DUR1	FF_DUR0	FF_THS2	FF_THS1	FF_THS0
	Register name	Address	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
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<![if ! IE]> <![endif]>5Rev	STATUS_DUP(1)	37h	OVR	DRDY_T	SLEEP_STATE_IA	DOUBLE_TAP	SINGLE_TAP	6D_IA	FF_IA	DRDY
	WAKE_UP_SRC(1)	38h	0	0	FF_IA	SLEEP_STATE IA	WU_IA	X_WU	Y_WU	Z_WU
	TAP_SRC(1)	39h	0	TAP_IA	SINGLE_TAP	DOUBLE_TAP	TAP_SIGN	X_TAP	Y_TAP	Z_TAP
	SIXD_SRC(1)	3Ah	0	6D_IA	ZH	ZL	YH	YL	XH	XL
	ALL_INT_SRC(1)	3Bh	0	0	SLEEP_	6D_IA	DOUBLE_TAP	SINGLE_TAP	WU_IA	FF_IA
					CHANGE_IA
	X_OFS_USR	3Ch	X_OFS_USR_7	X_OFS_USR_6	X_OFS_USR_5	X_OFS_USR_4	X_OFS_USR_3	X_OFS_USR_2	X_OFS_USR_1	X_OFS_USR_0
	Y_OFS_USR	3Dh	Y_OFS_USR_7	Y_OFS_USR_6	Y_OFS_USR_5	Y_OFS_USR_4	Y_OFS_USR_3	Y_OFS_USR_2	Y_OFS_USR_1	Y_OFS_USR_0
	Z_OFS_USR	3Eh	Z_OFS_USR_7	Z_OFS_USR_6	Z_OFS_USR_5	Z_OFS_USR_4	Z_OFS_USR_3	Z_OFS_USR_2	Z_OFS_USR_1	Z_OFS_USR_0
	CTRL7	3Fh	DRDY_	INT2_ON_INT1	INTERRUPTS	USR_OFF	USR_OFF	USR_OFF_W	HP_REF_MODE	LPASS_ON6D
			PULSED		_ENABLE	_ON_OUT	_ON_WU

1.Read-only register

2.If Low-Power Mode 1 is enabled, this bit is set to 0.

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<![if ! IE]> <![endif]>AN5038 Registers

AN5038

Operating modes

3Operating modes

3.1Power mode

Five sets of operating modes have been designed to offer the customer a broad choice of noise/powerconsumption combinations:

•1 High-Performance Mode: focus on low noise

•4 Low-Power Modes: trade-off between noise and power consumption

Table 3. Accelerometer resolution

High-Performance Mode	Low-Power Mode 4	Low-Power Mode 3	Low-Power Mode 2	Low-Power Mode 1
14-bit	14-bit	14-bit	14-bit	12-bit

These operating modes are selected by writing the MODE[1:0] and LP_MODE[1:0] bits in CTRL1 (20h) shown in the table below.

Table 4. CTRL1 register

b7	b6	b5	b4	b3	b2	b1	b0
ODR3	ODR2	ODR1	ODR0	MODE1	MODE0	LP_MODE1	LP_MODE0

	Table 5. Mode selection
MODE[1:0]	Mode and resolution
00	Low-Power Mode (12/14-bit resolution)
01	High-Performance Mode (14-bit resolution)
10	Single data conversion on-demand mode (12/14-bit resolution)
11	Not allowed

	Table 6. Low-power mode selection
LP_MODE[1:0]	Mode and resolution
00	Low-Power Mode 1 (12-bit resolution)
01	Low-Power Mode 2 (14-bit resolution)
10	Low-Power Mode 3 (14-bit resolution)
11	Low-Power Mode 4 (14-bit resolution)

From each of these five sets, two configurations have been designed:

•Very low-power(low-noise off)

•Low-noise

Writing the LOW_NOISE bit in CTRL6 (25h) selects the desired configuration. The LOW_NOISE bit in CTRL6 (25h) impacts front-end noise and current consumption. Bandwidths and settling time are not impacted.

AN5038 - Rev 5	page 5/51

AN5038

Power mode

Table 7 shows the typical values of power consumption for the different operating modes.

Table 7. Power consumption at 1.8 V [μA]

		High		Low-Power Mode			Low-Power Mode			Low-Power Mode			Low-Power Mode
	Performance				4			3			2			1
Output data rate	LOW_NOISE			LOW_NOISE			LOW_NOISE			LOW_NOISE			LOW_NOISE
	0		1	0		1	0		1	0		1	0		1
1.6 Hz	-		-	0.65		0.7	0.55		0.6	0.45		0.5	0.38		0.4
12.5 Hz	90		120	4		5	2.5		3	1.6		2	1		1.1
25 Hz	90		120	8.5		10	4.5		6	3		3.5	1.5		2
50 Hz	90		120	16		20	9		11	5.5		7	3		3.5
100 Hz	90		120	32		39	17.5		21.5	10.5		13	5		6
200 Hz	90		120	63		77	34.5		42	20.5		25	10		12
400/800/1600 Hz	90		120	-		-	-		-	-		-	-		-

Table 8 and Table 9 show the typical noise values for the different operating modes.

Table 8. High-Performance Mode: noise density [μg/√Hz]

Full scale		LOW_NOISE
	0		1
±2 g	110		90
±4 g	110		100
±8 g	130		120
±16 g	170		160

Note: In High-Performance Mode the noise density is the same for all ODRs.

Table 9. Low-Power Mode: RMS noise [mg(RMS)]

	Low-Power Mode 4		Low-Power Mode 3		Low-Power Mode 2		Low-Power Mode 1
Full scale	0	1	0	1	0	1	0	1
	LOW_NOISE		LOW_NOISE		LOW_NOISE		LOW_NOISE
±2 g	1.6	1.3	2.1	1.8	3.0	2.4	5.5	4.5
±4 g	1.7	1.4	2.3	1.9	3.2	2.7	6.5	5.4
±8 g	1.7	1.5	2.4	2.1	3.3	2.8	6.8	5.8
±16 g	2.0	1.8	2.7	2.4	3.7	3.3	7.7	7.0

Note: In Low-Power Mode the RMS noise is the same for all ODRs.

AN5038 - Rev 5	page 6/51

AN5038

Continuous conversion

3.2Continuous conversion

When bits MODE[1:0] in CTRL1 (20h) are set to Low-Power mode (00b) or High-Performance mode (01b), the device is in continuous conversion and the output data rate can be selected through the ODR[3:0] bits in CTRL1 (20h).

	Table 10. Output data rate selection
ODR[3:0]	Mode and resolution
0000	Power-down
0001	High-Performance 12.5 Hz / Low-Power mode 1.6 Hz
0010	12.5 Hz (independent of power mode)
0011	25 Hz (independent of power mode)
0100	50 Hz (independent of power mode)
0101	100 Hz (independent of power mode)
0110	200 Hz (independent of power mode)
0111	High-Performance 400 Hz / Low-Power mode 200 Hz
1000	High-Performance 800 Hz / Low-Power mode 200 Hz
1001	High-Performance 1600 Hz / Low-Power mode 200 Hz

AN5038 - Rev 5	page 7/51

AN5038

Single data conversion (on-demand mode)

3.3Single data conversion (on-demand mode)

This mode is available only for low-power modes and it is enabled by writing the MODE[1:0] bits to ‘10' in CTRL1 (20h).

In this configuration the device waits for a trigger signal in order to generate new data according to the selected power mode LP_MODE[1:0] bits in CTRL1 (20h), after that the device immediately enters power-down.

The trigger can be:

•A rising edge on the INT2 pin (if SLP_MODE_SEL = ‘0' in register CTRL3 (22h)). In this case the user can detect the end of the conversion using the DRDY bit of the STATUS register (27h) that can also be routed to the INT1 pin by setting the INT1_DRDY bit to 1 in register CTRL4_INT1_PAD_CTRL (23h). Minimum duration of trigger signal high level is 20 ns.

•A write of SLP_MODE_1 to ‘1' in register CTRL3 (22h) (if SLP_MODE_SEL ='1' in register CTRL3 (22h)). In this case, the user can detect the end of the conversion using the DRDY bit/signal as in the previous case, or by checking when the SLP_MODE_1 bit in register CTRL3 (22h) is automatically cleared.

Figure 2. Single data conversion using INT2 as external trigger (SLP_MODE_SEL = 0)

The maximum data rate using single data conversion mode is 200 Hz and the time of conversion depends on the low-power mode selected (refer to the following table).

		Table 11. Low-power mode selection
	Low-power	Typical time of conversion
		(T_on)
	Mode 1	1.20 ms
	Mode 2	1.70 ms
	Mode 3	2.30 ms
	Mode 4	3.55 ms

Note: If the ODR[3:0] bits of the CTRL1 register are set to 0000b, the accelerometer is permanently configured in Power-down mode and no conversion can be triggered. When the single data conversion mode has to be used, the ODR[3:0] bits of the CTRL1 register must be different than 0000b.

Interrupts, embedded features and FIFO are still supported when using single data conversion mode. Also the embedded filters LPF1, LPF2 and HP are available in single data conversion (on-demand mode) with the same bandwidth and settling time of the selected low-power mode (see Section 3.4 Accelerometer bandwidth for details).

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AN5038

Accelerometer bandwidth

3.4Accelerometer bandwidth

The accelerometer sampling chain (Figure 3. Accelerometer filtering chain diagram) is represented by a cascade of a few blocks:

•ADC: Analog-to-digital converter

•Anti-Aliasing Filter: available only in High-Performance Mode (MODE[1:0] = 01) with a cutoff frequency of 400 Hz

•LPF1(2): low-pass filter 1(2)

•HP: high-pass filter

•User offset: configurable values that are subtracted from the sampled data (one for each axis)

Figure 3. Accelerometer filtering chain diagram

As shown in the figure above, data can be generated using three different filter paths:

•only LPF1 (green path) : in order to select this path set BW_FILT[1:0] = 00 and FDS = 0. Additional details in Table 12. Low-pass filter 1 bandwidth.

•LPF1 + LPF2 (purple path) : in order to select this path set BW_FILT[1:0] to a value different from 00 and FDS = 0. Additional details in Table 13. Bandwidth: low-pass path.

•LPF1 + HP (blue path): these outputs are available by setting FDS = 1. Additional details in Table 14. Bandwidth: high-pass path.

AN5038 - Rev 5	page 9/51

AN5038

Accelerometer bandwidth

Table 12. Low-pass filter 1 bandwidth

		BW_FILT[1:0] = 00
Mode	ODR selection
		Samples to discard(1)		Cutoff [Hz]
		Settling @95%
Low-Power Mode 4	@ each ODR	0		180
Low-Power Mode 3	@ each ODR	0		360
Low-Power Mode 2	@ each ODR	0		720
Low-Power Mode 1	@ each ODR	0		3200
High-Performance	@12.5 Hz	0		ODR/2
High-Performance	@25 Hz	0		ODR/2
High-Performance	@50 Hz	0		ODR/2
High-Performance	@100 Hz	1		ODR/2
High-Performance	@200 Hz	1		ODR/2
High-Performance	@400 Hz	1		ODR/2
High-Performance	@800 Hz	1		ODR/2
High-Performance	@1600 Hz	2		400

1.The starting condition of ODR[3:0], MODE[1:0], LP_MODE[1:0] and BW_FILT[1:0] do not impact these values. The turn-on time (first sample available starting from power-down condition) is 1 / ODR.

Table 13. Bandwidth: low-pass path

			BW_FILT[1:0] = 01		BW_FILT[1:0] = 10		BW_FILT[1:0] = 11
	Mode	ODR selection	Samples to		Samples to	Cutoff	Samples to	Cutoff
			discard(1)	Cutoff [Hz]	discard(1)		discard(1)
						[Hz]		[Hz]
			Settling @95%		Settling @95%		Settling @95%
	LP	@ each ODR	1	ODR/4	5	ODR/10	11	ODR/20
	Mode 4
	LP	@ each ODR	1	ODR/4	5	ODR/10	11	ODR/20
	Mode 3
	LP	@ each ODR	1	ODR/4	5	ODR/10	11	ODR/20
	Mode 2
	LP	@ each ODR	1	ODR/4	5	ODR/10	11	ODR/20
	Mode 1
	HP	@12.5 Hz	1	ODR/4	5	ODR/10	11	ODR/20
	HP	@25 Hz	1	ODR/4	5	ODR/10	11	ODR/20
	HP	@50 Hz	1	ODR/4	5	ODR/10	11	ODR/20
	HP	@100 Hz	1	ODR/4	5	ODR/10	11	ODR/20
	HP	@200 Hz	2	ODR/4	5	ODR/10	11	ODR/20
	HP	@400 Hz	2	ODR/4	5	ODR/10	11	ODR/20
	HP	@800 Hz	2	ODR/4	5	ODR/10	11	ODR/20
	HP	@1600 Hz	3	ODR/4	6	ODR/10	12	ODR/20

1. The starting condition of ODR[3:0], MODE[1:0], LP_MODE[1:0] and BW_FILT[1:0] do not impact these values.

AN5038 - Rev 5	page 10/51

AN5038

Accelerometer bandwidth

Table 14. Bandwidth: high-pass path

			BW_FILT[1:0] = 01 / 00		BW_FILT[1:0] = 10			BW_FILT[1:0] = 11
	Mode	ODR selection	Samples to		Samples to discard	(1)	Cutoff	Samples to discard	(1)	Cutoff
			discard(1)	Cutoff [Hz]
			Settling @95%		Settling @95%		[Hz]	Settling @95%		[Hz]
	LP	@ each ODR	1	ODR/4	5		ODR/10	11		ODR/20
	Mode 4
	LP	@ each ODR	1	ODR/4	5		ODR/10	11		ODR/20
	Mode 3
	LP	@ each ODR	1	ODR/4	5		ODR/10	11		ODR/20
	Mode 2
	LP	@ each ODR	1	ODR/4	5		ODR/10	11		ODR/20
	Mode 1
	HP	@12.5 Hz	1	ODR/4	5		ODR/10	11		ODR/20
	HP	@25 Hz	1	ODR/4	5		ODR/10	11		ODR/20
	HP	@50 Hz	1	ODR/4	5		ODR/10	11		ODR/20
	HP	@100 Hz	1	ODR/4	5		ODR/10	11		ODR/20
	HP	@200 Hz	2	ODR/4	5		ODR/10	11		ODR/20
	HP	@400 Hz	2	ODR/4	5		ODR/10	11		ODR/20
	HP	@800 Hz	2	ODR/4	5		ODR/10	11		ODR/20
	HP	@1600 Hz	3	ODR/4	6		ODR/10	12		ODR/20

1. The starting condition of ODR[3:0], MODE[1:0], LP_MODE[1:0] and BW_FILT[1:0] do not impact these values.

Setting USR_OFF_ON_OUT = 1 in CTRL7 does not change the bandwidth of the system. In this configuration, the values written in registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR are subtracted from the respective axis. The offset values are signed values (two's complement).

The weight of the bits in registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR is defined through the USR_OFF_W bit in CTRL7.

AN5038 - Rev 5	page 11/51

AN5038

High-pass filter configuration

3.5High-pass filter configuration

The LIS2DW12 provides an embedded high-pass filtering capability to easily delete the DC component of the measured acceleration. As shown in Figure 3. Accelerometer filtering chain diagram, through the FDS bit in register CTRL6 the user can route the filter outputs to the output registers.

It is also possible to independently apply the filter to the embedded function data (Figure 6. Embedded functions in Section 5 Interrupt generation and embedded functions). This means that it is possible to get filtered data while the interrupt generation works on unfiltered data.

The high-pass filter can be configured in reference mode by setting the HP_REF_MODE bit in the CTRL7 register to 1. In this configuration the output data is calculated as the difference between the measured acceleration and the output values captured when reference mode was enabled. In this way only the difference is applied without any filtering.

As an example, this feature can be combined with the wake-up functionality described in Section 5.4 in order to detect when the device is displaced with respect to a specific orientation, i.e. the orientation of the device when the HP_REF_MODE bit was set to 1. When the output acceleration exceeds the wake-up threshold defined by the WK_THS[5:0] bits in the WAKE_UP_THS register for a duration longer than the one defined by the

WAKE_DUR[1:0] bits in the WAKE_UP_DUR register, an interrupt is generated. If the device is moved back to the original reference orientation, the interrupt is deactivated.

Figure 4. High-pass filter in normal and reference mode

AN5038 - Rev 5	page 12/51

AN5038

Reading output data

4Reading output data

4.1Startup sequence

Once the device is powered up, it automatically downloads the calibration coefficients from the embedded non-volatile memory to the internal registers. When the boot procedure is completed, i.e. after approximately

20 milliseconds, the accelerometer automatically enters power-down. The default status of the pins with both VDD and VDDIO "on" is indicated in Table 1. Internal pin status.

Note: VDD cannot be lower than VDDIO. VDD = 0 V and VDDIO "on" is allowed: when this power supply configuration is applied, an internal pull-up is applied also to the SDA and SCL pins (the other pins maintain the default status indicated in Table 1).

To turn on the accelerometer and gather acceleration data, it is necessary to select one of the operating modes through the CTRL1 register.

Refer to Section 3 Operating modes for a detailed description of data generation.

4.2Using the status register

The device is provided with a STATUS register which can be polled to check when a new set of data is available. The DRDY bit is set to 1 when a new set of data is available from the accelerometer output.

The read operations should be performed as follows:

1.Read STATUS

2.If DRDY = 0, then go to 1

3.Read OUT_X_L

4.Read OUT_X_H

5.Read OUT_Y_L

6.Read OUT_Y_H

7.Read OUT_Z_L

8.Read OUT_Z_H

9.Data processing

10.Go to 1

4.3Using the data-ready signal

The device can be configured to have one hardware signal to determine when a new set of measurement data is available to be read.

The data-ready signal is derived from the DRDY bit of the STATUS register. The signal can be driven to the INT1 pin by setting the INT1_DRDY bit of the CTRL4_INT1_PAD_CTRL register to 1 and to the INT2 pin by setting the INT2_DRDY bit of the CTRL5_INT2_PAD_CTRL register to 1.

The data-ready signal rises to 1 when a new set of data has been measured and is available to be read. In DRDY latched mode (DRDY_PULSED bit = 0 in CTRL7 register), which is the default condition, the signal gets reset when the higher part of one of the channels has been read (29h, 2Bh, 2Dh). In DRDY pulsed mode (DRDY_PULSED = 1) the pulse duration is 75 μs (typical) if the accelerometer is configured in High-Performance mode, otherwise it can vary between 105 μs and 175 μs. Pulsed mode is not applied to the DRDY bit which is always latched.

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Using the block data update (BDU) feature

Figure 5. Data-ready signal

4.4Using the block data update (BDU) feature

If reading the accelerometer data is particularly slow and cannot be synchronized (or it is not required) with either the DRDY event bit in the STATUS register or with the DRDY signal driven to the INT1/INT2 pins, it is strongly recommended to set the BDU (block data update) bit to 1 in the CTRL2 (21h) register.

This feature avoids reading values (most significant and least significant parts of output data) related to different samples. In particular, when the BDU is activated, the data registers related to each channel always contain the most recent output data produced by the device, but, in case the read of a given pair (i.e. OUT_X_H and OUT_X_L, OUT_Y_H and OUT_Y_L, OUT_Z_H and OUT_Z_L) is initiated, the refresh for that pair is blocked until both MSB and LSB parts of the data are read.

Note: BDU only guarantees that the LSB part and MSB part of one data channel have been sampled at the same moment. For example, if the reading speed is too slow, X and Y can be read at T1 and Z sampled at T2.

4.5Understanding output data

The measured acceleration data are sent to the OUT_X_H, OUT_X_L, OUT_Y_H, OUT_Y_L, OUT_Z_H, and OUT_Z_L registers. These registers contain, respectively, the most significant part and the least significant part of the acceleration signals acting on the X, Y, and Z axes.

The complete output data for the X, Y, Z channels is given by the concatenation OUT_X_H & OUT_X_L, OUT_Y_H & OUT_Y_L , OUT_Z_H & OUT_Z_L.

Acceleration data is represented as 16-bit numbers, left-aligned and encoded in two’s complement. These values (LSB) have different resolution according to the selected operating mode.

After calculating the LSB, it must be multiplied by the proper sensitivity parameter to obtain the corresponding value in mg.

Table 15. Sensitivity

Full Scale		Sensitivity [mg/LSB]
	12-bit format(1)		14-bit format
±2 g	0.976		0.244
±4 g	1.952		0.488
±8 g	3.904		0.976
±16 g	7.808		1.952

1. Only Low-Power Mode 1

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Understanding output data

4.5.1Example of output data

Below is a simple example of how to use the LSB data and transform it into mg.

The values are given under the hypothesis of ideal device calibration (i.e., no offset, no gain error, etc.). Get raw data from the sensor (High-Performance mode, ±2 g):

OUT_X_L: 60h

OUT_X_H: FDh

OUT_Y_L: 78h

OUT_Y_H: 00h

OUT_Z_L: FCh

OUT_Z_H: 42h

Do register concatenation:

OUT_X_H & OUT_X_L: FD60h

OUT_Y_H & OUT_Y_L: 0078h

OUT_Z_H & OUT_Z_L: 42FCh

Apply sensitivity (e.g., 14-bit resolution, 0.244 at full scale ±2 g):

X:-672 / 4 * 0.244 = -41 mg

Y:+120 / 4 * 0.244 = +7 mg

Z:+17148 / 4 * 0.244 = +1046 mg

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Interrupt generation and embedded functions

5Interrupt generation and embedded functions

Figure 6. Embedded functions

In order to generate an interrupt, the LIS2DW12 device has to be set in an active operating mode (not in power-down) because generation of the interrupt is based on accelerometer data.

The interrupt generator can be configured to detect:

•Free-fall;

•Wake-up;

•6D/4D orientation detection;

•Single-tap and double-tap sensing;

•Activity/Inactivity detection.

All these interrupt signals, together with the FIFO interrupt signals and sensor data-ready, can be driven to the INT1 and/or INT2 interrupt pins or checked by reading the dedicated source register bits.

The H_LACTIVE bit of the CTRL3 register must be used to select the polarity of the interrupt pins. If this bit is set to 0 (default value), the interrupt pins are active high and they change from low to high level when the

related interrupt condition is verified. Otherwise, if the H_LACTIVE bit is set to 1 (active low), the interrupt pins are normally at high level and they change from high to low when the interrupt condition is reached.

The PP_OD bit of CTRL3 allows changing the behavior of the interrupt pins also when the DRDY signal is routed to them from push-pull to open drain. If the PP_OD bit is set to 0, the interrupt pins are in push-pull configuration (low-impedance output for both high and low level). When the PP_OD bit is set to 1, only the interrupt active state is a low-impedance output.

The LIR bit of CTRL3 allows applying the latched mode to the interrupt signals (not affecting the DRDY signal). When the LIR bit is set to 1, once the interrupt pin is asserted, it must be reset by reading the related interrupt source register. If the LIR bit is set to 0, the interrupt signal is automatically reset when the interrupt condition is no longer verified or after a certain amount of time in function of the type of interrupt.

Note: If latched mode is enabled (LIR = 1), it is not recommended to continuously poll ALL_INT_SRC or the dedicated source registers because by reading them the embedded functions are internally reset; a synchronous (with interrupt event) read of the source registers is recommended in this case.

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