ST LIS2DM User Manual

Download

ultra low-power high performance 3-axis “femto” accelerometer

LGA-14

(2.0x2.0x1mm)

Features

■ Wide supply voltage, 1.71 V to 3.6 V

■ Independent IOs supply (1.8 V) and supply

voltage compatible

■ Ultra low-power mode consumption down to 2

µA

■ ±2g/±4g/±8g/±16g dynamically selectable full

scale

■ I

C/SPI digital output interface

■ 8-bit data output

■ 2 independent programmable interrupt

generators for free-fall and motion detection

■ 6D/4D orientation detection

■ “Sleep to wake” and “Return to sleep” function

■ Free-fall detection

■ Motion detection

■ Embedded temperature sensor

■ Embedded FIFO

■ ECOPACK

Applications

RoHS and “Green” compliant

LIS2DM

MEMS digital output motion sensor:

The LIS2DM has dynamically user selectable full scales of ±2g/±4g/±8g/±16g and it is capable of measuring accelerations with output data rates from 1 Hz to 5.3 kHz.

The self-test capability allows the user to check the functioning of the sensor in the final application.

The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself.

The LIS2DM is available in a small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

■ Motion activated functions

■ Display orientation

■ Shake control

■ Pedometer

■ Gaming and virtual reality input devices

■ Impact recognition and logging

Description

Table 1. Device summary

Order

codes

LIS2DM -40 to +85 LGA-14 Tray

LIS2DMTR -40 to +85 LGA-14

Temperature

range [° C]

Package Packaging

Tape and

reel

The LIS2DM is an ultra low-power high performance 3-axis linear accelerometer belonging to the “femto” family, with digital I

C/SPI

serial interface standard output.

November 2011 Doc ID 022536 Rev 1 1/47

www.st.com

Contents LIS2DM

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.2 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6 Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.3 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.4 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.5 6D / 4D orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.6 “Sleep to wake” and “Return to sleep” . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.7 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.9 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.10 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/47 Doc ID 022536 Rev 1

LIS2DM Contents

4.1.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.4 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.5 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.3 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1 STATUS_AUX (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2 OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh) . . . . . . . . . . . . . . . . . . . . . . 30

7.3 INT_COUNTER (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 TEMP_CFG_REG (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.6 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.7 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.8 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.9 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.10 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.11 CTRL_REG6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.12 REFERENCE/DATACAPTURE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.13 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.14 FIFO_READ_START (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.15 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.16 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.17 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.18 FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.19 FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 022536 Rev 1 3/47

Contents LIS2DM

7.20 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.21 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.22 INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.23 INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.24 INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.25 INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.26 INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.27 INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.28 CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.29 CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.30 CLICK_THS (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.31 TIME_LIMIT (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.32 TIME_LATENCY (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.33 TIME WINDOW(3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.34 Act_THS(3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.35 Act_DUR (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4/47 Doc ID 022536 Rev 1

LIS2DM List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9. Normal mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 10. Current consumption vs. ODR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16. Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 23

Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23

Table 18. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 19. STATUS_REG_AUX register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20. STATUS_REG_AUX description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. INT_COUNTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 23. TEMP_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 24. TEMP_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 25. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 26. CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 27. Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 28. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 29. CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 30. High pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 31. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 32. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 33. CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 34. CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 35. Self test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 36. CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 37. CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 38. CTRL_REG6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 39. CTRL_REG6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 40. REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 41. REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 42. STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 43. STATUS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 44. FIFO_CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 45. FIFO_CTRL_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 46. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 47. FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 48. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 022536 Rev 1 5/47

List of tables LIS2DM

Table 49. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 50. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 51. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 52. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 53. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 54. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 55. INT1_DURATION description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 56. INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 57. INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 58. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 59. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 60. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 61. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 62. INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 63. INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 64. INT2_DURATION description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 65. CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 66. CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 67. CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 68. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 69. CLICK_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 70. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 71. TIME_LIMIT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 72. TIME_LIMIT description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 73. TIME_LATENCY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 74. TIME_LATENCY description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 75. TIME_WINDOW register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 76. TIME_WINDOW description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 77. TIME_WINDOW register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 78. TIME_WINDOW description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 79. Act_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 80. Act_DUR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 81. LGA-14 2x2x1 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 82. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6/47 Doc ID 022536 Rev 1

LIS2DM List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. LIS2DM electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. Multiple bytes SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. Multiple bytes SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12. LGA-14 2x2x1 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Doc ID 022536 Rev 1 7/47

Block diagram and pin description LIS2DM

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram

SELF TEST

Temperature

Sensor

1.2 Pin description

Figure 2. Pin connection

X+

Y+

Z+

Z-

Y-

X-

MUX

CHARGE AMPLIFIER

TRIMMING

CIRCUITS

A/D

CONVERTER

CLOCK

CONTROL

LOGIC

32 Level

FIFO

Res

SCL/SPC

I2C

SDA/SDO/SDI

SPI

SDO/SA0

CONTROL LOGIC

INTERRUPT GEN.

Res

Pin 1 indicator

INT 1

INT 2

AM10218V1

12 14

GND

Vdd

L/SPC

SDA/SDI/SDO

SDO/SA0

(TOP VIEW)

DIRECTION OF THE DETECTABLE ACCELERATIONS

8/47 Doc ID 022536 Rev 1

INT2

INT1

Vdd_IO

(BOTTOM VIEW)

AM10218V1

LIS2DM Block diagram and pin description

Table 2. Pin description

Pin# Name Function

SCL SPC

SDA

SDI

SDO

SA0

4CS

5 INT2 Interrupt pin 2

6 INT1 Interrupt pin 1

7 Vdd_IO Power supply for I/O pins

8 Vdd Power supply

9 GND 0 V supply

10 Res Connect to GND

11 Res Connect to GND

C serial clock (SCL)

SPI serial port clock (SPC)

C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO)

SPI serial data output (SDO) I2C less significant bit of the device address (SA0)

SPI enable

C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I

C disabled)

12-14 Res Connect to GND

Doc ID 022536 Rev 1 9/47

Mechanical and electrical specifications LIS2DM

2 Mechanical and electrical specifications

2.1 Mechanical characteristics

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

Table 3. Mechanical characteristics

Symbol Parameter Test conditions Min. Typ.

FS bit set to 00 ±2.0

FS bit set to 01 ±4.0

FS Measurement range

So Sensitivity

TCSo

Ty O ff

TCOff

Vst

To p

1. Typical specifications are not guaranteed.

2. Verified by wafer level test and measurement of initial offset and sensitivity.

3. Typical zero-g level offset value after MSL3 preconditioning.

4. Offset can be eliminated by enabling the built-in high pass filter.

5. The sign of “Self-test output change” is defined by CTRL_REG4 ST bit, for all axes.

“Self-test output change” is defined as the absolute value of:

6. OUTPUT[LSb]

7. After enabling self-test, the correct data is obtained after two samples.

Sensitivity change vs. temperature

Ty p i c a l ze ro -

g level

offset accuracy

Zero-

g level change

vs. temperature

Self-test output change

Operating temperature range

(Self test enabled)

(2)

FS bit set to 10 ±8.0

FS bit set to 11 ±16.0

FS bit set to 00; Low power mode

FS bit set to 01; Low power mode

FS bit set to 10; Low power mode

FS bit set to 11; Low power mode

FS bit set to 00 0.01 %/°C

(3),(4)

FS bit set to 00 ±100 mg

Max. delta from 25 °C ±1 m

FS bit set to 00 X axis; 6 90 LSb

(5),(6),(7)

FS bit set to 00 Y axis; 6 90 LSb

FS bit set to 00 Z axis; 6 90 LSb

- OUTPUT[LSb]

(Self test disabled)

. 1LSb=16mg at 8-bit representation, ±2 g full-scale.

(a)

(1)

192

-40 +85 °C

Max. Unit

mg/digit

g/°C

a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71V to 3.6 V.

10/47 Doc ID 022536 Rev 1

LIS2DM Mechanical and electrical specifications

2.2 Temperature sensor characteristics

@ Vdd =2.5 V, T=25 °C unless otherwise noted

Table 4. Temperature sensor characteristics

Symbol Parameter Test condition Min. Typ.

(b)

(1)

Max. Unit

TSDr

TODR Temperature refresh rate ODR

Temperature sensor output change vs. temperature

1digit/°C

(3)

Top Operating temperature range -40 +85 °C

1. Typical specifications are not guaranteed.

2. 8-bit resolution.

3. Refer to Table 27.

2.3 Electrical characteristics

@ Vdd =2.5 V, T=25 °C unless otherwise noted

Table 5. Electrical characteristics

Symbol Parameter Test conditions Min. Typ.

Vdd Supply voltage 1.71 2.5 3.6 V

Vdd_IO I/O pins supply voltage

Idd

IddPdn

Current consumption in Normal mode

Current consumption in power down mode

VIH Digital high level input voltage 0.8*Vdd_IO V

(2)

50 Hz ODR 6 µA

(c)

(1)

Max. Unit

1.71 Vdd+0.1 V

0.5 µA

(2)

VIL Digital low level input voltage 0.2*Vdd_IO V

VOH High level output voltage 0.9*Vdd_IO V

VOL Low level output voltage 0.1*Vdd_IO V

Top Operating temperature range -40 +85

1. Typical specification are not guaranteed.

2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.

b. The product is factory calibrated at 2.5 V. Temperature sensor operation is guaranteed in the range 2 V - 3.6 V.

c. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

Doc ID 022536 Rev 1 11/47

°C

Mechanical and electrical specifications LIS2DM

SPC

SDI

SDO

su(CS)

v(SO)

h(SO)

h(SI)

su(SI)

h(CS)

dis(SO)

c(SPC)

MSB IN

MSB OUT

LSB OUT

LSB IN

(3)

2.4 Communication interface characteristics

2.4.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 6. SPI slave timing values

(1)

Val u e

Symbol Parameter

Min. Max.

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz

tsu(CS) CS setup time 5

th(CS) CS hold time 10

tsu(SI) SDI input setup time 5

th(SI) SDI input hold time 15

tv(SO) SDO valid output time 50

th(SO) SDO output hold time 5

tdis(SO) SDO output disable time 50

Unit

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

(d)

Figure 3. SPI slave timing diagram

3.When no communication is ongoing, data on SDO is driven by internal pull-up resistors.

12/47 Doc ID 022536 Rev 1

d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

LIS2DM Mechanical and electrical specifications

SPC

SDI

SDO

su(CS)

v(SO)

h(SO)

h(SI)

su(SI)

h(CS)

dis(SO)

c(SPC)

MSB IN

MSB OUT

LSB OUT

LSB IN

(3)

2.4.2 I2C - Inter IC control interface

Subject to general operating conditions for Vdd and top.

Table 7. I2C slave timing values

Symbol Parameter

I2C standard mode

(1)

I2C fast mode

Min. Max. Min. Max.

(1)

Unit

(SCL)

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA) tr(SCL)

f(SDA) tf(SCL)

h(ST)

su(SR)

su(SP)

w(SP:SR)

SCL clock frequency 0 100 0 400 kHz

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100 ns

SDA data hold time 0 3.45 0.01 0.9 µs

SDA and SCL rise time 1000

SDA and SCL fall time 300

START condition hold time 4 0.6

Repeated START condition setup time

4.7 0.6

STOP condition setup time 4 0.6

Bus free time between STOP and START condition

4.7 1.3

1. Data based on standard I2C protocol requirement, not tested in production.

2. Cb = total capacitance of one bus line, in pF.

Figure 4. I

C Slave timing diagram

(e)

20 + 0.1C

µs

(2)

300

µs

e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

Doc ID 022536 Rev 1 13/47

Mechanical and electrical specifications LIS2DM

This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part.

This is an ESD sensitive device, improper handling can cause permanent damage to the part.

2.5 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 8. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 4.8 V

Vdd_IO I/O pins supply voltage -0.3 to 4.8 V

Vin

POW

UNP

STG

ESD Electrostatic discharge protection 2 (HBM) kV

Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)

Acceleration (any axis, powered, Vdd = 2.5 V)

Acceleration (any axis, unpowered)

Operating temperature range -40 to +85 °C

Storage temperature range -40 to +125 °C

-0.3 to Vdd_IO +0.3 V

3000 g for 0.5 ms

10000 g for 0.1 ms

3000 g for 0.5 ms

10000 g for 0.1 ms

Note: Supply voltage on any pin should never exceed 4.8 V

14/47 Doc ID 022536 Rev 1

LIS2DM Mechanical and electrical specifications

2.6 Terminology and functionality

Terminology

2.6.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The sensitivity tolerance describes the range of Sensitivities of a large population of sensors.

2.6.2 Zero-g level

Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in steady-state on a horizontal surface measures 0 g in the X axis and 0 g in the Y axis whereas the Z axis measures 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see Table 3: Mechanical characteristics. The Zero-g level tolerance (TyOff) describes the standard deviation of the range of Zero-g levels of a population of sensors.

Functionality

2.6.3 Normal mode

The LIS2DM provides a single operating mode called normal mode.

Ta bl e 9 summarizes operating mode performances.

Table 9. Normal mode features

Operating mode

Normal mode ODR/2 1 16

[Hz]

Turn-on time

[ms]

So @ ±2g

[mg/digit]

Doc ID 022536 Rev 1 15/47

Mechanical and electrical specifications LIS2DM

Table 10. Current consumption vs. ODR

Operating mode

10 3

25 4

50 6

100 10

200 18

400 36

1620 100

5376 185

2.6.4 Self-test

Self-test allows the checking of the sensor functionality without moving it. When the self-test is enabled an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Ta bl e 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications.

[Hz]

Normal mode

[µA]

2.6.5 6D / 4D orientation detection

The LIS2DM includes 6D / 4D orientation detection. In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration the Z axis position detection is disabled.

2.6.6 “Sleep to wake” and “Return to sleep”

The LIS2DM can be programmed to automatically switch to low power mode upon recognition of a determined event. Once the event condition is over, the device returns to the preset normal or high resolution mode.

To enable this function the desired threshold value must be stored in the Act_THS(3Eh) registers while the duration value is written in the Act_DUR(3Fh) registers.

When the acceleration module becomes lower than the threshold value, the device automatically switches to low power mode (10Hz ODR). During this condition, ODRx bits and the LPen bit in CTRL_REG1 (20h) are not considered.

As soon as the acceleration goes back over the threshold, the systems restore the operating mode and ODRs for the CTRL_REG1 (20h) and CTRL_REG3 (22h) settings.

16/47 Doc ID 022536 Rev 1

LIS2DM Mechanical and electrical specifications

2.7 Sensing element

A proprietary process is used to create a surface micro-machined accelerometer. The technology allows the transfer of suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation.

When an acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.

At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied the maximum variation of the capacitive load is in the fF range.

2.8 IC interface

The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user through an analog-to-digital converter.

The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller.

C/SPI interface, therefore making the

The LIS2DM features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device.

The LIS2DM may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal according to a programmed acceleration event along the enabled axes. Both free-fall and wake-up can be available simultaneously on two different pins.

Doc ID 022536 Rev 1 17/47

Mechanical and electrical specifications LIS2DM

2.9 Factory calibration

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).

The trimming values are stored inside the device in a non-volatile memory. Anytime the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows use of the device without further calibration.

2.10 FIFO

The LIS2DM contains a 10-bit, 32-level FIFO. Buffered output allows 4 operation modes: FIFO, stream, trigger and FIFO bypass. Where FIFO bypass mode is activated, FIFO is not operating and remains empty. In FIFO mode, data from acceleration detection on X, Y, and Z-axes measurements are stored in FIFO.

2.11 Temperature sensor

The LIS2DM is supplied with an internal temperature sensor. Temperature data can be enabled by setting the TEMP_EN bit of the TEMP_CFG_REG register to 1.

To retrieve the temperature sensor data, the TDB temperature dummy bit on CTRL_REG4

(23h) must be set to ‘1’.

Both OUT_TEMP_H and OUT_TEMP_L registers must be read.

Temperature data is stored in OUT_TEMP_H as 2’s complement data in 8-bit format left justified.

18/47 Doc ID 022536 Rev 1

LIS2DM Application hints

3 Application hints

Figure 5. LIS2DM electrical connection

Vdd_IO

GND

Pin 1 indicator

1214

SCL/SPC

SDA/SDI/SDO

SDO/SA0

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

INT2

INT1

Vdd_IO

GND

Vdd

10µF

100nF

GND

AM10220V1

The device core is supplied through the Vdd line while the I/O pads are supplied through the Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should be placed as near as possible to pin 8 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to obtain proper behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.

The functionality of the device and the measured acceleration data is selectable and accessible through the I

C or SPI interfaces. When using the I2C, CS must be tied high.

The functions, the threshold, and the timing of the two interrupt pins (INT1 and INT2) can be completely programmed by the user through the I

3.1 Soldering information

The LGA package is compliant with the ECOPACK®, RoHS, and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com

Doc ID 022536 Rev 1 19/47

C/SPI interface.

Digital main blocks LIS2DM

4 Digital main blocks

4.1 FIFO

The LIS2DM embeds a 32-slot data FIFO for each of the three output channels, X, Y and Z. This allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to four different modes: bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits in FIFO_CTRL_REG (2E). Programmable Watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on the INT1/2 pin (configuration through FIFO_CFG_REG).

4.1.1 Bypass mode

In bypass mode, the FIFO is not operational and for this reason it remains empty. As described in the next figure, for each channel only the first address is used. The remaining FIFO slots are empty.

4.1.2 FIFO mode

In FIFO mode, data from X, Y and Z channels are stored in the FIFO. A Watermark interrupt can be enabled (FIFO_WTMK_EN bit in FIFO_CTRL_REG (2E) in order to be raised when the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG (2E). The FIFO continues filling until it is full (32 slots of data for X, Y and Z). When full, the FIFO stops collecting data from the input channels.

4.1.3 Stream mode

In Stream mode, data from X, Y and Z measurements are stored in the FIFO. A Watermark interrupt can be enabled and set as in FIFO mode.The FIFO continues filling until it’s full (32 slots of data for X, Y and Z). When full, the FIFO discards the older data as the new arrive.

4.1.4 Stream-to-FIFO mode

In Stream-to_FIFO mode, data from X, Y and Z measurements are stored in the FIFO. A Watermark interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG) in order to be raised when the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG. The FIFO continues filling until it’s full (32 slots of 10-bit for X, Y and Z). When full, the FIFO discards the older data as the new arrive. Once a trigger event occurs, the FIFO starts operating in FIFO mode.

4.1.5 Retrieve data from FIFO

FIFO data is read through OUT_X (Addr reg 29h), OUT_Y (Addr reg 2Bh), and OUT_Z (Addr reg 2Dh). When the FIFO is in Stream, Trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst operations can be used. The reading address is automatically updated by the device and it rolls back to 0x28 when register 0x2D is reached. In order to read all FIFO levels in a multiple byte reading,192 bytes (6 output registers by 32 levels) must be read.

20/47 Doc ID 022536 Rev 1

LIS2DM Digital interfaces

5 Digital interfaces

The registers embedded in the LIS2DM may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I CS line must be tied high (i.e. connected to Vdd_IO).

Table 11. Serial interface pin description

Pin name Pin description

SPI enable

SCL

SPC

SDA

SDI

SDO

I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled)

C serial clock (SCL)

SPI serial port clock (SPC)

C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO)

C interface, the

SA0

SDO

I2C less significant bit of the device address (SA0) SPI serial data output (SDO)

5.1 I2C serial interface

The LIS2DM I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back.

The relevant I

Table 12. Serial interface pin description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master

There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bi-directional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both lines are high.

The I

C interface is compliant with fast mode (400 kHz) I2C standards as well as with

Normal mode.

C terminology is given in Tab l e 1 2 below.

Term Description

The device which initiates a transfer, generates clock signals and terminates a transfer

Slave The device addressed by the master

Doc ID 022536 Rev 1 21/47

Digital interfaces LIS2DM

5.1.1 I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The slave address (SAD) associated to the LIS2DM is 001100xb. The SDO/SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to the voltage supply, LSb is ‘1’ (address 0011001b) or else, if the SA0 pad is connected to ground, the LSb value is ‘0’ (address 0011000b). This solution permits the connecting and addressing of two different accelerometers to the same I

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I

C embedded in the LIS2DM behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSb represent the actual register address while the MSb enables address auto increment. If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to allow multiple data read/write.

C lines.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write), the master transmits to the slave with direction unchanged. Tab le 1 3 explains how the SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 13. SAD+read/write patterns

Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W

Read 001100 0 1 00110001 (31h)

Write 001100 0 0 00110000 (30h)

Read 001100 1 1 00110011 (33h)

Write 001100 1 0 00110010 (32h)

Table 14. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP

Slave SAK SAK SAK

22/47 Doc ID 022536 Rev 1

LIS2DM Digital interfaces

Table 15. Transfer when master is writing multiple bytes to slave:

Master ST SAD + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

Table 16. Transfer when master is receiving (reading) one byte of data from slave:

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read.

In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge.

5.2 SPI bus interface

The LIS2DM SPI is a bus slave. The SPI allows the writing and reading of the device registers.

The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

Doc ID 022536 Rev 1 23/47

Digital interfaces LIS2DM

Figure 6. Read and write protocol

SPC

SDI

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AM10129V1

SDO

AD5 AD4 AD3 AD2 AD1 AD0

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and returns high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.

Both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in the case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS.

bit 0: RW

bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)

from the device is read. In the latter case, the chip drives SDO at the start of bit 8.

bit 1: MS

bit. When 0, the address remains unchanged in multiple read/write commands.

When 1, the address is auto incremented in multiple read/write commands.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods are added. When the MS bit is ‘0’, the address used to read/write data remains the same for every block. When the MS

bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

24/47 Doc ID 022536 Rev 1

LIS2DM Digital interfaces

SPC

SDI

SDO

DO7 DO6 DO5 DO4 DO3DO2 DO1DO0

AD5 AD4 AD3 AD2 AD1 AD0

AM10130V1

5.2.1 SPI read

Figure 7. SPI read protocol

The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed adding blocks of 8 clock pulses at the previous one.

bit 0: READ bit. The value is 1.

bit 1: MS

bit. When 0, do not increment the address, when 1, increment the address in

multiple reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

bit 16-... : data DO(...-8). Further data in multiple byte reading.

Figure 8. Multiple bytes SPI read protocol (2-byte example)

C S

SPC

SDI

AD5 AD4AD3 AD2 AD1 AD0

M S

SDO

DO 7 DO 6 DO5 DO 4 DO3 DO2 DO 1DO 0

DO15 DO 14 DO 13 DO12 DO 11 DO 10 D O9 DO8

AM10131V1

Doc ID 022536 Rev 1 25/47

Digital interfaces LIS2DM

5.2.2 SPI write

Figure 9. SPI write protocol

SPC

SDI

AD5 AD 4 AD 3 AD2 AD1 AD0MS

The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed adding blocks of 8 clock pulses to the previous one.

bit 0: WRITE bit. The value is 0.

DI7 DI6 DI5 DI4 DI3 DI2 DI 1 DI 0

AM10132V1

bit 1: MS

bit. When 0, do not increment the address, when 1, increment the address in

multiple writing.

bit 2 -7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writing.

Figure 10. Multiple bytes SPI write protocol (2-byte example)

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD 0

5.2.3 SPI read in 3-wires mode

3-wire mode is entered by setting bit SIM (SPI serial interface mode selection) to ‘1’ in CTRL_REG4.

DI7 D I6 DI 5 D I4 DI 3 DI2 DI 1 DI0 DI 15 D I1 4 DI 13 DI12 DI11 DI 10 DI 9 DI 8

AM10133V1

26/47 Doc ID 022536 Rev 1

LIS2DM Digital interfaces

Figure 11. SPI read protocol in 3-wire mode

SPC

SDI/O

AD5 AD4 AD3 AD2 AD1 AD0MS

The SPI read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.

DO7 DO6 DO5 DO4 DO3 DO 2 DO1 DO 0

AM10134V1

bit 1: MS

bit. When 0, do not increment the address, when 1, increment the address in

multiple reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

Multiple read command is also available in 3-wire mode.

Doc ID 022536 Rev 1 27/47

6 Register mapping

Ta bl e 1 8 below provides a listing of the 8-bit registers embedded in the device and the

related addresses:

Table 18. Register address map

Name Type

Hex Binary

Reserved 00 - 06 Reserved

STATUS_REG_AUX r 07 000 0111

Reserved r 08-0B Reserved

OUT_TEMP_L r 0C 000 1100 Output

OUT_TEMP_H r 0D 000 1101 Output

INT_COUNTER_REG r 0E 000 1110

WHO_AM_I r 0F 000 1111 00110011 Dummy register

Reserved 10 - 1E Reserved

TEMP_CFG_REG rw 1F 001 1111

CTRL_REG1 rw 20 010 0000 00000111

Default Comment

CTRL_REG2 rw 21 010 0001 00000000

CTRL_REG3 rw 22 010 0010 00000000

CTRL_REG4 rw 23 010 0011 00000000

CTRL_REG5 rw 24 010 0100 00000000

CTRL_REG6 rw 25 010 0101 00000000

REFERENCE rw 26 010 0110 00000000

STATUS_REG2 r 27 010 0111 00000000

FIFO READ START r 28 010 1000 Output

OUT_X r 29 010 1001 Output

Reserved r 2A 010 1010 Output

OUT_Y r 2B 010 1011 Output

Reserved r 2C 010 1100 Output

OUT_Z r 2D 010 1101 Output

FIFO_CTRL_REG rw 2E 010 1110 00000000

FIFO_SRC_REG r 2F 010 1111 00100000

INT1_CFG rw 30 011 0000 00000000

INT1_SOURCE r 31 011 0001 00000000

INT1_THS rw 32 011 0010 00000000

INT1_DURATION rw 33 011 0011 00000000

28/47 Doc ID 022536 Rev 1

LIS2DM Register mapping

Table 18. Register address map (continued)

Name Type

Hex Binary

INT2_CFG rw 34 011 0100 00000000

INT2_SOURCE r 35 011 0101 00000000

INT2_THS rw 36 011 0110 00000000

INT2_DURATION rw 37 011 0111 00000000

CLICK_CFG rw 38 011 1000 00000000

CLICK_SRC r 39 011 1001 00000000

CLICK_THS rw 3A 011 1010 00000000

TIME_LIMIT rw 3B 011 1011 00000000

TIME_LATENCY rw 3C 011 1100 00000000

TIME_WINDOW rw 3D 011 1101 00000000

Act_THS rw 3E 011 1110 00000000

Act_DUR rw 3F 011 1111 00000000

Default Comment

Registers marked as Reserved or not listed in Ta bl e 1 8 above must not be changed. The writing to those registers may cause permanent damage to the device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.

Boot procedure is complete about 5 milliseconds just after powering up the device.

Doc ID 022536 Rev 1 29/47

Registers Description LIS2DM

7 Registers Description

7.1 STATUS_AUX (07h)

Table 19. STATUS_REG_AUX register

-- TOR -- -- -- TDA -- --

Table 20. STATUS_REG_AUX description

TOR Temperature Data Overrun. Default value: 0

(0: no overrun has occurred; 1: a new temperature data has overwritten the previous one)

TDA Temperature new Data Available. Default value: 0

(0: a new temperature data is not yet available; 1: a new temperature data is available)

7.2 OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)

Temperature sensor data. Refer to Section 2.11: Temperature sensor for details on how to enable and read the temperature sensor output data.

7.3 INT_COUNTER (0Eh)

Table 21. INT_COUNTER register

IC7IC6IC5IC4IC3IC2IC1IC0

7.4 WHO_AM_I (0Fh)

Table 22. WHO_AM_I register

00110011

Device identification register.

7.5 TEMP_CFG_REG (1Fh)

Table 23. TEMP_CFG_REG register

TEMP_EN1TEMP_EN0000000

30/47 Doc ID 022536 Rev 1

LIS2DM Registers Description

Table 24. TEMP_CFG_REG description

TEMP_EN[1-0]

Temperature sensor (T) enable. Default value: 00 (00: T disabled; 11: T enabled)

7.6 CTRL_REG1 (20h)

Table 25. CTRL_REG1 register

ODR3 ODR2 ODR1 ODR0 1

1. This bit must be set to '1' for the correct device operation.

Table 26. CTRL_REG1 description

(1)

Zen Yen Xen

ODR3-0

Zen

Ye n

Xen

Data rate selection. Default value: 00 (0000: power down mode; Others: refer to Ta bl e 2 7 )

Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled)

Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled)

X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled)

ODR<3:0> is used to set ODR selection. In Tab le 2 7 all frequencies resulting in a combination of ODR<3:0>

Table 27. Data rate configuration

ODR3 ODR2 ODR1 ODR0 Power mode selection

0 0 0 0 Power down mode

0001Normal mode (1 Hz)

0 0 1 0 Normal mode (10 Hz)

0 0 1 1 Normal mode (25 Hz)

0 1 0 0 Normal mode (50 Hz)

0 1 0 1 Normal mode (100 Hz)

0 1 1 0 Normal mode (200 Hz)

0 1 1 1 Normal mode (400 Hz)

1 0 0 0 Normal mode (1.620 kHz)

1 0 0 1 Normal mode (5.376 kHz)

Doc ID 022536 Rev 1 31/47

Registers Description LIS2DM

7.7 CTRL_REG2 (21h)

Table 28. CTRL_REG2 register

HPM1 HPM0 HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1

Table 29. CTRL_REG2 description

HPM1 -HPM0 High pass filter Mode Selection. Default value: 00

Refer to Ta bl e 3 0

HPCF2 HPCF1

FDS

HPCLICK

HPIS2 High pass filter enabled for AOI function on interrupt 2,

HPIS1 High pass filter enabled for AOI function on interrupt 1,

High pass filter Cut Off frequency selection

Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO)

High pass filter enabled for CLICK function. (0: filter bypassed; 1: filter enabled)

(0: filter bypassed; 1: filter enabled)

Table 30. High pass filter mode configuration

HPM1 HPM0 High Pass filter mode

0 0 Normal mode (reset reading REFERENCE/DATACAPTURE (26h) register)

0 1 Reference signal for filtering

1 0 Normal mode

1 1 Autoreset on interrupt event

7.8 CTRL_REG3 (22h)

Table 31. CTRL_REG3 register

I1_CLICK I1_AOI1 I1_AOI2 I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN --

Table 32. CTRL_REG3 description

I1_CLICK CLICK interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

I1_AOI1 AOI1 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

32/47 Doc ID 022536 Rev 1

LIS2DM Registers Description

Table 32. CTRL_REG3 description (continued)

I1_AOI2 AOI2 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

I1_DRDY1 DRDY1 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

I1_DRDY2 DRDY2 interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

I1_WTM FIFO Watermark interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

I1_OVERRUN FIFO Overrun interrupt on INT1 pin. Default value 0.

(0: disable; 1: enable)

7.9 CTRL_REG4 (23h)

Table 33. CTRL_REG4 register

TDB 0

1. This bit must be set to “0” for the correct device operation.

(1)

FS1 FS0 0 ST1 ST0 SIM

Table 34. CTRL_REG4 description

TDB Refer to Section 2.11.

FS1-FS0 Full scale selection. Default value: 00

(00: +/- 2G; 01: +/- 4G; 10: +/- 8G; 11: +/- 16G)

ST1-ST0 Self-Test Enable. Default value: 00

(00: self-test disabled; Other: see Ta b l e 1 9)

SIM SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 35. Self test mode configuration

ST1 ST0 Self test mode

0 0 Normal mode

01Self-test 0

10Self-test 1

11--

7.10 CTRL_REG5 (24h)

Table 36. CTRL_REG5 register

BOOT FIFO_EN -- -- LIR_INT1 D4D_INT1 LIR_INT2 D4D_INT2

Doc ID 022536 Rev 1 33/47

Registers Description LIS2DM

Table 37. CTRL_REG5 description

BOOT Reboot memory content. Default value: 0

(0: Normal mode; 1: reboot memory content)

FIFO_EN FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO enable)

LIR_INT1 Latch interrupt request on the INT1_SRC register, with the INT1_SRC register

cleared by reading INT1_SRC itself. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched)

D4D_INT1

LIR_INT2 Latch interrupt request on the INT2_SRC register, with the INT2_SRC register

D4D_INT2

4D enable: 4D detection is enabled on INT1 pin when 6D bit on INT1_CFG is

set to 1.

cleared by reading INT2_SRC itself. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched)

4D enable: 4D detection is enabled on INT2 pin when 6D bit on INT2_CFG is

set to 1.

7.11 CTRL_REG6 (25h)

Table 38. CTRL_REG6 register

I2_CLICKen I2_INT1 I2_INT2 BOOT_I2 P2_ACT - - H_LACTIVE -

Table 39. CTRL_REG6 description

I2_CLICKen Click interrupt on INT2 pin. Default value: 0

(0: disable; 1: enable)

I2_INT1 Interrupt 1 function enabled on INT2 pin. Default value: 0

(0: function disable; 1: function enable)

I2_INT2 Interrupt 2 function enabled on INT2 pin. Default value: 0

(0: function disable; 1: function enable)

BOOT_I2

P2_ACT Activity interrupt enable on INT2 pin. Default value: 0.

H_LACTIVE

Boot on INT2 pin enable. Default value: 0

(0: disable; 1:enable)

interrupt active. Default value: 0.

(0: interrupt active high; 1: interrupt active low)

7.12 REFERENCE/DATACAPTURE (26h)

Table 40. REFERENCE register

Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0

34/47 Doc ID 022536 Rev 1

LIS2DM Registers Description

Table 41. REFERENCE register description

Ref 7-Ref0 Reference value for interrupt generation. Default value: 0

7.13 STATUS_REG (27h)

Table 42. STATUS register

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 43. STATUS register description

ZYXOR X, Y and Z axis Data Overrun. Default value: 0

(0: no overrun has occurred; 1: a new set of data has overwritten the previous ones)

ZOR Z axis Data Overrun. Default value: 0

(0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one)

YOR Y axis Data Overrun. Default value: 0

(0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one)

XOR X axis Data Overrun. Default value: 0

(0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one)

ZYXDA X, Y and Z axis New Data Available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

ZDA Z axis New Data Available. Default value: 0

(0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available)

YDA Y axis New Data Available. Default value: 0

(0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available)

7.14 FIFO_READ_START (28h)

FIFO starts reading the register. Before a new data reading from FIFO, perform a spare data read from FIFO_READ_START (28h).

7.15 OUT_X (29h)

X-axis acceleration data. The value is expressed as 2’s complement with 8-bit data.

7.16 OUT_Y (2Bh)

Y-axis acceleration data. The value is expressed as 2’s complement with 8-bit data.

Doc ID 022536 Rev 1 35/47

Registers Description LIS2DM

7.17 OUT_Z (2Dh)

Z-axis acceleration data. The value is expressed as 2’s complement with 8-bit data.

7.18 FIFO_CTRL_REG (2Eh)

Table 44. FIFO_CTRL_REG register

FM1 FM0 TR FTH4 FTH3 FTH2 FTH1 FTH0

Table 45. FIFO_CTRL_REG register description

FM1-FM0

TR Trigger selection. Default value: 0

FTH4:0 Default value: 0

FIFO mode selection. Default value: 00 (see

0: trigger event allows to trigger signal on INT1 1: trigger event allows to trigger signal on INT2

Ta bl e 4 6 )

Table 46. FIFO mode configuration

FM1 FM0 FIFO mode

0 0 Bypass mode

01FIFO mode

1 0 Stream mode

1 1 Trigger mode

7.19 FIFO_SRC_REG (2Fh)

Table 47. FIFO_SRC register

WTM OVRN_FIFO EMPTY FSS4 FSS3 FSS2 FSS1 FSS0

7.20 INT1_CFG (30h)

Table 48. INT1_CFG description

AOI AND/OR combination of interrupt events. Default value: 0. Refer to Ta b l e 49

6D 6 direction detection function enabled. Default value: 0. Refer to Tab l e 4 9

ZHIE/ ZUPE

36/47 Doc ID 022536 Rev 1

Enable interrupt generation on Z high event or on direction recognition. Default value: 0 (0: disable interrupt request;1: enable interrupt request)

LIS2DM Registers Description

Table 48. INT1_CFG description

ZLIE/ ZDOWNE

YHIE/ YUPE

Enable interrupt generation on Z low event or on direction recognition. Default value: 0 (0: disable interrupt request;1: enable interrupt request)

Enable interrupt generation on Y high event or on direction recognition. Default value: 0 (0: disable interrupt request; 1: enable interrupt request.)

YLIE/ YDOWNE

XHIE/ XUPE

XLIE/XDOWNEEnable interrupt generation on X low event or on direction recognition.

Enable interrupt generation on Y low event or on direction recognition. Default value: 0 (0: disable interrupt request; 1: enable interrupt request.)

Enable interrupt generation on X high event or on direction recognition. Default value: 0 (0: disable interrupt request; 1: enable interrupt request.)

Default value: 0 (0: disable interrupt request; 1: enable interrupt request.)

Content of this register is loaded at boot.

Write operation at this address is possible only after system boot.

Table 49. Interrupt mode

AOI 6D Interrupt mode

0 0 OR combination of interrupt events

0 1 6 direction movement recognition

1 0 AND combination of interrupt events

1 1 6 direction position recognition

Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.

AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves from unknown zone to known zone. The interrupt signal stays for a duration ODR.

AOI-6D = ‘11’ is direction recognition. An interrupt is generated when orientation is inside a known zone. The interrupt signal stays until orientation is inside the zone.

7.21 INT1_SRC (31h)

Table 50. INT1_SRC register

0 IA ZHZLYHYLXHXL

Table 51. INT1_SRC description

Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred)

Doc ID 022536 Rev 1 37/47

Registers Description LIS2DM

Table 51. INT1_SRC description

Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0 (0: no interrupt, 1: X high event has occurred)

X low. Default value: 0 (0: no interrupt, 1: X low event has occurred)

Interrupt 1 source register. Read only register.

Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option was chosen.

7.22 INT1_THS (32h)

Table 52. INT1_THS register

0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 53. INT1_THS description

Interrupt 1 threshold. Default value: 000 0000 1LSb = 16 mg @FS=2g

THS6 - THS0

1LSb = 32 mg @FS=4g 1LSb = 62 mg @FS=8g 1LSb = 186 mg @FS=16g

7.23 INT1_DURATION (33h)

Table 54. INT1_DURATION register

0 D6D5D4D3D2D1D0

Table 55. INT1_DURATION description

D6 - D0

D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen.

Duration time is measured in N/ODR, where N is the content of the duration register.

Duration value. Default value: 000 0000 1 LSb = 1/ODR

38/47 Doc ID 022536 Rev 1

LIS2DM Registers Description

7.24 INT2_CFG (34h)

Table 56. INT2_CFG register

AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 57. INT2_CFG description

AOI

6D 6 direction detection function enabled. Default value: 0. Refer to Tab l e 58

ZHIE

ZLIE

YHIE

AND/OR combination of interrupt events. Default value: 0. (See Ta b le 5 8 below)

Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0

YLIE

XHIE

XLIE

(0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

The content of this register is loaded at boot.

Write operation at this address is possible only after system boot.

Table 58. Interrupt mode

AOI 6D Interrupt mode

0 0 OR combination of interrupt events

0 1 6 direction movement recognition

1 0 AND combination of interrupt events

1 1 6 direction position recognition

Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.

Doc ID 022536 Rev 1 39/47

Registers Description LIS2DM

AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves from an unknown zone to a known zone. The interrupt signal stays for a duration ODR.

AOI-6D = ‘11’ is direction recognition. An interrupt is generated when orientation is inside a known zone. The interrupt signal stays until orientation is inside the zone.

7.25 INT2_SRC (35h)

Table 59. INT2_SRC register

0 IA ZHZLYHYLXHXL

Table 60. INT2_SRC description

Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0 (0: no interrupt, 1: X high event has occurred)

X Low. Default value: 0 (0: no interrupt, 1: X low event has occurred)

Interrupt 2 source register. Read only register.

Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT 2 pin) and allows the refreshment of data in the INT2_SRC register if the latched option was chosen.

7.26 INT2_THS (36h)

Table 61. INT2_THS register

0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

40/47 Doc ID 022536 Rev 1

LIS2DM Registers Description

Table 62. INT2_THS description

Interrupt 2 threshold. Default value: 000 0000

1LSb = 16 mg @FS=2g;

THS6 - THS0

1LSb = 32 mg @FS=4g; 1LSb = 62 mg @FS=8g; 1LSb = 186 mg @FS=16g

7.27 INT2_DURATION (37h)

Table 63. INT2_DURATION register

0 D6D5D4D3D2D1D0

Table 64. INT2_DURATION description

D6-D0

Duration value. Default value: 000 0000 1 LSb = 1/ODR

(1)

1. Duration time is measured in N/ODR, where N is the content of the duration register.

D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen.

7.28 CLICK_CFG (38h)