ST LIS2DM User Manual

LIS2DM

MEMS digital output motion sensor: ultra low-power high performance 3-axis “femto” accelerometer

Features

■Wide supply voltage, 1.71 V to 3.6 V

■Independent IOs supply (1.8 V) and supply voltage compatible

■Ultra low-power mode consumption down to 2 µA

■±2g/±4g/±8g/±16g dynamically selectable full scale

■I2C/SPI digital output interface

■8-bit data output

■2 independent programmable interrupt generators for free-fall and motion detection

■6D/4D orientation detection

■“Sleep to wake” and “Return to sleep” function

■Free-fall detection

■Motion detection

■Embedded temperature sensor

■Embedded FIFO

■ECOPACK® RoHS and “Green” compliant

Applications

■Motion activated functions

■Display orientation

■Shake control

■Pedometer

■Gaming and virtual reality input devices

■Impact recognition and logging

Description

The LIS2DM is an ultra low-power high performance 3-axis linear accelerometer belonging to the “femto” family, with digital I2C/SPI serial interface standard output.

LGA-14 (2.0x2.0x1mm)

The LIS2DM has dynamically user selectable full scales of ±2g/±4g/±8g/±16g and it is capable of measuring accelerations with output data rates from 1 Hz to 5.3 kHz.

The self-test capability allows the user to check the functioning of the sensor in the final application.

The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself.

The LIS2DM is available in a small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

	Table 1.	Device summary
	Order	Temperature	Package	Packaging
	codes	range [° C]
	LIS2DM	-40 to +85	LGA-14	Tray
	LIS2DMTR	-40 to +85	LGA-14	Tape and
				reel

November 2011

Doc ID 022536 Rev 1

1/47

www.st.com

Contents	LIS2DM

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
	1.1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	1.2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
2	Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . .		10
	2.1	Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2	Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.4	Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . .	12

2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.3 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.4 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.5 6D / 4D orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.6 “Sleep to wake” and “Return to sleep” . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.7 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.9 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3	Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	3.1	Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
4	Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20

4.1 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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4.1.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.4 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.5 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5	Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	5.1	I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

	5.2.1	SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	5.2.2	SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	5.2.3	SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
6	Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
7	Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30

7.1 STATUS_AUX (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2 OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh) . . . . . . . . . . . . . . . . . . . . . . 30

7.3 INT_COUNTER (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 TEMP_CFG_REG (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.6 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.7 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.8 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.9 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.10 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.11 CTRL_REG6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.12 REFERENCE/DATACAPTURE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.13 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.14 FIFO_READ_START (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.15 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.16 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.17 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.18 FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.19 FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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	7.20	INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 36
	7.21	INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 37
	7.22	INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 38
	7.23	INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 38
	7.24	INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 39
	7.25	INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 40
	7.26	INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 40
	7.27	INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 41
	7.28	CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 41
	7.29	CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 42
	7.30	CLICK_THS (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 42
	7.31	TIME_LIMIT (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 43
	7.32	TIME_LATENCY (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 43
	7.33	TIME WINDOW(3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 43
	7.34	Act_THS(3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 43
	7.35	Act_DUR (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 44
8	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . 45
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . 46

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LIS2DM	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Normal mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10. Current consumption vs. ODR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 14. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 15. Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 16. Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 23 Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23 Table 18. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 19. STATUS_REG_AUX register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 20. STATUS_REG_AUX description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 21. INT_COUNTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 22. WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 23. TEMP_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 24. TEMP_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 25. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 26. CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 27. Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 28. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 29. CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 30. High pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 31. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 32. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 33. CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 34. CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 35. Self test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 36. CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 37. CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 38. CTRL_REG6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 39. CTRL_REG6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 40. REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 41. REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 42. STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 43. STATUS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 44. FIFO_CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 45. FIFO_CTRL_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 46. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 47. FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 48. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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List of tables	LIS2DM

Table 49. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 50. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 51. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 52. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 53. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 54. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 55. INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 56. INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 57. INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 58. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 59. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 60. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 61. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 62. INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 63. INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 64. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 65. CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 66. CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 67. CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 68. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 69. CLICK_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 70. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 71. TIME_LIMIT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 72. TIME_LIMIT description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 73. TIME_LATENCY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 74. TIME_LATENCY description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 75. TIME_WINDOW register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 76. TIME_WINDOW description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 77. TIME_WINDOW register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 78. TIME_WINDOW description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 79. Act_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 80. Act_DUR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 81. LGA-14 2x2x1 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 82. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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LIS2DM	List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. LIS2DM electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8. Multiple bytes SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Multiple bytes SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12. LGA-14 2x2x1 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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Block diagram and pin description	LIS2DM

1 Block diagram and pin description

1.1Block diagram

Figure 1. Block diagram

	X+
	Y+	CHARGE				CS
		AMPLIFIER
	Z+
						SCL/SPC
				CONTROL	I2C
a
			A/D
				LOGIC		SDA/SDO/SDI
	MUX		CONVERTER
					SPI
	Z-					SDO/SA0
	Y-
	X-
	Temperature	TRIMMING		32 Level	CONTROL LOGIC		INT 1
SELF TEST			CLOCK			&
	Sensor	CIRCUITS		FIFO
					INTERRUPT GEN.		INT 2
							AM10218V1

1.2Pin description

Figure 2. Pin connection

Z

1

X Y

(TOP VIEW)

DIRECTION OF THE DETECTABLE ACCELERATIONS

				Res		Res		Res		Pin 1 indicator
				12				14
GND											SCL/SPC
		11								1
GND											SDA/SDI/SDO
GND											SDO/SA0
Vdd											CS
		8								4
				7				5
				Vdd IO		INT1		INT2

(BOTTOM VIEW)

AM10218V1

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LIS2DM				Block diagram and pin description
	Table 2.	Pin description
	Pin#		Name	Function
	1		SCL	I2C serial clock (SCL)
			SPC	SPI serial port clock (SPC)
			SDA	I2C serial data (SDA)
	2		SDI	SPI serial data input (SDI)
			SDO	3-wire interface serial data output (SDO)
	3		SDO	SPI serial data output (SDO)
			SA0	I2C less significant bit of the device address (SA0)
				SPI enable
	4		CS	I2C/SPI mode selection (1: SPI idle mode / I2C communication
				enabled; 0: SPI communication mode / I2C disabled)
	5		INT2	Interrupt pin 2
	6		INT1	Interrupt pin 1
	7		Vdd_IO	Power supply for I/O pins
	8		Vdd	Power supply
	9		GND	0 V supply
	10		Res	Connect to GND
	11		Res	Connect to GND
	12-14		Res	Connect to GND

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Mechanical and electrical specifications	LIS2DM

2 Mechanical and electrical specifications

2.1Mechanical characteristics

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(a).

Table 3.	Mechanical characteristics
Symbol	Parameter	Test conditions	Min.	Typ.(1)	Max.	Unit
		FS bit set to 00		±2.0
FS	Measurement range(2)	FS bit set to 01		±4.0		g
		FS bit set to 10		±8.0
		FS bit set to 11		±16.0
		FS bit set to 00;		16
		Low power mode
		FS bit set to 01;		32
		Low power mode
So	Sensitivity					mg/digit
		FS bit set to 10;		64
		Low power mode
		FS bit set to 11;		192
		Low power mode
TCSo	Sensitivity change vs.	FS bit set to 00		0.01		%/°C
	temperature
TyOff	Typical zero-g level	FS bit set to 00		±100		mg
	offset accuracy(3),(4)
TCOff	Zero-g level change	Max. delta from 25 °C		±1		mg/°C
	vs. temperature
		FS bit set to 00 X axis;	6		90	LSb
	Self-test
Vst		FS bit set to 00 Y axis;	6		90	LSb
	(5),(6),(7)
	output change
		FS bit set to 00 Z axis;	6		90	LSb
Top	Operating		-40		+85	°C
	temperature range

1.Typical specifications are not guaranteed.

2.Verified by wafer level test and measurement of initial offset and sensitivity.

3.Typical zero-g level offset value after MSL3 preconditioning.

4.Offset can be eliminated by enabling the built-in high pass filter.

5.The sign of “Self-test output change” is defined by CTRL_REG4 ST bit, for all axes.

6.“Self-test output change” is defined as the absolute value of:

OUTPUT[LSb](Self test enabled) - OUTPUT[LSb](Self test disabled). 1LSb=16mg at 8-bit representation, ±2 g full-scale.

7.After enabling self-test, the correct data is obtained after two samples.

a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71V to 3.6 V.

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LIS2DM	Mechanical and electrical specifications

2.2Temperature sensor characteristics

@ Vdd =2.5 V, T=25 °C unless otherwise noted(b).

Table 4.	Temperature sensor characteristics
Symbol		Parameter	Test condition	Min.	Typ.(1)	Max.	Unit
TSDr		Temperature sensor output			1		digit/°C(2)
		change vs. temperature
TODR		Temperature refresh rate			ODR(3)		Hz
Top		Operating temperature range		-40		+85	°C

1.Typical specifications are not guaranteed.

2.8-bit resolution.

3.Refer to Table 27.

2.3Electrical characteristics

@ Vdd =2.5 V, T=25 °C unless otherwise noted(c).

Table 5.	Electrical characteristics
Symbol		Parameter	Test conditions	Min.	Typ.(1)	Max.	Unit
Vdd		Supply voltage		1.71	2.5	3.6	V
Vdd_IO		I/O pins supply voltage(2)		1.71		Vdd+0.1	V
Idd		Current consumption in Normal	50 Hz ODR		6		µA
		mode
IddPdn		Current consumption in power			0.5		µA
		down mode
VIH		Digital high level input voltage		0.8*Vdd_IO			V
VIL		Digital low level input voltage				0.2*Vdd_IO	V
VOH		High level output voltage		0.9*Vdd_IO			V
VOL		Low level output voltage				0.1*Vdd_IO	V
Top		Operating temperature range		-40		+85	°C

1.Typical specification are not guaranteed.

2.It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.

b.The product is factory calibrated at 2.5 V. Temperature sensor operation is guaranteed in the range 2 V - 3.6 V.

c.The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.

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Mechanical and electrical specifications	LIS2DM

2.4Communication interface characteristics

2.4.1SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 6.	SPI slave timing values
Symbol		Parameter		Value (1)		Unit
			Min.		Max.
tc(SPC)		SPI clock cycle	100			ns
fc(SPC)		SPI clock frequency			10	MHz
tsu(CS)		CS setup time	5
th(CS)		CS hold time	10
tsu(SI)		SDI input setup time	5
th(SI)		SDI input hold time	15			ns
tv(SO)		SDO valid output time			50
th(SO)		SDO output hold time	5
tdis(SO)		SDO output disable time			50

1.Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

Figure 3. SPI slave timing diagram(d)

CS	(3)					(3)
	su(CS)			c(SPC)	h(CS)
SPC	(3)					(3)
		su(SI)	h(SI)
SDI	(3)	MSB IN			LSB IN	(3)
			v(SO)	h(SO)		dis(SO)
SDO	(3)		MSB OUT		LSB OUT	(3)

3.When no communication is ongoing, data on SDO is driven by internal pull-up resistors.

d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

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2.4.2I2C - Inter IC control interface

Subject to general operating conditions for Vdd and top.

Table 7.	I2C slave timing values
Symbol		Parameter	I2C standard mode (1)		I2C fast mode (1)			Unit
			Min.	Max.	Min.		Max.
f(SCL)		SCL clock frequency	0	100	0		400	kHz
tw(SCLL)		SCL clock low time	4.7		1.3			µs
tw(SCLH)		SCL clock high time	4.0		0.6
tsu(SDA)		SDA setup time	250		100			ns
th(SDA)		SDA data hold time	0	3.45	0.01		0.9	µs
tr(SDA) tr(SCL)		SDA and SCL rise time		1000	20 + 0.1C	(2)	300
						b		ns
tf(SDA) tf(SCL)		SDA and SCL fall time		300	20 + 0.1C	(2)	300
						b
th(ST)		START condition hold time	4		0.6
tsu(SR)		Repeated START condition	4.7		0.6
		setup time
								µs
tsu(SP)		STOP condition setup time	4		0.6
tw(SP:SR)		Bus free time between STOP	4.7		1.3
		and START condition

1.Data based on standard I2C protocol requirement, not tested in production.

2.Cb = total capacitance of one bus line, in pF.

Figure 4. I2C Slave timing diagram (e)

CS	(3)					(3)
	su(CS)			c(SPC)	h(CS)
SPC	(3)					(3)
		su(SI)	h(SI)
SDI	(3)	MSB IN			LSB IN	(3)
			v(SO)	h(SO)		dis(SO)
SDO	(3)		MSB OUT		LSB OUT	(3)

e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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Mechanical and electrical specifications	LIS2DM

2.5Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

	Table 8.	Absolute maximum ratings
	Symbol	Ratings	Maximum value	Unit
	Vdd	Supply voltage	-0.3 to 4.8	V
	Vdd_IO	I/O pins supply voltage	-0.3 to 4.8	V
	Vin	Input voltage on any control pin	-0.3 to Vdd_IO +0.3	V
		(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
	APOW	Acceleration (any axis, powered, Vdd = 2.5 V)	3000 g for 0.5 ms
			10000 g for 0.1 ms
	AUNP	Acceleration (any axis, unpowered)	3000 g for 0.5 ms
			10000 g for 0.1 ms
	TOP	Operating temperature range	-40 to +85	°C
	TSTG	Storage temperature range	-40 to +125	°C
	ESD	Electrostatic discharge protection	2 (HBM)	kV
Note:	Supply voltage on any pin should never exceed 4.8 V

This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part.

This is an ESD sensitive device, improper handling can cause permanent damage to the part.

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2.6Terminology and functionality

Terminology

2.6.1Sensitivity

Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The sensitivity tolerance describes the range of Sensitivities of a large population of sensors.

2.6.2Zero-g level

Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in steady-state on a horizontal surface measures 0 g in the X axis and 0 g in the Y axis whereas the Z axis measures 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see Table 3: Mechanical characteristics. The Zero-g level tolerance (TyOff) describes the standard deviation of the range of Zero-g levels of a population of sensors.

Functionality

2.6.3Normal mode

The LIS2DM provides a single operating mode called normal mode.

Table 9 summarizes operating mode performances.

	Table 9.	Normal mode features
	Operating mode		BW	Turn-on time	So @ ±2g
			[Hz]	[ms]	[mg/digit]
	Normal mode		ODR/2	1	16

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