ultra low-power high performance 3-axis “femto” accelerometer
LGA-14
(2.0x2.0x1mm)
Features
■ Wide supply voltage, 1.71 V to 3.6 V
■ Independent IOs supply (1.8 V) and supply
voltage compatible
■ Ultra low-power mode consumption down to 2
µA
■ ±2g/±4g/±8g/±16g dynamically selectable full
scale
2
■ I
C/SPI digital output interface
■ 8-bit data output
■ 2 independent programmable interrupt
generators for free-fall and motion detection
■ 6D/4D orientation detection
■ “Sleep to wake” and “Return to sleep” function
■ Free-fall detection
■ Motion detection
■ Embedded temperature sensor
■ Embedded FIFO
■ ECOPACK
Applications
®
RoHS and “Green” compliant
LIS2DM
MEMS digital output motion sensor:
The LIS2DM has dynamically user selectable full
scales of ±2g/±4g/±8g/±16g and it is capable of
measuring accelerations with output data rates
from 1 Hz to 5.3 kHz.
The self-test capability allows the user to check
the functioning of the sensor in the final
application.
The device may be configured to generate
interrupt signals by two independent inertial
wake-up/free-fall events as well as by the position
of the device itself.
The LIS2DM is available in a small thin plastic
land grid array package (LGA) and is guaranteed
to operate over an extended temperature range
from -40 °C to +85 °C.
■ Motion activated functions
■ Display orientation
■ Shake control
■ Pedometer
■ Gaming and virtual reality input devices
■ Impact recognition and logging
Description
Table 1.Device summary
Order
codes
LIS2DM-40 to +85LGA-14Tray
LIS2DMTR-40 to +85LGA-14
Temperature
range [° C]
PackagePackaging
Tape and
reel
The LIS2DM is an ultra low-power high
performance 3-axis linear accelerometer
belonging to the “femto” family, with digital I
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
I2C less significant bit of the device address (SA0)
SPI enable
2
I
C/SPI mode selection (1: SPI idle mode / I2C communication
enabled; 0: SPI communication mode / I
2
C disabled)
12-14ResConnect to GND
Doc ID 022536 Rev 19/47
Mechanical and electrical specificationsLIS2DM
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted
Table 3.Mechanical characteristics
SymbolParameterTest conditionsMin.Typ.
FS bit set to 00±2.0
FS bit set to 01±4.0
FSMeasurement range
SoSensitivity
TCSo
Ty O ff
TCOff
Vst
To p
1. Typical specifications are not guaranteed.
2. Verified by wafer level test and measurement of initial offset and sensitivity.
3. Typical zero-g level offset value after MSL3 preconditioning.
4. Offset can be eliminated by enabling the built-in high pass filter.
5. The sign of “Self-test output change” is defined by CTRL_REG4 ST bit, for all axes.
“Self-test output change” is defined as the absolute value of:
6.
OUTPUT[LSb]
7. After enabling self-test, the correct data is obtained after two samples.
Sensitivity change vs.
temperature
Ty p i c a l ze ro -
g level
offset accuracy
Zero-
g level change
vs. temperature
Self-test
output change
Operating
temperature range
(Self test enabled)
(2)
FS bit set to 10±8.0
FS bit set to 11±16.0
FS bit set to 00;
Low power mode
FS bit set to 01;
Low power mode
FS bit set to 10;
Low power mode
FS bit set to 11;
Low power mode
FS bit set to 000.01%/°C
(3),(4)
FS bit set to 00±100mg
Max. delta from 25 °C±1m
FS bit set to 00 X axis; 690LSb
(5),(6),(7)
FS bit set to 00 Y axis; 690LSb
FS bit set to 00 Z axis;690LSb
- OUTPUT[LSb]
(Self test disabled)
. 1LSb=16mg at 8-bit representation, ±2 g full-scale.
(a)
.
(1)
16
32
64
192
-40+85°C
Max.Unit
g
mg/digit
g/°C
a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71V to 3.6 V.
10/47Doc ID 022536 Rev 1
LIS2DMMechanical and electrical specifications
2.2 Temperature sensor characteristics
@ Vdd =2.5 V, T=25 °C unless otherwise noted
Table 4.Temperature sensor characteristics
SymbolParameterTest conditionMin.Typ.
(b)
.
(1)
Max.Unit
TSDr
TODRTemperature refresh rateODR
Temperature sensor output
change vs. temperature
1digit/°C
(3)
Top Operating temperature range-40+85°C
1. Typical specifications are not guaranteed.
2. 8-bit resolution.
3. Refer to Table 27.
2.3 Electrical characteristics
@ Vdd =2.5 V, T=25 °C unless otherwise noted
Table 5.Electrical characteristics
SymbolParameterTest conditionsMin.Typ.
VddSupply voltage1.712.53.6V
Vdd_IOI/O pins supply voltage
Idd
IddPdn
Current consumption in Normal
mode
Current consumption in power
down mode
VIHDigital high level input voltage0.8*Vdd_IOV
(2)
50 Hz ODR6µA
(c)
.
(1)
Max.Unit
1.71Vdd+0.1V
0.5µA
(2)
Hz
VILDigital low level input voltage0.2*Vdd_IOV
VOHHigh level output voltage0.9*Vdd_IOV
VOLLow level output voltage0.1*Vdd_IOV
TopOperating temperature range-40+85
1. Typical specification are not guaranteed.
2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
b. The product is factory calibrated at 2.5 V. Temperature sensor operation is guaranteed in the range 2 V - 3.6 V.
c. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.
Doc ID 022536 Rev 111/47
°C
Mechanical and electrical specificationsLIS2DM
SPC
CS
SDI
SDO
t
su(CS)
t
v(SO)
t
h(SO)
t
h(SI)
t
su(SI)
t
h(CS)
t
dis(SO)
t
c(SPC)
MSB IN
MSB OUT
LSB OUT
LSB IN
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6.SPI slave timing values
(1)
Val u e
SymbolParameter
Min.Max.
tc(SPC)SPI clock cycle100ns
fc(SPC)SPI clock frequency10MHz
tsu(CS)CS setup time5
th(CS)CS hold time10
tsu(SI)SDI input setup time5
th(SI)SDI input hold time15
tv(SO)SDO valid output time50
th(SO)SDO output hold time5
tdis(SO)SDO output disable time50
Unit
ns
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
(d)
Figure 3.SPI slave timing diagram
3.When no communication is ongoing, data on SDO is driven by internal pull-up resistors.
12/47Doc ID 022536 Rev 1
d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
LIS2DMMechanical and electrical specifications
SPC
CS
SDI
SDO
t
su(CS)
t
v(SO)
t
h(SO)
t
h(SI)
t
su(SI)
t
h(CS)
t
dis(SO)
t
c(SPC)
MSB IN
MSB OUT
LSB OUT
LSB IN
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
2.4.2 I2C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 7.I2C slave timing values
SymbolParameter
I2C standard mode
(1)
I2C fast mode
Min.Max.Min.Max.
(1)
Unit
f
(SCL)
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA) tr(SCL)
t
f(SDA) tf(SCL)
t
h(ST)
t
su(SR)
t
su(SP)
t
w(SP:SR)
SCL clock frequency01000400kHz
SCL clock low time4.71.3
SCL clock high time4.00.6
SDA setup time250100ns
SDA data hold time03.450.010.9µs
SDA and SCL rise time1000
SDA and SCL fall time300
START condition hold time40.6
Repeated START condition
setup time
4.70.6
STOP condition setup time40.6
Bus free time between STOP
and START condition
4.71.3
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
Figure 4.I
2
C Slave timing diagram
(e)
20 + 0.1C
20 + 0.1C
µs
(2)
b
(2)
b
300
ns
300
µs
e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Doc ID 022536 Rev 113/47
Mechanical and electrical specificationsLIS2DM
This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part.
This is an ESD sensitive device, improper handling can cause permanent damage to
the part.
2.5 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 8.Absolute maximum ratings
SymbolRatingsMaximum valueUnit
VddSupply voltage-0.3 to 4.8V
Vdd_IOI/O pins supply voltage-0.3 to 4.8V
Vin
A
POW
A
UNP
T
T
STG
ESDElectrostatic discharge protection 2 (HBM)kV
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Acceleration (any axis, powered, Vdd = 2.5 V)
Acceleration (any axis, unpowered)
Operating temperature range-40 to +85°C
OP
Storage temperature range-40 to +125°C
-0.3 to Vdd_IO +0.3V
3000 g for 0.5 ms
10000 g for 0.1 ms
3000 g for 0.5 ms
10000 g for 0.1 ms
Note:Supply voltage on any pin should never exceed 4.8 V
14/47Doc ID 022536 Rev 1
LIS2DMMechanical and electrical specifications
2.6 Terminology and functionality
Terminology
2.6.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g
acceleration to it. As the sensor can measure DC accelerations this can be done easily by
pointing the axis of interest towards the center of the earth, noting the output value, rotating
the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing
so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and also time. The sensitivity tolerance describes
the range of Sensitivities of a large population of sensors.
2.6.2 Zero-g level
Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in steady-state on a horizontal surface
measures 0 g in the X axis and 0 g in the Y axis whereas the Z axis measures 1 g. The
output is ideally in the middle of the dynamic range of the sensor (content of OUT registers
00h, data expressed as 2’s complement number). A deviation from the ideal value in this
case is called Zero-g offset. Offset is to some extent a result of stress to the MEMS sensor
and therefore the offset can slightly change after mounting the sensor onto a printed circuit
board or exposing it to extensive mechanical stress. Offset changes little over temperature,
see Table 3: Mechanical characteristics. The Zero-g level tolerance (TyOff) describes the
standard deviation of the range of Zero-g levels of a population of sensors.
Functionality
2.6.3 Normal mode
The LIS2DM provides a single operating mode called normal mode.
Ta bl e 9 summarizes operating mode performances.
Table 9.Normal mode features
Operating mode
Normal modeODR/2116
BW
[Hz]
Turn-on time
[ms]
So @ ±2g
[mg/digit]
Doc ID 022536 Rev 115/47
Mechanical and electrical specificationsLIS2DM
Table 10.Current consumption vs. ODR
Operating mode
12
103
254
506
10010
20018
40036
1620100
5376185
2.6.4 Self-test
Self-test allows the checking of the sensor functionality without moving it. When the self-test
is enabled an actuation force is applied to the sensor, simulating a definite input
acceleration. In this case the sensor outputs exhibit a change in their DC levels which are
related to the selected full scale through the device sensitivity. When self-test is activated,
the device output level is given by the algebraic sum of the signals produced by the
acceleration acting on the sensor and by the electrostatic test-force. If the output signals
change within the amplitude specified in Ta bl e 3 , then the sensor is working properly and
the parameters of the interface chip are within the defined specifications.
[Hz]
Normal mode
[µA]
2.6.5 6D / 4D orientation detection
The LIS2DM includes 6D / 4D orientation detection. In this configuration the interrupt is
generated when the device is stable in a known direction. In 4D configuration the Z axis
position detection is disabled.
2.6.6 “Sleep to wake” and “Return to sleep”
The LIS2DM can be programmed to automatically switch to low power mode upon
recognition of a determined event.
Once the event condition is over, the device returns to the preset normal or high resolution
mode.
To enable this function the desired threshold value must be stored in the Act_THS(3Eh)
registers while the duration value is written in the Act_DUR(3Fh) registers.
When the acceleration module becomes lower than the threshold value, the device
automatically switches to low power mode (10Hz ODR).
During this condition, ODRx bits and the LPen bit in CTRL_REG1 (20h) are not considered.
As soon as the acceleration goes back over the threshold, the systems restore the operating
mode and ODRs for the CTRL_REG1 (20h) and CTRL_REG3 (22h) settings.
16/47Doc ID 022536 Rev 1
LIS2DMMechanical and electrical specifications
2.7 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows the transfer of suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques, a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor, the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the capacitor.
At steady-state the nominal value of the capacitors are a few pF and when an acceleration is
applied the maximum variation of the capacitive load is in the fF range.
2.8 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which
converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is
finally available to the user through an analog-to-digital converter.
The acceleration data may be accessed through an I
device particularly suitable for direct interfacing with a microcontroller.
2
C/SPI interface, therefore making the
The LIS2DM features a data-ready signal (RDY) which indicates when a new set of
measured acceleration data is available, therefore simplifying data synchronization in the
digital system that uses the device.
The LIS2DM may also be configured to generate an inertial Wake-Up and Free-Fall interrupt
signal according to a programmed acceleration event along the enabled axes. Both free-fall
and wake-up can be available simultaneously on two different pins.
Doc ID 022536 Rev 117/47
Mechanical and electrical specificationsLIS2DM
2.9 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).
The trimming values are stored inside the device in a non-volatile memory. Anytime the
device is turned on, the trimming parameters are downloaded into the registers to be used
during the active operation. This allows use of the device without further calibration.
2.10 FIFO
The LIS2DM contains a10-bit, 32-level FIFO. Buffered output allows 4 operation modes:
FIFO, stream, trigger and FIFO bypass. Where FIFO bypass mode is activated, FIFO is not
operating and remains empty. In FIFO mode, data from acceleration detection on X, Y, and
Z-axes measurements are stored in FIFO.
2.11 Temperature sensor
The LIS2DM is supplied with an internal temperature sensor. Temperature data can be
enabled by setting the TEMP_EN bit of the TEMP_CFG_REG register to 1.
To retrieve the temperature sensor data, the TDB temperature dummy bit on CTRL_REG4
(23h) must be set to ‘1’.
Both OUT_TEMP_H and OUT_TEMP_L registers must be read.
Temperature data is stored in OUT_TEMP_H as 2’s complement data in 8-bit format left
justified.
18/47Doc ID 022536 Rev 1
LIS2DMApplication hints
3 Application hints
Figure 5.LIS2DM electrical connection
Vdd_IO
GND
Pin 1 indicator
1214
SCL/SPC
SDA/SDI/SDO
SDO/SA0
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
CS
1
4
INT2
INT1
7
Vdd_IO
5
11
GND
GND
GND
Vdd
8
Vdd
10µF
100nF
GND
AM10220V1
The device core is supplied through the Vdd line while the I/O pads are supplied through the
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should
be placed as near as possible to pin 8 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to obtain proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I
2
C or SPI interfaces. When using the I2C, CS must be tied high.
The functions, the threshold, and the timing of the two interrupt pins (INT1 and INT2) can be
completely programmed by the user through the I
3.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS, and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com
Doc ID 022536 Rev 119/47
2
C/SPI interface.
.
Digital main blocksLIS2DM
4 Digital main blocks
4.1 FIFO
The LIS2DM embeds a 32-slot data FIFO for each of the three output channels, X, Y and Z.
This allows a consistent power saving for the system, since the host processor does not
need to continuously poll data from the sensor, but it can wake up only when needed and
burst the significant data out from the FIFO. This buffer can work accordingly to four different
modes: bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is
selected by the FIFO_MODE bits in FIFO_CTRL_REG (2E). Programmable Watermark
level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on
the INT1/2 pin (configuration through FIFO_CFG_REG).
4.1.1 Bypass mode
In bypass mode, the FIFO is not operational and for this reason it remains empty. As
described in the next figure, for each channel only the first address is used. The remaining
FIFO slots are empty.
4.1.2 FIFO mode
In FIFO mode, data from X, Y and Z channels are stored in the FIFO. A Watermark interrupt
can be enabled (FIFO_WTMK_EN bit in FIFO_CTRL_REG (2E) in order to be raised when
the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG
(2E). The FIFO continues filling until it is full (32 slots of data for X, Y and Z). When full, the
FIFO stops collecting data from the input channels.
4.1.3 Stream mode
In Stream mode, data from X, Y and Z measurements are stored in the FIFO. A Watermark
interrupt can be enabled and set as in FIFO mode.The FIFO continues filling until it’s full
(32 slots of data for X, Y and Z). When full, the FIFO discards the older data as the new
arrive.
4.1.4 Stream-to-FIFO mode
In Stream-to_FIFO mode, data from X, Y and Z measurements are stored in the FIFO. A
Watermark interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG) in order
to be raised when the FIFO is filled to the level specified in the FIFO_WTMK_LEVEL bits of
FIFO_CTRL_REG. The FIFO continues filling until it’s full (32 slots of 10-bit for X, Y and Z).
When full, the FIFO discards the older data as the new arrive. Once a trigger event occurs,
the FIFO starts operating in FIFO mode.
4.1.5 Retrieve data from FIFO
FIFO data is read through OUT_X (Addr reg 29h), OUT_Y (Addr reg 2Bh), and OUT_Z
(Addr reg 2Dh). When the FIFO is in Stream, Trigger or FIFO mode, a read operation to the
OUT_X, OUT_Y or OUT_Z registers provides the data stored in the FIFO. Each time data is
read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X, OUT_Y and
OUT_Z registers and both single read and read_burst operations can be used. The reading
address is automatically updated by the device and it rolls back to 0x28 when register 0x2D
is reached. In order to read all FIFO levels in a multiple byte reading,192 bytes (6 output
registers by 32 levels) must be read.
20/47Doc ID 022536 Rev 1
LIS2DMDigital interfaces
5 Digital interfaces
The registers embedded in the LIS2DM may be accessed through both the I2C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I
CS line must be tied high (i.e. connected to Vdd_IO).
Table 11.Serial interface pin description
Pin namePin description
SPI enable
CS
SCL
SPC
SDA
SDI
SDO
I2C/SPI mode selection (1: SPI idle mode / I2C communication
enabled; 0: SPI communication mode / I2C disabled)
2
I
C serial clock (SCL)
SPI serial port clock (SPC)
2
I
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
2
C interface, the
SA0
SDO
I2C less significant bit of the device address (SA0)
SPI serial data output (SDO)
5.1 I2C serial interface
The LIS2DM I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I
Table 12.Serial interface pin description
TransmitterThe device which sends data to the bus
ReceiverThe device which receives data from the bus
Master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up
resistor. When the bus is free, both lines are high.
2
The I
C interface is compliant with fast mode (400 kHz) I2C standards as well as with
Normal mode.
2
C terminology is given in Tab l e 1 2 below.
TermDescription
The device which initiates a transfer, generates clock signals and terminates a
transfer
SlaveThe device addressed by the master
Doc ID 022536 Rev 121/47
Digital interfacesLIS2DM
5.1.1 I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The slave address (SAD) associated to the LIS2DM is 001100xb. The SDO/SA0 pad can be
used to modify the less significant bit of the device address. If the SA0 pad is connected to
the voltage supply, LSb is ‘1’ (address 0011001b) or else, if the SA0 pad is connected to
ground, the LSb value is ‘0’ (address 0011000b). This solution permits the connecting and
addressing of two different accelerometers to the same I
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
2
The I
C embedded in the LIS2DM behaves like a slave device and the following protocol
must be adhered to. After the start condition (ST) a slave address is sent, once a slave
acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7
LSb represent the actual register address while the MSb enables address auto increment. If
the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/write.
2
C lines.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write),
the master transmits to the slave with direction unchanged. Tab le 1 3 explains how the
SAD+read/write bit pattern is composed, listing all the possible configurations.
Table 13.SAD+read/write patterns
CommandSAD[6:1]SAD[0] = SA0R/WSAD+R/W
Read0011000100110001 (31h)
Write0011000000110000 (30h)
Read0011001100110011 (33h)
Write0011001000110010 (32h)
Table 14.Transfer when master is writing one byte to slave
MasterSTSAD + WSUBDATASP
SlaveSAKSAKSAK
22/47Doc ID 022536 Rev 1
LIS2DMDigital interfaces
Table 15.Transfer when master is writing multiple bytes to slave:
MasterSTSAD + WSUBDATADATASP
SlaveSAKSAKSAKSAK
Table 16.Transfer when master is receiving (reading) one byte of data from slave:
MasterSTSAD + WSUBSRSAD + RNMAKSP
SlaveSAKSAKSAKDATA
Table 17.Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+WSUBSR SAD+RMAKMAKNMAK SP
SlaveSAKSAKSAKDATADATADATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
5.2 SPI bus interface
The LIS2DM SPI is a bus slave. The SPI allows the writing and reading of the device
registers.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Doc ID 022536 Rev 123/47
Digital interfacesLIS2DM
Figure 6.Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AM10129V1
SDO
RW
MS
AD5 AD4 AD3 AD2 AD1 AD0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and returns high at the end. SPC is the serial port clock and it is controlled
by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are
respectively the serial port data input and output. Those lines are driven at the falling edge
of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiple of 8 in the case of multiple bytes read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW
bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In the latter case, the chip drives SDO at the start of bit 8.
bit 1: MS
bit. When 0, the address remains unchanged in multiple read/write commands.
When 1, the address is auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When the MS
bit is ‘0’, the address used to read/write data remains the same for every block. When the
MS
bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
24/47Doc ID 022536 Rev 1
LIS2DMDigital interfaces
CS
SPC
SDI
SDO
RW
DO7 DO6 DO5 DO4 DO3DO2 DO1DO0
AD5 AD4 AD3 AD2 AD1 AD0
MS
AM10130V1
5.2.1 SPI read
Figure 7.SPI read protocol
The SPI read command is performed with 16 clock pulses. The multiple byte read command
is performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS
bit. When 0, do not increment the address, when 1, increment the address in
multiple reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
The SPI write command is performed with 16 clock pulses. The multiple byte write
command is performed adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
DI7 DI6 DI5 DI4 DI3 DI2 DI 1 DI 0
AM10132V1
bit 1: MS
bit. When 0, do not increment the address, when 1, increment the address in
multiple writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
3-wire mode is entered by setting bit SIM (SPI serial interface mode selection) to ‘1’ in
CTRL_REG4.
DI7 D I6 DI 5 D I4 DI 3 DI2 DI 1 DI0 DI 15 D I1 4 DI 13 DI12 DI11 DI 10 DI 9 DI 8
AM10133V1
26/47Doc ID 022536 Rev 1
LIS2DMDigital interfaces
Figure 11. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
RW
AD5 AD4 AD3 AD2 AD1 AD0MS
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
DO7 DO6 DO5 DO4 DO3 DO 2 DO1 DO 0
AM10134V1
bit 1: MS
bit. When 0, do not increment the address, when 1, increment the address in
multiple reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Multiple read command is also available in 3-wire mode.
Doc ID 022536 Rev 127/47
Register mappingLIS2DM
6 Register mapping
Ta bl e 1 8 below provides a listing of the 8-bit registers embedded in the device and the
related addresses:
Table 18.Register address map
Register address
NameType
HexBinary
Reserved 00 - 06Reserved
STATUS_REG_AUXr07000 0111
Reservedr08-0BReserved
OUT_TEMP_Lr0C000 1100Output
OUT_TEMP_Hr0D000 1101Output
INT_COUNTER_REGr0E000 1110
WHO_AM_Ir0F000 1111 00110011 Dummy register
Reserved 10 - 1EReserved
TEMP_CFG_REGrw1F001 1111
CTRL_REG1rw20010 0000 00000111
DefaultComment
CTRL_REG2rw21010 0001 00000000
CTRL_REG3rw22010 0010 00000000
CTRL_REG4rw23010 0011 00000000
CTRL_REG5rw24010 0100 00000000
CTRL_REG6rw25010 0101 00000000
REFERENCErw26010 0110 00000000
STATUS_REG2r27010 0111 00000000
FIFO READ STARTr28010 1000Output
OUT_Xr29010 1001Output
Reservedr2A010 1010Output
OUT_Yr2B010 1011Output
Reservedr2C010 1100Output
OUT_Zr2D010 1101Output
FIFO_CTRL_REGrw2E010 1110 00000000
FIFO_SRC_REGr2F010 1111 00100000
INT1_CFGrw30011 0000 00000000
INT1_SOURCEr31011 0001 00000000
INT1_THSrw32011 0010 00000000
INT1_DURATIONrw33011 0011 00000000
28/47Doc ID 022536 Rev 1
LIS2DMRegister mapping
Table 18.Register address map (continued)
Register address
NameType
HexBinary
INT2_CFGrw34011 0100 00000000
INT2_SOURCEr35011 0101 00000000
INT2_THSrw36011 0110 00000000
INT2_DURATIONrw37011 0111 00000000
CLICK_CFGrw38011 1000 00000000
CLICK_SRCr39011 1001 00000000
CLICK_THSrw3A011 1010 00000000
TIME_LIMITrw3B011 1011 00000000
TIME_LATENCYrw3C011 1100 00000000
TIME_WINDOWrw3D011 1101 00000000
Act_THSrw3E011 1110 00000000
Act_DURrw3F011 1111 00000000
DefaultComment
Registers marked as Reserved or not listed in Ta bl e 1 8 above must not be changed. The
writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered-up.
Boot procedure is complete about 5 milliseconds just after powering up the device.
Doc ID 022536 Rev 129/47
Registers DescriptionLIS2DM
7 Registers Description
7.1 STATUS_AUX (07h)
Table 19.STATUS_REG_AUX register
--TOR------TDA----
Table 20.STATUS_REG_AUX description
TORTemperature Data Overrun. Default value: 0
(0: no overrun has occurred;
1: a new temperature data has overwritten the previous one)
TDATemperature new Data Available. Default value: 0
(0: a new temperature data is not yet available;
1: a new temperature data is available)
7.2 OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)
Temperature sensor data. Refer to Section 2.11: Temperature sensor for details on how to
enable and read the temperature sensor output data.
7.3 INT_COUNTER (0Eh)
Table 21.INT_COUNTER register
IC7IC6IC5IC4IC3IC2IC1IC0
7.4 WHO_AM_I (0Fh)
Table 22.WHO_AM_I register
00110011
Device identification register.
7.5 TEMP_CFG_REG (1Fh)
Table 23.TEMP_CFG_REG register
TEMP_EN1TEMP_EN0000000
30/47Doc ID 022536 Rev 1
LIS2DMRegisters Description
Table 24.TEMP_CFG_REG description
TEMP_EN[1-0]
Temperature sensor (T) enable. Default value: 00
(00: T disabled; 11: T enabled)
7.6 CTRL_REG1 (20h)
Table 25.CTRL_REG1 register
ODR3ODR2ODR1ODR01
1. This bit must be set to '1' for the correct device operation.
Table 26.CTRL_REG1 description
(1)
ZenYenXen
ODR3-0
Zen
Ye n
Xen
Data rate selection. Default value: 00
(0000: power down mode; Others: refer to Ta bl e 2 7 )
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
ODR<3:0> is used to set ODR selection. In Tab le 2 7 all frequencies resulting in a
combination of ODR<3:0>
Write operation at this address is possible only after system boot.
Table 49.Interrupt mode
AOI6DInterrupt mode
00OR combination of interrupt events
016 direction movement recognition
10AND combination of interrupt events
116 direction position recognition
Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves
from unknown zone to known zone. The interrupt signal stays for a duration ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when orientation is inside a
known zone. The interrupt signal stays until orientation is inside the zone.
7.21 INT1_SRC (31h)
Table 50.INT1_SRC register
0 IA ZHZLYHYLXHXL
Table 51.INT1_SRC description
IA
ZH
ZL
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
Doc ID 022536 Rev 137/47
Registers DescriptionLIS2DM
Table 51.INT1_SRC description
YH
YL
XH
XL
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Interrupt 1 source register. Read only register.
Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refreshment of data in the INT1_SRC register if the latched option was
chosen.
6D6 direction detection function enabled. Default value: 0. Refer to Tab l e 58
ZHIE
ZLIE
YHIE
AND/OR combination of interrupt events. Default value: 0.
(See Ta b le 5 8 below)
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Y low event. Default value: 0
YLIE
XHIE
XLIE
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
The content of this register is loaded at boot.
Write operation at this address is possible only after system boot.
Table 58.Interrupt mode
AOI6DInterrupt mode
00OR combination of interrupt events
016 direction movement recognition
10AND combination of interrupt events
116 direction position recognition
Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
Doc ID 022536 Rev 139/47
Registers DescriptionLIS2DM
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves
from an unknown zone to a known zone. The interrupt signal stays for a duration ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when orientation is inside a
known zone. The interrupt signal stays until orientation is inside the zone.
7.25 INT2_SRC (35h)
Table 59.INT2_SRC register
0 IA ZHZLYHYLXHXL
Table 60.INT2_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
ZL
YH
YL
XH
XL
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
X Low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Interrupt 2 source register. Read only register.
Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT 2
pin) and allows the refreshment of data in the INT2_SRC register if the latched option was
chosen.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 81.LGA-14 2x2x1 mechanical dimensions
Ref.Min.Typ.Max.
A11
A20.785
A30.200
D11.8502.0002.150
E11.8502.0002.150
L10.900
L21.250
N10.350
T10.275
T20.200
P10.850
P20.850
d0.150
M0.100
K0.050
Figure 12. LGA-14 2x2x1 mechanical drawing
Doc ID 022536 Rev 145/47
8224765_A
Revision historyLIS2DM
9 Revision history
Table 82.Document revision history
DateRevisionChanges
25-Nov-20111Initial release.
46/47Doc ID 022536 Rev 1
LIS2DM
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.