Ultra low drop BICMOS voltage regulator
Feature summary
■ 3A Guaranteed output current
■ Ultra low dropout voltage (200mV typ. @ 3A
load, 40mV typ. @600mA load)
■ Very low quiescent current (1.2mA typ. @ 3A
load, 1µA max @ 25°C in off mode)
■ Logic-controlled electronic shutdown
■ Current and thermal internal limit
■ ±1.5% Output voltage tolerance @ 25°C
■ Fixed and ADJ output voltages: 1.22V, 1.8V,
2.5V, 3.3V, ADJ. (*see order code)
■ Temperature range: -40 to 125°C
■ Fast dynamic response to line and load
changes
■ Stable with ceramic capacitor (see paragraph
7.1, 7.2, 7.3)
■ Available in PPAK and DPAK
Typical application
■ Microprocessor power supply
■ DSPs power supply
■ Post regulators for switchin suppliers
■ High efficiency linear regulator
LD39300
PPAK
Description
The LD39300 is a fast ultra low drop linear
regulator which operates from 2.5V to 6V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
DPAK
Order codes
Part numbers
Output voltage
DPAK PPAK
LD39300DT12-R 1.22V
LD39300DT18-R LD39300PT18-R 1.8V
LD39300DT25-R LD39300PT25-R 2.5V
LD39300DT33-R LD39300PT33-R 3.3V
LD39300PT-R ADJ From 1.22 to 5.0V
January 2007 Rev. 1 1/17
www.st.com
17
LD39300
Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
LD39300 Diagram
1 Diagram
Figure 1. Block diagram
(*) Not present on ADJ Versions
3/17
Pin configuration LD39300
2 Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK)
PPAK
Table 1. Pin description
Pln N°
Symbol Note
PPAK DPAK
5
V
21 V
43 V
1V
3 2 GND Common ground
/N.C. For fixed versions: Not Connected on PPAK
SENSE
ADJ For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V
LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a distance of not
I
more than 0.5’’ from input pin.
O
INH
LDO Output Voltage pins, with minimum CO=4.7µF needed for stability (also refer
vs. ESR stability chart)
to C
O
Inhibit Input Voltage: ON MODE when V
(Do not leave floating, not internally pulled down/up)
DPAK
≥ 2V, OFF MODE when V
INH
INH
≤ 0.3V
4/17
LD39300 Typical application circuits
3 Typical application circuits
(CI and CO Capacitors must be placed as close as possible to the IC pins)
Figure 3. LD39300 Fixed version with inhibit
1 Inhibit Pin is not internally pulled down/up then it must not be left floating. Disable the device
when connected to GND or to a positive voltage less than 0.3V
Figure 4. LD39300 Adjustable version
VO = V
(1 + R1/R2)
REF
2 Set R2 as close as possible to 4.7K
Ω.
5/17
Typical application circuits LD39300
Figure 5. LD39300 DPAK
Figure 6. Timing diagram
6/17
LD39300 Maximum ratings
4 Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
DC Input voltage -0.3 to 6.5 V
INHIBIT Input voltage -0.3 to VI +0.3 (6.5V Max) V
DC Output voltage -0.3 to VI +0.3 (6.5V Max) V
ADJ Pin voltage -0.3 to VI +0.3 (6.5V Max) V
Output current Internally Limited mA
Power dissipation Internally Limited mW
Storage temperature range -50 to 150 °C
Operating junction temperature range -40 to 125 °C
V
V
T
V
P
STG
T
V
INH
O
ADJ
I
O
D
OP
I
Note: Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. All values are referred to
GND.
Table 3. Thermal Data
Symbol Parameter PPAK DPAK Unit
R
thJA
R
thJC
Thermal resistance junction-ambient 100 100 °C/W
Thermal resistance junction-case 8 8 °C/W
7/17
Electrical characteristics LD39300
5 Electrical characteristics
Table 4. Electrical characteristics
(T
= 25°C, VI = VO+1V, CI = 1µF, CO = 4.7µF, I
J
specified)
Symbol Parameter Parameter Min. Typ. Max. Unit
LOAD
= 10mA, V
= 2V, unless otherwise
INH
Operating input voltage 2.5 6 V
I
Output voltage tolerance
Reference voltage 1.22 V
Output voltage LINE
O
regulation
Output voltage LOAD
LOAD
regulation
Dropout voltage (VI - VO)
V
V
∆V
∆VO/∆I
V
DROP
V
O
REF
Quiescent current:
ON MODE
I
Q
Quiescent current:
OFF MODE
Short Circuit Protection
I
SC
Short circuit protection RL = 0 6 A
Inhibit Input
VI = VO+1V, I
= 10mA to 3A -1.5 1.5
LOAD
VI = VO+1V to 6V,
I
= 10mA to 3A
LOAD
= -40 to 125°C
T
J
= VO+1V to 6V 0.04 %
V
I
V
= VO+1V to 6V, TJ = -40 to 125°C 0.1 0.2 %
I
= 10mA to 3A 0.06
I
LOAD
I
= 10mA to 3A,
LOAD
= -40 to 125°C
T
J
= 600mA, TJ=-40 to 125°C 40 80
I
LOAD
I
= 3A, TJ = -40 to 125°C 200 400
LOAD
I
= 10mA to 3A, V
LOAD
= -40 to 125°C
T
J
= 0.3V 1
V
INH
= 0.3V, TJ = -40 to 125°C 5
V
INH
INH
= 2V
-3 3
0.2 0.4
1.2 2.5 mA
% of
V
O(NOM)
%/A
mV
µA
V
T
D-OFF
T
D-ON
I
INH
INH
Inhibit threshold HIGH 2
Current limit I
Current limit I
Inhibit input current
AC Parameters
SVR Supply voltage rejection
Inhibit threshold LOW
e
N
Output noise voltage
Thermal shutdown OFF 170
T
SHDN
1. Guaranteed by design
Hysteresis 10
8/17
(1)
V
= 2.5 to 6V OFF
I
= -40 to 125°C
T
J
= 3A, VO = 3.3V 20
LOAD
= 3A, VO = 3.3V 20
LOAD
VI = 6V, V
= 4.5 ± 1V,
V
I
V
= 3.3V,
O
I
LOAD
= 10Hz to 100kHz,
B
W
C
= 4.7µF, VO = 2.5V
O
= 0 to 6V ±0.1 ±1µA
INH
f = 120Hz 65
= 10mA,
f = 1kHz 55
0.3
100 µV
V
µs
dB
RMS
°C
LD39300 Typical performance characteristics
6 Typical performance characteristics
(TJ = 25°C, VI = VO+1V, CI = 1µF, CO = 4.7µF, I
LOAD
= 10mA, V
= VI, unless otherwise
INH
specified)
Figure 7. Output voltage vs temperature Figure 8. Dropout voltage vs temperature
Figure 9. Dropout voltage vs output current Figure 10. Quiescent current vs temperature
Figure 11. Quiescent current vs temperature Figure 12. Short circuit current vs temperature
9/17
Typical performance characteristics LD39300
Figure 13. Output voltage vs input voltage Figure 14. Stability region vs CO & ESR
Figure 15. Stability region vs CO & ESR (low
ESR zoom area)
Figure 16. Load transient (fall time)
VI = 5V, VO = 3.3V, IO = 10mA to 3A, CI = 1µF, CO = 4.7µF
Figure 17. Load transient (rise time) Figure 18. Line transient
VI = 5V, VO = 3.3V, IO = 10mA to 3A, CI = 1µF, CO = 4.7µF
10/17
VI = 3.5V to 5.5V, VO = 3.3V, I
= 10mA, CO = 4.7µF
LOAD
LD39300 Application notes
7 Application notes
7.1 External capacitors
The LD39300 requires external capacitors for regulator stability. These capacitors must be
selected to meet the requirements of minimum capacitance and equivalent series resistance
(see
Figure 14. Figure 15.
the relative pins and connected directly to the input/output ground pins using traces which
have no other currents flowing through them. Any good quality of Ceramic or Electrolytic
capacitors can be used.
7.2 Input capacitor
An input capacitor whose minimum value is 1µF is required with the LD39300 (amount of
capacitance can be increased without limit). This capacitor must be located a distance of not
more than 1cm from the input pin of the device and returned to a clean analog ground. Any
good quality ceramic, tantalum or film capacitors can be used for this capacitor.
). The input/output capacitors must be located less than 1cm from
7.3 Output capacitor
It is possible to use Ceramic or Tantalum capacitors but the output capacitor must meet the
requirement for minimum amount of capacitance and E.S.R. (equivalent series resistance)
value. A minimum capacitance of 4.7µF is a good choice to guarantee the stability of the
regulator. Anyway, other C
showing the allowable ESR range as a function of the output capacitance. This curve
represents the stability region over the full temperature and I
values can be used according to the (
O
7.4 Thermal note
The output capacitor must maintain its ESR in the stable region over the full operating
temperature range to assure stability. Also, capacitors tolerance and variation with
temperature must be kept in consideration in order to assure the minimum amount of
capacitance at all times.
7.5 Inhibit input operation
The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically
reducing the current consumption down to less than 1µA. When the inhibit feature is not
used, this pin must be tied to V
proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section (V
The inhibit pin must not be left floating because it is not internally pulled down/up.
to keep the regulator output ON at all times. To assure
I
Figure 14. Figure 15.
range.
O
IH VIL
)
).
11/17
Package mechanical data LD39300
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
12/17
LD39300 Package mechanical data
PPAK MECHANICAL DATA
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.4 0.6 0.015 0.023
B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
D1 5.1 0.201
E 6.4 6.6 0.252 0.260
E1 4.7 0.185
e 1.27 0.050
G 4.9 5.25 0.193 0.206
G1 2.38 2.7 0.093 0.106
H 9.35 10.1 0.368 0.397
L2 0.8 1 0.031
L4 0.6 1 0.023 0.039
L5 1
L6 2.8 0.110
mm. inch
0.039
0.039
0078180-E
13/17
Package mechanical data LD39300
DPAK MECHANICAL DATA
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035
b4 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
D1 5.1 0.200
E 6.4 6.6 0.252 0.260
E1 4.7 0.185
e 2.28 0.090
e1 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L 1 0.039
(L1)
L2 0.8 0.031
L4 0.6 1 0.023 0.039
mm. inch
2.8 0.110
14/17
0068772-F
LD39300 Package mechanical data
Tape & Reel DPAK-PPAK MECHANICAL DATA
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
C 12.8 13.0 13.2 0.504 0.512 0.519
D 20.2 0.795
N 60 2.362
T 22.4 0.882
Ao 6.80 6.90 7.00 0.268 0.272 0.2.76
Bo 10.40 10.50 10.60 0.409 0.413 0.417
Ko 2.55 2.65 2.75 0.100 0.104 0.105
Po 3.9 4.0 4.1 0.153 0.157 0.161
P 7.9 8.0 8.1 0.311 0.315 0.319
mm. inch
15/17
Revision history LD39300
9 Revision history
Table 5. Revision history
Date Revision Changes
26-Jan-2007 1 Initial release.
16/17
LD39300
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