ST LD39300 User Manual
Ultra low drop BICMOS voltage regulator
Feature summary
■ 3A Guaranteed output current
■ Ultra low dropout voltage (200mV typ. @ 3A
load, 40mV typ. @600mA load)
■ Very low quiescent current (1.2mA typ. @ 3A
load, 1µA max @ 25°C in off mode)
■ Logic-controlled electronic shutdown
■ Current and thermal internal limit
■ ±1.5% Output voltage tolerance @ 25°C
■ Fixed and ADJ output voltages: 1.22V, 1.8V,
2.5V, 3.3V, ADJ. (*see order code)
■ Temperature range: -40 to 125°C
■ Fast dynamic response to line and load
changes
■ Stable with ceramic capacitor (see paragraph
7.1, 7.2, 7.3)
■ Available in PPAK and DPAK
Typical application
■ Microprocessor power supply
■ DSPs power supply
■ Post regulators for switchin suppliers
■ High efficiency linear regulator
LD39300
PPAK
Description
The LD39300 is a fast ultra low drop linear
regulator which operates from 2.5V to 6V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
DPAK
Order codes
Part numbers
Output voltage
DPAK PPAK
LD39300DT12-R 1.22V
LD39300DT18-R LD39300PT18-R 1.8V
LD39300DT25-R LD39300PT25-R 2.5V
LD39300DT33-R LD39300PT33-R 3.3V
LD39300PT-R ADJ From 1.22 to 5.0V
January 2007 Rev. 1 1/17
www.st.com
17
LD39300
Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
LD39300 Diagram
1 Diagram
Figure 1. Block diagram
(*) Not present on ADJ Versions
3/17
Pin configuration LD39300
2 Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK)
PPAK
Table 1. Pin description
Pln N°
Symbol Note
PPAK DPAK
5
V
21 V
43 V
1V
3 2 GND Common ground
/N.C. For fixed versions: Not Connected on PPAK
SENSE
ADJ For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V
LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a distance of not
I
more than 0.5’’ from input pin.
O
INH
LDO Output Voltage pins, with minimum CO=4.7µF needed for stability (also refer
vs. ESR stability chart)
to C
O
Inhibit Input Voltage: ON MODE when V
(Do not leave floating, not internally pulled down/up)
DPAK
≥ 2V, OFF MODE when V
INH
INH
≤ 0.3V
4/17
LD39300 Typical application circuits
3 Typical application circuits
(CI and CO Capacitors must be placed as close as possible to the IC pins)
Figure 3. LD39300 Fixed version with inhibit
1 Inhibit Pin is not internally pulled down/up then it must not be left floating. Disable the device
when connected to GND or to a positive voltage less than 0.3V
Figure 4. LD39300 Adjustable version
VO = V
(1 + R1/R2)
REF
2 Set R2 as close as possible to 4.7K
Ω.
5/17
Typical application circuits LD39300
Figure 5. LD39300 DPAK
Figure 6. Timing diagram
6/17
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