The LD1117 is a LOW DROP Voltage Regulator
able to provide up to 800mA of Output Current,
available even in adjustable version (Vref=1.25V).
Concerning fixed versions, are offered the
following Output Voltages: 1.2V,1.8V,2.5V,2.85V,
3.0V 3.3V and 5.0V. The 2.85V t yp e is ideal for
SCSI-2 lines active termination. The device is
supplied in: SOT-223, DPAK, SO-8 and TO-220.
The SOT-223 and DPAK surfa ce mount packages
optimize the thermal characteristics even offering
a relevant space saving effect. High efficiency is
assured by NPN pass transistor. In fact in this
TO-220
SOT-223
DPAK
SO-8
case, unlike than PNP one, the Quiescent Current
flows mostly into the load. Only a very comm on
10µF minimum capacitor is needed for stability.
On chip trimming a llows the regulator to reach a
very tight output voltage tolerance, within ± 1% at
25°C. The ADJUSTABLE LD1117 is pin to pin
compatible with the other standard. Adjustable
voltage regulators maintaining the better
performances in terms of Drop and Tolerance.
Figure 1: Block Diagram
Rev. 19
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LD1117 SERIES
Figure 2: Pin Connec t ion (top view)
SOT-223SO-8
DPAK
NOTE: The T AB is connect ed to the V
OUT
.
TO-220
Table 1: Order Codes
SOT-223SO-8DPAKDPAK (T&R)TO-220
LD1117S12TRLD1117D12TR (*)LD1117DT12 (*)LD1117DT12TRLD1117V12 (*)1.2 V
LD1117S12CTR (*) LD1117D12CTR (*) LD1117DT12C (*)LD1117V12C (*)1.2 V
LD1117S1 8TRLD 1117D18TR (*)LD1117D T18LD1117DT18TRLD1117V181.8 V
LD1117S18CTR (*) LD1117D18CTR (*)LD1117DT18CLD1117DT18CTR LD1117V18C (*)1.8 V
LD1117S2 5TRLD 1117D25TR (*)LD1117D T25LD1117DT25TRLD1117V252.5 V
LD1117S25CTRLD1117D25CTR (*)LD1117DT25CLD1117DT25CTRLD1117V25C2.5 V
LD1117S2 8TRLD 1117D28TR (*)LD1117DT28 TR2.85 V
LD1117S3 0TRLD 1117D30TR (*)3 V
LD1117S33TRLD1117D33TRLD1117DT33LD1117DT33TRLD1117V333.3 V
LD1117S33CTRLD1117D33CTRLD1117DT33CLD1117DT33CTRLD1117V33C3.3 V
LD1117S50TRLD1117D50TRLD1117DT50LD1117DT50TRLD1117V505 V
LD1117S50CTRLD1117D50CTR (*)LD1117DT50CLD1117DT50CTR5 V
LD1117STRLD1117DTR (*)LD1117DTLD1117DTTRLD1117VADJ FROM
LD1117SC-RLD1117DC-R (*)LD1117DTC (*)LD1117DTC-RLD1117VC (*)ADJ FROM
OUTPUT
VOLTAGE
1.25 TO 15V
1.25 TO 15V
(*) Avai l abl e on request
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LD1117 SERIES
Table 2: Absolute Maximum Ratings
SymbolParameterValueUnit
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not impl i ed. Over the abov e suggested M a x Power Dis sipation a Short Circuit could defini ti v e l y damage the device.
Table 3: Thermal Data
SymbolParameterSOT-223SO-8DPAKTO-220Unit
R
thj-case
R
thj-amb
Figure 3: Applica t i on Circuit (FOR 1.2 V)
DC Input Voltage
IN
Power Dissipation
tot
Storage Temperature Range
stg
Operating Junction Temperature Rangefor C Version-40 to +150°C
op
15V
12W
-40 to +150°C
for standard Version0 to +150°C
Thermal Resistance Junction-case
152083°C/W
Thermal Resistance Junction-ambient
50°C/W
Figure 4: Applica t i on Circuit (FOR OTHER FIXED OUTPUT VOLTAGES)
3/27
LD1117 SERIES
Table 4: Electrical Characteristics Of LD1117#12 (refer to the test circuits, TJ = 0 to 125°C,
= 10 µF, R = 120 Ω between GND and OUT pins, unless otherwise specified)
Output VoltageIO = 0 to 800 mAVin = 6.5 to 15 V4.85.2V
O
∆V
∆V
∆V
∆V
SVRSupply Voltage RejectionI
Line RegulationVin = 6.5 to 15 VIO = 0 mA150mV
O
Load RegulationVin = 6.5 VIO = 0 to 800 mA150mV
O
Temperature Stability0.5%
O
Long Term Stability1000 hrs, TJ = 125°C0.3%
O
Operating Input VoltageIO = 100 mA15V
V
in
Quiescent CurrentVin ≤ 15 V510mA
I
d
Output CurrentVin = 10 V TJ = 25°C8009501300mA
I
O
eNOutput Noise VoltageB =10Hz to 10KHzT
= 40 mA f = 120HzTJ = 25°C
O
V
= 8 VV
in
V
Dropout VoltageIO = 100 mA TJ = 0 to 125°C11.1V
d
= 500 mA TJ = 0 to 125°C1.051.15
I
O
= 800 mA TJ = 0 to 125°C1.101.2
I
O
Dropout VoltageIO = 100 mA1.1V
V
d
I
= 500 mA1.2
O
= 800 mA1.3
I
O
Thermal RegulationT
= 25°C 30ms Pulse0.010.1%/W
a
ripple
= 25°C100µV
J
6075dB
= 1 V
PP
13/27
LD1117 SERIES
Table 18: Electrical Characteristics Of LD1117C (ADJUSTABLE) (refer to the test circuits,
T
= -40 to 125°C, CO = 10 µF unless otherwise specified)
J
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
Reference VoltageVin - VO = 2 V IO = 10 mA TJ =
ref
25°C
Reference VoltageIO = 10 to 800 mAVin - VO= 1.4 to 10 V1.21.3V
V
ref
1.2251.251.275V
∆V
∆V
∆V
∆V
∆I
I
O(min)
Line RegulationVin - VO = 1.5 to 13.75 VIO = 10 mA1%
O
Load RegulationVin - VO = 3 VIO = 10 to 800 mA1%
O
Temperature Stability0.5%
O
Long Term Stability1000 hrs, TJ = 125°C0.3%
O
Operating Input Voltage15V
V
in
Adjustment Pin CurrentVin ≤ 15 V60120µA
I
adj
Adjustment Pin Current
adj
Change
Minimum Load CurrentVin = 15 V25mA
I
Output CurrentVin - VO = 5 VTJ = 25°C8009501300mA
O
eNOutput Noise (%V
)B =10Hz to 10KHzTJ = 25°C0.003%
O
SVRSupply Voltage RejectionI
V
Dropout VoltageIO = 100 mATJ = 0 to 125°C11.1V
d
Dropout VoltageIO = 100 mA1.1V
V
d
Thermal RegulationT
Vin - VO = 1.4 to 10 V
I
= 10 to 800 mA
O
= 40 mA f = 120HzTJ = 25°C
O
V
- VO = 3 VV
in
= 500 mATJ = 0 to 125°C1.051.15
I
O
I
= 800 mATJ = 0 to 125°C1.101.2
O
= 500 mA1.2
I
O
= 800 mA1.3
I
O
= 25°C 30ms Pulse0.010.1%/W
a
ripple
= 1 V
PP
6075dB
110µA
TYPICAL APPLICATIONS
Figure 5: Negativ e Supply
14/27
Figure 6: Active Terminator for SCSI-2 BUS
Figure 7: Circuit for Increasing Output Voltage
LD1117 SERIES
Figure 8: Voltage Regulator With Reference
15/27
LD1117 SERIES
Figure 9: Battery Backed-up Regulated Supply
16/27
Figure 10: Post-Regulated Dual Supply
LD1117 SERIES
LD1117 ADJUSTABLE: APPLICATION NOTE
The LD1117 ADJUSTABLE has a thermal
stabilized 1.25±0.012V reference voltage between
the OUT and ADJ pins. I
max.) and ∆I
is 1µA typ. (5µA max.).
ADJ
is 60µA ty p. (120µA
ADJ
R1 is normally fixed to 120Ω. From figure 11 we
obtain:
V
+V
OUT
REF
= V
/R1) = V
REF
+ R2 (I
REF
+IR1) = V
ADJ
(1 + R2 / R1) + R2 x I
REF
+ R2 (I
ADJ
ADJ
.
In normal application R2 value is in the range of
few kohm, so the R2 x I
considered in the V
product could not be
DJ
calculation; then the
OUT
above expres s ion becom es:
V
OUT
= V
(1 + R2 / R1).
REF
In order to have the better load regulation it is
important to realize a good Kelvin connection of
R1 and R2 resistors. In particular R1 con nection
must be realized very close to OUT and A DJ pin,
while R2 ground connection must be placed as
near as poss ible to the ne gative Loa d pin. Rippl e
rejection can be improv ed by introducing a 10µF
electrolytic capacitor placed in parallel to the R2
resistor (see Fig. 12).
17/27
LD1117 SERIES
Figure 11: Adjustable Output Voltage Application
Figu re 12: Adjust a b l e O u t put Vo lt a ge Applica tion with improv e d R ipple R e jection
22-Sep-200415.0Add new Part Number #12C; Typing Error: Note on table 2.
25-Oct-200416.0
18-Jul-200517.0The DPAK Mechanical Data has been updated.
25-Nov-200518.0The TO220FM Package has been removed.
14-Dec-200519.0
Add V
The T
Reference Voltage on Table 12.
ref
on Table 2 has been updated.
op
26/27
LD1117 SERIES
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