ST L99PD08 User Manual

L99PD08

SPI control diagnosis interface device for VIPower™ M0-5 and M0-5E high side drivers

Features

■8 channel VIPower driver and diagnostics device

■Supports analog and digital VIPower status readback

■8 independent PWM channels

■Selectable PWM base clock (2 external, one internal)

■Programmable PWM turn on phase shift

■Programmable diagnostic thresholds (analog VIPower)

■Programmable over temperature latch off for enhanced HSD short circuit reliability

■Limp home safety mode

■ST-SPI interface protocol for data communication

■External enable pin for low power mode

■Detailed and filtered diagnostic for each channel

■Direct multiplexed VIPower status / current sense feedback

■Supply voltage 3.3 or 5.0 V (two pins)

Applications

■ Exterior and interior automotive light system

LQFP32

Description

The device has integrated several functions which save job load of the microcontroller and save necessary connections to the microcontroller. It’s possible to connect analog and digital high side drivers (HSD) to the device and control them via SPI interface. A synchronous detailed diagnostics feature is integrated.

The device has 8 outputs to the HSD with the possibility to be driven either by steady state ON/OFF mode or by PWM. Two clock inputs used as base frequency to generate the PWM signal internally are provided. The outputs are fully independent and can also be driven with phase shift to improve characteristics of power net during the inrush phase. The device has 8 current sense (CS)/status (ST) pins connected to the HSD to run diagnostics. The index of ST/CS pin corresponds to the input connected to the same HSD channel (ST0/CS0 with OUT0, ST1/CS1 with OUT1 …).

Table 1.	Summary device
			Order codes
	Package
		Tube		Tape and reel
	LQFP32	L99PD08		L99PD08TR
April 2010		Doc ID 15872 Rev 3	1/41
				www.st.com	1

Contents	L99PD08

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
2	Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	2.1	ST-SPI: SCK, SDI, SDO, CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.2	CLK_IN0, CLK_IN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.3	LHOMEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.4	Output 0 to 7 (OUT0 … OUT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.5	Status/current sense inputs (ST0/CS0 … ST7/CS7) . . . . . . . . . . . . . . . . .	9
	2.6	Multiplexed status/current sense output (MUX_ST/CS) . . . . . . . . . . . . . . .	9
	2.7	VDDIO, VCORE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9

2.7.1 5.0 volt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7.2 3.3 volt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

	2.8	GND (2 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	2.9	Faultn .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.10	SYNC . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.11	EN . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
3	Device mode		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
4	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			14
	4.1	ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	4.2	Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			15
6	SPI . .	. . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	6.1	SPI timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	6.2	Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
		6.2.1	Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
		6.2.2	Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
		6.2.3	Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
		6.2.4	Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25

6.3 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/41	Doc ID 15872 Rev 3

L99PD08				Contents
		6.3.1	General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 25
		6.3.2	Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 25
		6.3.3	Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 26
		6.3.4	Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 26
	6.4	SPI – control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 28
7	Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . 37
	7.1	ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 37
	7.2	LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 37
	7.3	LQFP32 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 38
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . 40

Doc ID 15872 Rev 3	3/41

List of tables	L99PD08

List of tables

Table 1. Summary device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Device modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. Undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. EN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10. Output switches/fault pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Current sense/status inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. MUX_ST/CS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 13. Current MUX_ST/CS ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 14. Current sense diagnostic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. LHOMEN and SYNC pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 18. CSN timeout/CLK_INx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 19. Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 20. Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 21. Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 22. Global status byte: description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 23. RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 24. ROM memory map (access with OC0 and OC1 set to ‘1’) . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 25. Control register, hex00 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 26. ON_OFF register, hex01 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 27. DEV_TYPE register, hex02 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 28. PWM_EN register, hex03 (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 29. CLK_SEL register, hex04 (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 30. ASDT register, hex05 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 31. DET_DIAG register, hex06 (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 32. BLK_TIME1 register, hex07 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 33. BLK_TIME2 register, hex08 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 34. TD_SENSE register, hex09 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 35. CFR register, hex0A (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 36. OLOVL_TH_1 register, hex0B (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 37. OLOVL_TH_2 register, hex0C (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 38. DUTY_CH 0 – DUTY_CH 7 Registers, hex10 – hex17 (RW-Type) . . . . . . . . . . . . . . . . . . 34 Table 39. PHASE_CH 0 - PHASE_CH7 Registers, hex18 – hex1F (RW-Type) . . . . . . . . . . . . . . . . 34 Table 40. CHANNEL_FB Registers, hex2E (R-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 41. AUX_STATUS Registers, hex2F (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 42. OT_FAULT Registers, hex30 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 43. OL_FAULT Registers, hex31 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 44. STK_FAULT Registers, hex32 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 45. OVL_FAULT Registers, hex33 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 46. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 47. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4/41	Doc ID 15872 Rev 3

L99PD08	List of figures

List of figures

Figure 1. Application example block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pinning of device in LQFP-32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Example for SYNC pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Device state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. CS pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. ST pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. MUX_ST/CS ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. SPI frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. SDO status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. LQFP32 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 12. LQFP32 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 13. LQFP32 tray shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 15872 Rev 3	5/41

Block diagram	L99PD08

1Block diagram

Figure 1. Application example block diagram

Vbat
					LHOMEN
Vreg 5V					10k			Vbat_SWITCH
						4k7	4k7
		VDDIO		diagnostics				10k
				3	ST0/CS0				IN1
VDD								4k7
		VCORE3	Vreg 3.3V
					OUT0			4k7	IN2	OUT1
										OUT2
				CHANNEL0		100			CS1	VIP
	MUX_ST/CS				ST1/CS1 100				CS2
	1k			.	OUT1
		2k7
	VDD			. .	. .				VNxxxAx
										.
	10k
	1k	FAULT		.	.					.
	1k	CLK_IN0		.	.			Vbat_SWITCH		.
			CONTROL
	1k	CLK_IN1		.	.					.
	1k	EN	LOGIC					10k
Microcontroller				.
	1k	SYNC			ST6/CS6				IN1
								4k7
		10k			OUT6			4k7	IN2	OUT1
										OUT2
						VDD		VDD
									ST1	VIP
						4k7		4k7
	1k	CSN			ST7/CS7 4k7			4k7	ST2
	1k	SCK			OUT7
			SPI
	1k	SDI
	1k	SDO		CHANNEL7					VNxxx
				GND

6/41	Doc ID 15872 Rev 3

L99PD08	Pin definitions and functions

2Pin definitions and functions

Table 2.	Pin definition and function
Pin	Symbol	Function
1	CLK_IN0	PWM clock input 0
2	CLK_IN1	PWM clock input 1
3, 13	GND	Common ground
4	VDDIO	I/O and 3.3 V voltage regulator supply (3.3 V or 5 V)
5	FAULTN	Failure on HSD or communication error
6	SYNC	Output of OUT0-OUT7 signals, selected by control register
7	MUX_ST/CS	Output from ST/CS multiplexer
8	VCORE3	Core supply voltage (3.3 V only)
9	SCK	ST-SPI – serial clock input
10	SDI	ST-SPI – serial data input
11	SDO	ST-SPI – serial data output
12	CSN	ST-SPI – chip select input
14	EN	Enable pin
15	N.C.	Not connected
16	LHOMEN	Active mode pull-up supply – limp home
17	ST7/CS7	Input from HSD status / current sense pin
18	OUT7	Output to High side driver – channel 7
19	ST6/CS6	Input from HSD status / current Sense pin
20	OUT6	Output to high side driver – channel 6
21	ST5/CS5	Input from HSD status / current sense pin
22	OUT5	Output to high side driver – channel 5
23	ST4/CS4	Input from HSD status / current sense pin
24	OUT4	Output to high side driver – channel 4
25	ST3/CS3	Input from HSD status / current sense pin
26	OUT3	Output to high side driver – channel 3
27	ST2/CS2	Input from HSD status / current sense pin
28	OUT2	Output to high side driver – channel 2
29	ST1/CS1	Input from HSD status / current sense pin
30	OUT1	Output to high side driver – channel 1
31	ST0/CS0	Input from HSD status / current sense pin
32	OUT0	Output to high side driver – channel 0

Doc ID 15872 Rev 3	7/41

Pin definitions and functions	L99PD08

Figure 2. Pinning of device in LQFP-32 package

OUT0	ST0/CS0	OUT1	ST1/CS1	OUT2	ST2/CS2	OUT3	ST3/CS3
32	31	30	29	28	27	26	25

	CLK_IN0	1		24	OUT4
	CLK_IN1	2		23	ST4/CS4
	GND	3	L99PD08	22	OUT5
	VDDIO	4		21	ST5/CS5
	FAULTN	5	LQFP32	20	OUT6
	SYNC	6		19	ST6/CS6
	MUX_ST/CS	7		18	OUT7
	VCORE3	8		17	ST7/CS7

9	10	11	12	13	14	15	16
SCK	SDI	SDO	CSN	GND	EN	N.C.	LHOMEN

2.1ST-SPI: SCK, SDI, SDO, CSN

A 16-bit SPI interface is used to control the device. The communication interface is activated by pulling CSN to low. The SDI is captured with the positive edge of SCK and the data is shifted out at SDO at the negative edge of SCK. A CSN timeout is implemented.

2.2CLK_IN0, CLK_IN1

These pins are used to run the two internal PWM base frequency counters to generate the output PWM.

Each channel can be programmed as steady state ON/OFF output or a PWM output through the PWM_EN (Addr: hex03) SPI register. During PWM mode, the PWM signal can be generated either from CLK_IN0 or CLK_IN1 as base counter, selected through the SPI register CLK_SEL (Addr: hex04). Phase shift and duty cycle are set through the dedicated registers DUTY_CHx (Addr: hex10 – hex17) and PHASE_CHx (Addr: hex18 – hex1F).

8/41	Doc ID 15872 Rev 3

L99PD08	Pin definitions and functions

The output PWM period is a factor of 256 of the frequency applied on CLK_INx signal.

If the external clock signal is not available or is below fPWM(min) , the device will fallback to an internal PWM frequency generator fPWM of approximately 122Hz periode.

2.3LHOMEN

This pin allows connecting the output pull-down resistor for LIMP HOME mode. This pin is pulled to VDDIO in normal mode and is pulled low in case of failure (RESET and FAIL SAVE mode).

If power supply VDDIO is not connected, LHOMEN becomes weak low (LIMP HOME mode).

2.4Output 0 to 7 (OUT0 … OUT7)

True open drain outputs are used to drive the High Side Driver inputs. These lines must have a pull-up resistor connected either to a separate supply or LHOMEN signal if LIMP HOME is supported.

These outputs are high impedance during RESET, Fail Safe modes and during SW Reset.

2.5Status/current sense inputs (ST0/CS0 … ST7/CS7)

Those inputs are used to take the status or current sense information from DIGITAL or ANALOG HSD and provide information to the internal diagnosis. Every output has to correspond to the same HSD channel like the ST/CS input (OUT0 with ST0/CS0, OUT1 with ST1/CS1, …). Status of digital channels have to have an external pull-up resistor

(4.7 kOhm) and a series protection resistor of 4.7 kOhm to STx/CSx, current sense signals of analog channels have to be connected to STx/CSx pins through a 100 Ohm reverse battery protection resistor.

The HSD type which is connected to the device (digital or analog) must be selected through the register DEV_TYPE (Addr: hex02).

2.6Multiplexed status/current sense output (MUX_ST/CS)

The MUX_ST/CS Pin reflects the status or current sense information corresponding to the channel selected in the control register bits MUX_EN, MUX_A, B, C (Addr: hex00; Bit 7-4).

This pin delivers up to 3 mA at 2.7 V. It is recommended to use a 1.6k to 2.7kOhm external resistor to ground for the maximum dynamic range. The best choice for the external resistor depends on the Rdson class of the analog current sense HSD and of the loads.

If the multiplexer is disabled the MUX_ST/CS pin is in tristate condition.

2.7VDDIO, VCORE3

The digital voltage supply of the device is internally limited to 3.3 V. In order to support also the 5 V supply voltages a linear internal voltage regulator can be used.

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Pin definitions and functions	L99PD08

2.7.15.0 volt operation

The voltage regulator input is available at the terminal VDDIO, the output is available at VCORE3.

In the 5V operation mode it is recommended to attach a decoupling capacitor on VCORE3 to stabilize the regulator. Due to the limited current capability of this regulator no external loads should be attached on VCORE3.

2.7.23.3 volt operation

In applications with 3.3 V supply only, both, VDDIO and VCORE3 have to be attached (shorted) to the local supply.

If the internal supply (VCORE3) is below the threshold of the internal power-and-reset circuit, the device is in standby mode. The device is in low power consumption and no SPI communications are possible.

2.8GND (2 pins)

These two pins are the GND voltage supply of the device and have to be connected externally.

2.9Faultn

This active low pin indicates any internal error reported by the device. This can be a High Side Driver failure or a communication error. In fault condition this open drain output is set to low, while during reset it is left open. This pin has to be connected to a pull up resistor.

2.10SYNC

The SYNC pin reflects the OUTx corresponding to the channel selected in the control register bits MUX_EN, MUX_A, B, C (Addr: hex00; Bit 7-4). If the multiplexer is disabled the SYNC pin is actively pulled low.

Figure 3. Example for SYNC pin functionality

OUT0
OUT1
SYNC
Channel 0 selected	Channel 1 selected

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L99PD08	Pin definitions and functions

2.11EN

With this pin pulled high, the device leaves low power mode. An internal pull down resistor guarantees the OFF condition when not connected.

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Device mode	L99PD08

3Device mode

Table 3.	Device modes
Mode		Source	Actions		CS-timer	SPI state	Outputs	ChipReset-	LHOMEN
							state	bit
Power down		Low VCORE3	All registers		Not active	No comm.	High-Z	1	LOW(1)
			are cleared				fail safe
Standby		EN = ‘0’	All registers		Not active	No comm.	High-Z	1	LOW(1)
			are cleared				fail safe
		CSNTO(2) /	-					0
		LHOMEN bit =‘0’					High-Z
Fail save					Active	Active			LOW(1)
							fail safe
		SW reset	All registers					1
			are cleared
Normal		LHOMEN-bit = ‘1’	-		Active	Active	Normal	0	VDDIO
1. Max. sink current can only be guaranteed for VCORE3					VCORE3min. Therefore an external pull down is recommended.
2. ChipSelectNot-TimeOut
Note:	To leave FAIL SAVE the LHOMEN-bit in ControlRegister (Addr.: hex00, Bit 0) has to be set
	to ‘1’. FAIL SAVE is reentered by either ChipSelectNot-TimeOut (CSNTO) or SW-Reset (in
	both cases LHOME-bit is automatically reset) or setting this bit to ‘0’ via SPI access.

To stay in normal mode a rising edge has to be generated at CSN within every timeframe programmed in the control register (Addr.: hex00, Bit 3,2). Else a CSNTO is detected and FAIL SAVE entered.

When SDI is stuck to GND the device enters automatically FAIL SAVE.

When SDI is stuck to logical high level then the device receives a SW-Reset and enters FAIL SAVE. A read of ROM address Addr.: hex3F is detected as stuck to logical high level.

In FAIL SAVE the SYNC pin is logical high.

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L99PD08	Device mode

Figure 4. Device state diagram

POWER DOWN

STANDBY

			’1	’
		=
	N						’
E						’0
					=
				N
			E

E N

=

’ 0 ’

FAIL SAVE	LHOMEN-bit = ’1’
	NORMAL

LHOMEN-bit = ’0’

CSN-TimOut

SW-Reset

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