ST L99DZ80EP User Manual

L99DZ80EP

Door actuator driver

Features

■One full bridge for 6 A load (RON = 150 mΩ)

■Two half bridges for 3 A load (RON = 300 mΩ)

■Two half bridges for 0.5 A load (RON = 1600 mΩ)

■One high-side driver for 5 A load (RON = 100 mΩ)

■One configurable high-side driver for up to

1.5 A (RON = 500 mΩ) or 0.35 A (RON = 1600 mΩ) load

■One configurable high-side driver for 0.7 A (RON = 800 mΩ) or 0.35 A (RON = 1600 mΩ) load

■Two high-side drivers for 0.5 A load (RON = 1600 mΩ)

■Programmable softstart function to drive loads with higher inrush currents as current limitation value

■Very low VS current consumption in standby mode (IS < 6 µA typ; Tj ≤ 85 °C)

■Current monitor output for all high-side drivers

■Central two-stage charge pump

■Motor bridge driver with full Rdson down to 6 V

■Device contains temperature warning and protection

■Open-load detection for all outputs

■Overcurrent protection for all outputs

■Separated half bridges for door lock motor

■Programmable PWM control of all outputs

■STM standard serial peripheral interface (STSPI 3.1)

■Control block for electrochromic element

■Electrochromic element can be negatively discharged

■Prepared for additional fail-safe path for H-bridge

*$3*&)7

TQFP-64

Applications

■Door actuator driver with 6 bridges for double door lock control, mirror fold and mirror axis control, high-side driver for mirror defroster, bulbs and LEDs.

■Control block with external MOS transistor for charging / discharging of electrochromic glass. Motor bridge driver.

■H-bridge control for external power transistors

Description

The L99DZ80EP is a microcontroller driven multifunctional door actuator driver for automotive applications. Up to five DC motors and five grounded resistive loads can be driven with six half bridges and five high-side drivers. Four external MOS transistors in bridge configuration can be driven. An electrochromic mirror glass can be controlled using the integrated SPI-driven module in conjunction with an external MOS transistor. The mirror glass can also be discharged through a negative supply. The integrated SPI controls all operating modes (forward, reverse, brake and high impedance). Also all diagnostic information is available via SPI read.

Table 1.	Device summary
Package		Order codes
		Tray	Tape and reel
TQFP-64		L99DZ80EP	L99DZ80EPTR

September 2011

Doc ID 18260 Rev 4

1/68

www.st.com

Contents	L99DZ80EP

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 7
2	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.2	ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.3	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.4	Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13

2.4.1 TQFP-64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Outputs OUT1 - OUT11, ECV, ECFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.8 Electrochrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.9 SPI / logic – electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
	3.1	Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	3.2	Wake up and Active mode/standby mode . . . . . . . . . . . . . . . . . . . . . . . .	32
	3.3	Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	3.4	Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	3.5	Overvoltage and undervoltage detection at VS . . . . . . . . . . . . . . . . . . . .	32
	3.6	Overvoltage and undervoltage detection at VCC . . . . . . . . . . . . . . . . . . .	33
	3.7	Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	3.8	Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	3.9	Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	3.10	Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	3.11	Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	3.12	PWM mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	3.13	Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35

3.14Programmable soft-start function to drive loads with higher inrush

	current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
3.15	H-bridge control (DIR, PWMH, bits SD, SDS) . . . . . . . . . . . . . . . . . . . . .	36
3.16	H-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37

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L99DZ80EP			Contents
	3.17	Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 38
	3.18	Short circuit detection/drain source monitoring . . . . . . . . . . . . . . . .	. . . . 38
	3.19	H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 39
	3.20	Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . .	. . . . 41
	3.21	Controller of electrochromic glass . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 42
	3.22	Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 44
4	Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 45
	4.1	General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 45

4.1.1 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.2 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.3 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.5 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.2.1 Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

	4.3	Device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
5	SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		49
	5.1	Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	5.2	Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	5.3	Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
	5.4	Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
	5.5	Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	5.6	Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	5.7	Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
	5.8	Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
	5.9	Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
	5.10	Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
	5.11	Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
	5.12	Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
6	Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		59

6.1 ECOPACK® package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 TQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Doc ID 18260 Rev 4

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Contents			L99DZ80EP
	6.3	TQFP-64 packing information . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 61
7	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . 65

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L99DZ80EP	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Package thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10. Current monitor output (CM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. On-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 13. Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 15. Gate drivers for the external Power-MOS (H-bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. Gate drivers for the external Power-MOS switching times . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 17. Drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 18. Open-load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 19. Electrochrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 20. Delay time from Standby to Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 21. Inputs: DI, CSN, CLK, DIR and PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 22. AC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 23. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 24. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 25. H-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 26. H-bridge DS-monitor threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 27. Cross-current protection time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 28. Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 29. Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 30. RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 31. ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 32. Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 33. Control Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 34. Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 35. Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 36. Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 37. Control Register 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 38. Control Register 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 39. Control Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 40. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 41. Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 42. Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 43. Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 44. Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 45. TQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 46. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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List of figures	L99DZ80EP

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. TQFP-64 2 layer PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. TQFP-64 4 layer PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. TQFP-64 thermal impedance junction to ambient vs PCB copper area . . . . . . . . . . . . . . . 14 Figure 6. IGHxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 7. IGHxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. H-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 10. SPI input and output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 11. SPI delay description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12. Power-output (OUT<11:1>, ECV, ECFD) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 13. Overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 14. H-bridge GSHx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 15. H-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 16. H-bridge open-load detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 17. H-bridge open-load detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 18. H-bridge open-load detection (short to ground detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 19. H-bridge open-load detection with H-OLTH HIGH = ‘1’ (short to VS detected) . . . . . . . . . 41 Figure 20. Electrochrome mirror driver with mirror referenced to ground . . . . . . . . . . . . . . . . . . . . . . 43 Figure 21. Electrochrome mirror driver with mirror referenced to ECFD for negative discharge . . . . . 44 Figure 22. Write and read SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 23. TQFP-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 24. TQFP-64 power lead-less tray shipment (no suffix) (part 1). . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 25. TQFP-64 power lead-less tray shipment (no suffix) (part 2). . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 26. TQFP-64 power lead-less tape and reel shipment (suffix “TR”) (part 1). . . . . . . . . . . . . . . 63 Figure 27. TQFP-64 power lead-less tape and reel shipment (suffix “TR”) (part 2). . . . . . . . . . . . . . . 64

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L99DZ80EP	Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

								9%$7
			a Q)
		a Q)				! N
		&3 3	96	&3
		&3 0				Pё		0
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7/68

Block diagram and pin description			L99DZ80EP
	Table 2.	Pin definitions and functions
	Pin	Symbol	Function
	57, 58	GND1	Ground: reference potential. GND1 and GND2 are internally connected.
			GND1 supplies OUT1-3, GND2 supplies OUT4-6
	17, 18,
		GND2	Important: For the capability of driving the full current at the outputs, all
	26, 31, 32		pins of GND must be externally connected!
	17	SGND	Signal Ground: this pin is shared with GND2 pin
	2, 3, 45,	VS1	Power supply voltage for power stage outputs (external reverse protection
	46, 51, 52		required): for this input a ceramic capacitor as close as possible to GND
			is recommended. VS1 supplies OUT1-3, OUT7-11 and the internal VS
	11, 12,	VS2	supply, VS2 supplies OUT4-6
			Important: For the capability of driving the full current at the outputs all
	23, 36, 37
			pins of VS must be externally connected!
			High-side-driver output 11: the output is built by a high-side switch and is
			intended for resistive loads, hence the internal reverse diode from GND to
			the output is missing. For ESD reason a diode to GND is present but the
			energy which can be dissipated is limited. The High-side driver is a power
	48, 49, 50	OUT11	DMOS transistor with an internal parasitic reverse diode from the output
			to VS (bulk-drain-diode). The output is overcurrent and open load
			protected.
			Important: For the capability of driving the full current at the outputs all
			pins of OUT11 must be externally connected!
	59, 60	OUT1
	56	OUT2	Half-bridge outputs 1,2,3,4,5,6: the output is built by a high side and a low
	55	OUT3
			side switch, which are internally connected. The output stage of both
	19, 20,	OUT4	switches is a power DMOS transistor. Each driver has an internal
			parasitic reverse diode (bulk-drain-diode: high side driver from output to
	21, 22
			VS, low side driver from GND to output). This output is over current and
	27, 28,
		OUT5	open load protected.
	29, 30
	24, 25	OUT6
			Serial data output: the diagnosis data is available via the SPI and this
	40	DO	3-state-output. The output remains in 3-state, if the chip is not selected by
			the input CSN (CSN = high).
			Current monitor output: depending on the selected multiplexer bits of the
	34	CM	Control Register this output sources an image of the instant current
			through the corresponding high side driver with a fixed ratio.
			Chip-Select-Not input: this input is low active and requires CMOS logic
	35	CSN	levels. The serial data transfer between the device and the micro
			controller is enabled by pulling the input CSN to low level.
			Serial data input: the input requires CMOS logic levels and receives serial
	41	DI	data from the microcontroller. The data is a 24 bit control word and the
			most significant bit (MSB, bit 23) is transferred first.
	38	CLK	Serial clock input: this input controls the internal shift register of the SPI
			and requires CMOS logic levels.
	33	DIR	Direction Input: this input controls the H-Bridge Drivers

8/68	Doc ID 18260 Rev 4

L99DZ80EP			Block diagram and pin description
	Table 2.	Pin definitions and functions (continued)
	Pin	Symbol	Function
	39	VCC	Supply Voltage: 5 V supply. A ceramic capacitor as close as possible to
			GND is recommended.
			High-side-driver output 9: the output is built by a high side switch and is
			intended for resistive loads; hence the internal reverse diode from GND to
			the output is missing. For ESD reason a diode to GND is present but the
	44	OUT9	energy which can be dissipated is limited. The high-side driver is a power
			DMOS transistor with an internal parasitic reverse diode from the output
			to VS (bulk-drain-diode). The output is over current and open load
			protected.
	42	PWMH	PWMH input: this input signal can be used to control the H-Bridge Gate
			drivers
	43	ECDR	ECDR: using the device in EC control mode this pin is used to control the
			Gate of an external MOSFET.
	62, 63	OUT7	High side driver output 8: see OUT9
			Important: This output can be configured to supply a bulb with low on-
	61	OUT8
			resistance or a LED with higher on-resistance in a different application.
			High-side-driver-output 10: see OUT9
	47	OUT10/EC	Important: Beside the OUT10-HS on/off bit this output can be switched on
			setting the ECON bit for electrochrome control mode with higher priority.
			ECFD: using the device in EC control mode this pin is used as “virtual
	54	ECFD	GND” for the EC-glass. For EC-glasses, that require a negative discharge
			voltage, this supplies the fast discharge voltage. If no EC-glass is used,
			this pin must be connected to ground.
			ECV: using the device in EC control mode this pin is used as voltage
	53	ECV	monitor input. For fast discharge an additional low-side-switch is
			implemented.
	13	GH2	GH2: gate driver for power MOS high side switch in half-bridge 2
	14	SH2	SH2: source of high-side switch in half-bridge 2
	15	GL2	GL2: gate driver for power MOS low side switch in half-bridge 2
	16	SL2	SL2: source of low side switch in half-bridge 2
	64	GH1	GH1: gate driver for power MOS high side switch in half-bridge 1
	1	SH1	SH1: source of high-side switch in half-bridge 1
	4	GL1	GL1: gate driver for power MOS low side switch in half-bridge 1
	5	SL1	SL1: source of low side switch in half-bridge 1
	7	CP1P	CP1P: charge pump pin for capacitor 1, positive side
	8	CP1M	CP1M: charge pump pin for capacitor 1, negative side
	9	CP2P	CP2P: charge pump pin for capacitor 2, positive side
	10	CP2M	CP2M: charge pump pin for capacitor 2, negative side
	6	CP	CP: charge pump output

Doc ID 18260 Rev 4

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Block diagram and pin description																																	L99DZ80EP
	Figure 2. Pin connection (top view)
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Doc ID 18260 Rev 4

L99DZ80EP	Electrical specifications

2 Electrical specifications

2.1Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

	Table 3.	Absolute maximum ratings
	Symbol		Parameter/test condition		Value	Unit
					[DC Voltage]
	VS1, VS2		DC supply voltage		-0.3 to +28	V
			Single pulse / tmax < 400 ms “transient load dump”		-0.3 to +40	V
		VCC	Stabilized supply voltage, logic supply		-0.3 to VS + 0.3	V
	VDI, VCLK, VCSN, VDO,		Logic input / output voltage range		-0.3 to VCC + 0.3	V
	VCM, VDIR, VPWMH, VDIR
	VOUTn, ECDR, ECV, ECFD		Output voltage (n = 1 to 11)		-0.3 to VS + 0.3	V
	VSL1, VSH1, VSL2, VSH2		High voltage signal pins		-6 to 40	V
		(VSxy)
	VGL1, VGH1, VGL2, VGH2		High voltage signal pins		VSxy - 1 to VSxy + 10;	V
		(VGxy)			VCP + 0.3
		VCP1P	High voltage signal pins		VS - 0.3 to VS + 10	V
		VCP2P	High voltage signal pins		VS - 0.6 to VS + 10	V
	VCP1M, VCP2M		High voltage signal pins		-0.3 to VS + 0.3	V
		VCP	High voltage signal pin	VS1,2 ≤ 26 V	VS - 0.3 to VS + 14	V
				VS1,2 > 26 V	VS - 0.3 to +40	V
	IOUT2,3,9,10, ECV, ECFD		Output current(1)		±1.25	A
	IOUT1,6,7		Output current(1) (low on-resistance mode)		±5	A
		IOUT7	Output current(1) (high on-resistance mode)		±5	A
		IOUT8	Output current(1)		±2.5	A
		IOUT4,5	Output current(1)		±10	A
		IOUT11	Output current(1)		±7.5	A
		IVS1cum	Maximum cumulated input current at VS1 pins(1)		±12.5	A
		IVS2cum	Maximum cumulated input current at VS2 pins(1)		±12.5	A
	IGND1cum		Maximum cumulated output current at GND1 pins(1)		±5	A
	IGND2cum		Maximum cumulated output current at GND2 pins(1)		±12.5	A

1.Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power dissipation or other limits.

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Electrical specifications	L99DZ80EP

2.2ESD protection

Table 4.	ESD protection
	Parameter	Value	Unit
All pins		±2(1)	kV
Power output pins: OUT1 – OUT11, ECV, ECFD		±4(1)	kV

1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.

2.3Thermal data

Table 5.

Operating junction temperature

Symbol

Parameter

Value

Unit

Tj

Operating junction temperature

-40 to 150

°C

Table 6.

Temperature warning and thermal shutdown

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

TjTW ON

Temperature warning threshold

130

150

°C

(junction temperature)

TjTS ON

Thermal shutdown threshold

150

170

°C

(junction temperature)

Tjtft

Thermal warning / shutdown

32

µs

filter time

Table 7.

Package thermal impedance

Symbol

Parameter

Value

Unit

Rthj-amb

Thermal resistance junction to ambient (max)

See Figure 5

K/W

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Doc ID 18260 Rev 4

L99DZ80EP	Electrical specifications

2.4Package and PCB thermal data

2.4.1TQFP-64 thermal data

Figure 3. TQFP-64 2 layer PCB

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Figure 4. TQFP-64 4 layer PCB

	*$3*&)7
Note:	Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm +/- 10%,
	board double layer and four layers, board dimension 77 mm x114 mm, board material FR4,
	Cu thickness 0.070mm (outer layers), Cu thickness 0.035mm (inner layers), thermal vias
	separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias
	0.025 mm, footprint dimension 6 mm x 6 mm). 4-layer PCB: Cu on mid1 layer, Cu on mid2
	layer and Cu on bottom layer: 62 cm2. Zth measured on the major power dissipator
	contributor

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Electrical specifications	L99DZ80EP

Figure 5. TQFP-64 thermal impedance junction to ambient vs PCB copper area

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Doc ID 18260 Rev 4

L99DZ80EP	Electrical specifications

2.5Electrical characteristics

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ VS ≤ 18 V, 4.75 V ≤ VCC ≤ 5.5 V; all outputs open;

Tj = -40 °C to 150 °C, unless otherwise specified.

Table 8.	Supply
Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
VS	Operating voltage range		5		28	V
IVS(act)	Current consumption in	VS = 13.5 V(1)		5	10	mA
	active mode
		VS = 16 V; VCC = 5.3 V;
		standby mode
IVS(stby)	Current consumption in	OUT1 - OUT11; ECV;		4	12	µA
	standby mode	ECDR floating
		TTEST = -40 °C to 25 °C
		TTEST = 85 °C(1)		6	25	µA
VCC	Operating voltage range		4.5		5.5	V
		VS = 16 V; VCC = 5.3 V;
IVCC(active)	VCC supply current	CSN = VCC; active mode		5	10	mA
		OUT1 - OUT11; ECV;
		ECDR floating
		VS = 16 V; VCC = 5.0 V;
		CSN = VCC; active mode		3	6	µA
		OUT1 - OUT11; ECV;
		ECFD ECDR floating
		TTEST = -40 °C to 25 °C
IVCC(stby)	VCC standby current	TTEST = 85 °C(1)		4	8	µA
		VS = 16 V; VCC = 5.3 V;
		CSN = VCC; active mode			25	µA
		OUT1 - OUT11; ECV;
		ECFD ECDR floating
		TTEST = -40 °C to 125 °C
1. This parameter is guaranteed by design

Table 9.	Overvoltage and undervoltage detection
Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
VSUV ON	VS UV threshold voltage(1)	VS increasing	5.6		7.2	V
VSUV OFF	VS UV threshold voltage(1)	VS decreasing	5		5.9	V
VSUV hyst	VS UV hysteresis(1)	VSUV ON-VSUV OFF		0.5		V
tvsuvfilt	VS UV filter time			48		µs
VSOV OFF	VS OV threshold voltage(1)	VS increasing	18.5		24.5	V
VSOV ON	VS OV threshold voltage(1)	VS decreasing	18.0		23.5	V
VSOV hyst	VS OV hysteresis(1)	VSOV OFF-VSOV ON		1		V

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Electrical specifications						L99DZ80EP
	Table 9.	Overvoltage and undervoltage detection (continued)
	Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
	tvsovfilt	VS OV filter time			48		µs
	VVCCRESHU	Upper VCC reset	VCC increasing	5.8		7.5	V
		threshold(2)
	VVCCRESHD	Upper VCC reset threshold	VCC decreasing	5.5		7.1	V
	VVCCRES	Upper reset hysteresis	VVCCRESHU - VVCCRESHD		0.1		V
	hysth
	VPOROFF	Power-on-reset threshold	VCC increasing	3.4		4.4	V
	VPORON	Power-on-reset threshold	VCC decreasing	3.1		4.1	V
	VPOR hystL	Power-on-reset hysteresis	VPOROFFL - VPORONL		0.3		V

1.VS = 5V to 28V

2.If VCC exceeds this value all registers are reset and the device enters standby mode.

Table 10. Current monitor output (CM)

Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
VCM	Functional voltage range		0		VCC - 1 V	V
	Current monitor output ratio:
	ICM/IOUT1,4,5,6,11 and 7 (low on-			1/10000
ICM r	resistance)	0 V ≤ VCM ≤ VCC - 1 V
	ICM/IOUT8 (low on-resistance)			1/6500
	ICM/IOUT2,3,7,8,9,10 and 7,8 (high on-			1/2000
	resistance)
		0 V ≤ VCM ≤ VCC - 1 V;
		IOUTmin = 500 mA;
	Current monitor accuracy	IOUT4,5max = 5.9 A;
	accICMOUT1,4,5,6,11 and 7(low on-res.)	IOUT11max = 4.9 A;
		IOUT1,6max = 2.9 A;		4 % +	8 % +
		IOUT7max = 1.4 A
ICM acc				1 % FS	2 % FS
		0 V ≤ VCM ≤ VCC - 1 V;
				(1)	(1)
		IOUT.min = 100 mA;
	accICMOUT2,3,8,9,10 and 7(high on-res.)	IOUT2,3,9,10max = 0.4A;
		IOUT7max = 0.3 A;
		IOUT8(low rdson)max = 0.6 A;
		IOUT8(high rdson)max = 0.3 A
tcmb	Current monitor blanking time			32		µs
1. FS (full scale) = IOUTmax * ICMr

Table 11.		Charge pump
Symbol		Parameter	Test condition	Min.	Typ.	Max.	Unit
VCP		Charge pump output	VS = 6 V; ICP = -10 mA	VS + 6	VS + 7	VS + 7.85	V
		voltage	VS ≥ 10 V; ICP = -15 mA	VS + 11	VS + 12	VS + 13.5	V

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Doc ID 18260 Rev 4

L99DZ80EP							Electrical specifications
	Table 11.		Charge pump (continued)
	Symbol		Parameter		Test condition		Min.	Typ.	Max.	Unit
			Charge pump output	VCP = VS + 10 V;
	ICP		current(1)	VS = 13.5 V;			25		47	mA
				C1 = C2 = CCP = 100 nF
	ICPlim		Charge pump output	VCP = VS; VS = 13.5 V;			29		70	mA
			current limitation(2)	C	= C	= C = 100 nF
				1	2	CP
	VCP_low		Charge pump low				VS + 4.6	VS + 5	VS + 5.4	V
			threshold voltage
	TCP		Charge pump low filter					64		µs
			time

1.ICP is the minimum current the device can provide to an external circuit without VCP going below VS + 10 V

2.ICPlim is the maximum current, which flows out of the device in case of a short to VS

2.6Outputs OUT1 - OUT11, ECV, ECFD

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ VS ≤ 18 V, 4.75 V ≤ VCC ≤ 5.5 V; all outputs open;

Tj = -40 °C to 150 °C, unless otherwise specified.

Table 12. On-resistance

Symbol	Parameter		Test condition	Min.	Typ.	Max.	Unit
			VS = 13.5 V; Tamb = +25 °C;		300	400	mΩ
	On-resistance to supply or		IOUT1,6 = ±1.5 A
rON OUT1,6
	GND		VS = 13.5 V; Tamb = +125 °C;		450	600	mΩ
			IOUT1,6 = ±1.5 A
			VS = 13.5 V; Tamb = +25 °C;		1600	2200	mΩ
	On-resistance to supply or		IOUT2,3 = ±0.4 A
rON OUT2,3
	GND		VS = 13.5 V; Tamb = +125 °C;		2500	3400	mΩ
			IOUT2,3 = ±0.4 A
			VS = 13.5 V; Tamb = +25 °C;		150	200	mΩ
	On-resistance to supply or		IOUT4,5 = ±3.0 A
rON OUT4,5
	GND		VS = 13.5 V; Tamb = +125 °C;		225	300	mΩ
			IOUT4,5 = ±3.0 A
			VS = 13.5 V; Tamb = +25 °C;		500	700	mΩ
	On-resistance to supply in		IOUT7 = -0.8 A
	low resistance mode		VS = 13.5 V; Tamb = +125 °C;		700	950	mΩ
			IOUT7 = -0.8 A
rON OUT7
			VS = 13.5 V; Tamb = +25 °C;		1600	2400	mΩ
	On-resistance to supply in		IOUT7 = -0.2 A
	high resistance mode		VS = 13.5 V; Tamb = +125 °C;		2500	3400	mΩ
			IOUT7 = -0.2 A

Doc ID 18260 Rev 4

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Electrical specifications								L99DZ80EP
	Table 12.	On-resistance (continued)
	Symbol		Parameter			Test condition	Min.	Typ.	Max.	Unit
					VS = 13.5 V; Tamb = +25 °C;			800	1200	mΩ
			On-resistance to supply in		IOUT8 = -0.4 A
			low resistance mode		VS = 13.5 V; Tamb = +125 °C;			1200	1700	mΩ
					IOUT8 = -0.4 A
	rON OUT8
					VS = 13.5 V; Tamb = +25 °C;			1600	2400	mΩ
			On-resistance to supply in		IOUT8 = -0.2 A
			high resistance mode		VS = 13.5 V; Tamb = +125 °C;			2500	3400	mΩ
					IOUT8 = -0.2 A
					VS = 13.5 V; Tamb = +25 °C;			1600	2200	mΩ
					IOUT9,10 = -0.4 A
	rON OUT9,10		On-resistance to supply
					VS = 13.5 V; Tamb = +125 °C;			2500	3400	mΩ
					IOUT9,10 = -0.4 A
					VS = 13.5 V; Tamb = +25 °C;			100	140	mΩ
					IOUT11 = -3.0 A
	rON OUT11		On-resistance to supply
					VS = 13.5 V; Tamb = +125 °C;			140	190	mΩ
					IOUT11 = -3.0 A
					VS = 13.5 V; Tamb = +25 °C;			1600	2200	mΩ
					IOUTECV,ECFD = +0.4 A
	rON ECV,ECFD		On-resistance to GND
					VS = 13.5 V; Tamb = +125 °C;			2500	3400	mΩ
					IOUTECV,ECFD = +0.4 A
			Switched-off output current		VOUT = 0 V; standby mode		-5	-2		µA
	IQLH		high side drivers of OUT1-
					VOUT = 0 V; active mode		-10.2	-7		µA
			6,9-11
	IQLH7,8		Switched-off output current		VOUT = 0 V; standby mode		-5	-2		µA
			high side drivers of OUT7,8		V	= 0 V; active mode	-15	-10		µA
					OUT
			Switched-off output current		VOUT = VS; standby mode			80	165	µA
					VOUT = VS - 0.5 V;
			low side drivers of OUT1-6				-10	-7		µA
					active mode
	IQLL		Switched-off output current		VOUT = VS; standby mode		-15		15	µA
					VOUT = VS - 0.5 V;
			low side drivers of ECV				-10	-7		µA
					active mode
			Switched-off output current		VOUT = 4 V; standby mode			80	165	µA
			low side drivers of ECFD		VOUT = 4 V; active mode		-10		10	µA

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Doc ID 18260 Rev 4

L99DZ80EP				Electrical specifications
	Table 13.	Power outputs switching times
	Symbol	Parameter	Test condition		Min.	Typ.	Max.	Unit
		Output delay time high side
		driver on (all OUT except			10	40	80	µs
		OUT7,8)
		Output delay time high side	VS = 13.5 V; VCC = 5 V;
	td ON H	driver on (OUT7,8 in high RDSON	corresponding low side		15	35	60	µs
		mode)	driver is not active(1)(2)(3)
		Output delay time high side
		driver on (OUT7,8 in low RDSON			10	35	80	µs
		mode)
		Output delay time high side			50	150	300	µs
		driver off (OUT1,4,5,6,11)	VS = 13.5 V;
	td OFF H
			VCC = 5 V	(1)(2)(3)
		Output delay time high side			40	70	100	µs
		driver off (OUT2,3, 7,8,9,10)
	td ON L	Output delay time low side driver	VS = 13.5 V; VCC = 5 V;		15	30	70	µs
		on	corresponding low side
			driver is not active(1)(2)(3)
		Output delay time low side driver	VS = 13.5 V; VCC = 5 V		40	150	300	µs
		(OUT1-6) off	(1)(2)(3)
	td OFF L
		Output delay time low side driver	VS = 13.5 V;		15	45	88	µs
		(ECV, ECFD) off	VCC = 5 V(1)(2)(3)
	td HL	Cross current protection time		(4)
			tcc ONLS_OFFHS – td OFF H		40	200	400	µs
	td LH	(OUT1-6)	tcc ONHS_OFFLS – td OFF L
				(4)
	dVOUT/dt	Slew rate of OUTx, ECV, ECFD	VS = 13.5 V;		0.08	0.2	0.6	V/µs
			VCC = 5 V(1)(2)(3)
	fPWMx(low)	Low PWM switching frequency	VS = 13.5 V; VCC = 5 V			122		Hz
	fPWMx(high)	High PWM switching frequency	VS = 13.5 V; VCC = 5 V			244		Hz

1.Rload = 16 Ω at OUT1,6 and OUT7,8 in low on-resistance mode

2.Rload = 4 Ω at OUT4,5,11

3.Rload = 64 Ω at OUT2,3,4,9,10 ECV, ECFD and OUT7,8 in high on-resistance mode

4.tCC is the switch-on delay time if complement in half bridge has to switch off

Table 14.	Current monitoring
Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
|IOC1|,			3		5.3	A
|IOC6|
|IOC2|,	Overcurrent threshold to supply	VS = 13.5 V;	0.5		1.0	A
|IOC3|,	or GND	VCC = 5 V; sink and
|IOCECFD|		source
|IOC4|,			6		9.2	A
|IOC5|

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Electrical specifications									L99DZ80EP
	Table 14.		Current monitoring (continued)
	Symbol		Parameter		Test condition		Min.	Typ.	Max.	Unit
			Overcurrent threshold to supply				1.5		2.5	A
			in low on-resistance mode
	|IOC7|
			Overcurrent threshold to supply				0.35		0.65	A
			in high on-resistance mode
			Overcurrent threshold to supply	VS = 13.5 V;			0.7		1.3	A
			in low on-resistance mode
	|IOC8|			VCC = 5 V;
			Overcurrent threshold to supply	source			0.35		0.65	A
			in high on-resistance mode
	|IOC9|,						0.5		1.0	A
	|IOC10|		Overcurrent threshold to supply
	|IOC11|						5		7.5	A
				VS = 13.5 V;
	|IOCECV|		Output current limitation to GND	VCC = 5 V;			0.5		1.0	A
				sink
				Duration of
		tFOC	Filter time of overcurrent signal	overcurrent condition			10	55	100	µs
				to set the status bit
		frec0	Recovery frequency for OC;				1		4	kHz
			recovery frequency bit = 0
		frec1	Recovery frequency for OC;				2		6	kHz
			recovery frequency bit = 1
	|IOLD1|,						8	30	80	mA
	|IOLD6|
	|IOLD2|,		Undercurrent threshold to supply	VS = 13.5 V;			10	20	30	mA
	|I	|,		V	CC	= 5 V;
		OLD3	or GND
	|I	|		sink and source
	OLDECFD
	|IOLD4|,						60	150	300	mA
	|IOLD5|
			Undercurrent threshold to supply				15	40	60	mA
			in low on-resistance mode
	|IOLD7|
			Undercurrent threshold to supply				5	10	15	mA
			in high on-resistance mode
			Undercurrent threshold to supply	VS = 13.5 V;			10	30	45	mA
	|IOLD8|		in low on-resistance mode	VCC = 5 V;
			Undercurrent threshold to supply	source			5	10	15	mA
			in high on-resistance mode
	|IOLD9|,						10	20	30	mA
	|IOLD10|		Undercurrent threshold to supply
	|IOLD11|						30	150	300	mA

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Doc ID 18260 Rev 4

L99DZ80EP				Electrical specifications
	Table 14.	Current monitoring (continued)
	Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
			VS = 13.5 V;
	|IOLDECV|	Undercurrent threshold to GND	VCC = 5 V;	10	20	30	mA
			sink
			Duration of open-
	tFOL	Filter time of open-load signal	load condition to set	0.5	2.0	3.0	ms
			the status bit

2.7H-bridge driver

Table 15. Gate drivers for the external Power-MOS (H-bridge)

Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
	Drivers for external high-side Power-MOS
IGHx(Ch)	Average charge current	Tj = 25 °C		0.3		A
	(charge stage)
		VSHx = 0 V; IGHx = 50 mA;	4	6	8	Ω
	On-resistance (discharge-	Tj = 25 °C
RGHx
	stage)	VSHx = 0 V; IGHx = 50 mA;		8	10	Ω
		Tj = 125 °C
VGHxH	Gate-on voltage	Outputs floating	VSHx +	VSHx +	VSHx +	V
			8	10	11.5
RGSHx	Passive gate-clamp	VGHx = 0.5 V		15		kΩ
	resistance
	Drivers for external low-side Power-MOS
IGLx(Ch)	Average charge-current	Tj = 25 °C		0.3		A
	(charge stage)
		VSLx = 0 V; IGHx = 50 mA;	4	6	8	Ω
	On-resistance (discharge-	Tj = 25 °C
RGLx
	stage)	VSLx = 0 V; IGHx = 50 mA;		8	10	Ω
		Tj = 125 °C
VGHLx	Gate-on voltage	Outputs floating	VSLx +	VSLx +	VSLx +	V
			8	10	11.5
RGSLx	Passive gate-clamp			15		kΩ
	resistance

Table 16.	Gate drivers for the external Power-MOS switching times
Symbol	Parameter		Test condition	Min.	Typ.	Max.	Unit
TG(HL)xHL	Propagation delay time high to	VS = 13.5 V; VSHx = 0;			1.5		µs
	low (switch mode)(1)	R	= 0 Ω; C = 2.7 nF
		G	G
TG(HL)xLH	Propagation delay time low to	VS = 13.5 V; VSLx = 0;			1.5		µs
	high (switch mode)(1)	R	= 0 Ω; C = 2.7 nF
		G	G

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