L99DZ70XP
Door actuator driver
Features
■ One full bridge for 6 A load (R
■ Two half bridges for 3 A load (R
■ Two half bridges for 0.75 A load
(R
= 1600 mΩ)
on
■ One highside driver for 6 A load (R
■ Two configurable highside drivers for up to
1.5 A load (R
(R
=1800mΩ)
on
■ Two highside drivers for 0.5 A load
(R
= 1600 mΩ)
on
■ Programmable softstart function to drive loads
=500mΩ) or 0.4 A
on
with higher inrush currents as current limitation
value
■ Very low current consumption in standby mode
(I
< 6 µA typ; Tj ≤ 85 °C; ICC < 5 µA typ;
S
T
≤ 85 °C)
j
■ Current monitor output for all highside drivers
■ Device contains temperature warning and
protection
■ Openload detection for all outputs
■ Over-current protection for all otputs
■ Separated half bridges for door lock motor
■ PWM control of all outputs
■ Charge pump output for reverse polarity
protection
■ STM standard serial peripheral interface (ST-
SPI 3.0)
■ Control block for electrochromic element
Table 1. Device summary
= 150 mΩ)
on
= 300 mΩ)
on
on
=90mΩ)
PowerSSO-36
Applications
■ Door actuator driver with 6 bridges for double
door lock control, mirror fold and mirror axis
control, highside driver for mirror defroster,
bulbs and LEDs (replacement for L9950).
Control block with external MOS transistor for
charging / discharging of electrochromic glass.
Description
The L99DZ70XP is a microcontroller driven
multifunctional door actuator driver for automotive
applications. Up to five DC motors and five
grounded resistive loads can be driven with six
half bridges and five highside drivers. An
electrochromic mirror glass can be controlled
using the integrated SPI-driven module in
conjunction with an external MOS transistor. The
integrated SPI controls all operating modes
(forward, reverse, brake and high impedance).
Also all diagnostic information is available via SPI
read.
Package
Order codes
Tube Tape and reel
PowerSSO-36 L99DZ70XP L99DZ70XPTR
November 2010 Doc ID 15162 Rev 3 1/47
www.st.com
1
Contents L99DZ70XP
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Outputs OUT1 - OUT11, ECV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 SPI - Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Wake up and active mode / standby mode . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Overvoltage and undervoltage detection at V
3.6 Overvoltage and undervoltage detection at V
. . . . . . . . . . . . . . . . . . . . 25
S
. . . . . . . . . . . . . . . . . . . 25
CC
3.7 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25
3.8 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Over-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 Programmable soft-start function to drive loads with higher inrush current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Controller for electrochromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/47 Doc ID 15162 Rev 3
4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.1 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
L99DZ70XP Contents
4.1.3 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.5 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.1 Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5 Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6 Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.7 Status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.8 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 15162 Rev 3 3/47
List of tables L99DZ70XP
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Current monitor output CM / PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Charge pump output CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. On-resistance and switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 12. Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Electrochrome control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 15. Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 16. SDI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 17. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 18. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 19. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 20. SPI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 21. Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 23. RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 24. ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25. Control register 0 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 26. Control register 1 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. Control register 2 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 28. Control register 3 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 29. Status register 0 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 30. Status register 1 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 31. Status register 2 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 32. Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 33. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 34. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4/47 Doc ID 15162 Rev 3
L99DZ70XP List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Electrochrome control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. SPI - Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. SPI - driver turn on/off timing, minimum CSN HI time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Example of programmable soft-start function for inductive loads . . . . . . . . . . . . . . . . . . . . 27
Figure 10. Write and read SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Global error flag definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 15162 Rev 3 5/47
Block diagram and pin description L99DZ70XP
1 Block diagram and pin description
Figure 1. Block diagram
V
BAT
L99PM62GXP
VCC
SPC560D
100µF
1k
1k
1k
1k
1k
1k
100nF
DI
DO
CLK
CSN
PWM1
CM/PWM2
STD18NF03L
VS
Charge
Pump
VCC
ST SPI
SPI
Standby
Interface
CM
MUX
100k
10k
CP
Ωm300
OUT1
Ωm1600
Ωm1600
Ωm150
Ωm150
Ωm300
Ωm1800/500
Ωm1800/500
Ωm90
Driver Interface & Diagnostic
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT11
OUT9
M
M
M
M
10 Watt
10 Watt
M
progr. Bulb or LED Mode
Ωm1600
OUT10
STD18NF03L
Control Block
6BIT SPI controlled
GND
EC Glass
Ωm1600
Ωm1600
ECDR (VS)
5 nF 100 nF
ECV (VS)
All components to be
placed together as close
as possible
Table 2. Pin definition and functions
Pin
Symbol Function
Ground: reference potential.
1, 18, 19, 36 GND
Important: For the capability of driving the full current at the outputs all pins
of GND must be externally connected!
Highside driver output 11.
The output is built by a highside switch and is intended for resistive loads,
therefore the internal reverse diode from GND to the output is missing. For
ESD reason a diode to GND is present, but the energy which can be
2, 35 OUT11
dissipated is limited. The highside driver is a power DMOS transistor with an
internal parasitic reverse diode from the output to VS (bulk-drain-diode). The
output is over-current protected.
Important: for the capability of driving the full current at the outputs both pins
of OUT11 must be externally connected!
6/47 Doc ID 15162 Rev 3
L99DZ70XP Block diagram and pin description
Table 2. Pin definition and functions (continued)
Pin
3
4
5
Symbol Function
OUT1,
OUT2,
OUT3
6, 7, 14, 15,
23, 24, 28, 29V
8DI
9
CM/
PWM2
10 CSN
11 DO
Halfbridge outputs 1,2,3.
The output is built by a highside and a lowside switch, which are internally
connected. The output stage of both switches is a power DMOS transistor.
Each driver has an internal parasitic reverse diode (bulk-drain-diode:
highside driver from output to VS, lowside driver from GND to output). This
output is over-current protected.
Power supply voltage (external reverse protection required).
For this input a ceramic capacitor as close as possible to GND is
recommended.
S
Important: For the capability of driving the full current at the outputs all pins
of VS must be externally connected!
Serial data input.
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is a 24 bit control word and the most significant bit
(MSB, bit 23) is transferred first.
Current monitor output/PWM2 input.
Depending on the selected multiplexer bits of the control register this output
sources an image of the instant current through the corresponding highside
driver with a ratio of 1/10.000 or 1/2000. This pin is bidirectional. The
microcontroller can overdrive the current monitor signal to provide a second
PWM input for the outputs OUT5, OUT8 and OUT10.
Chip Select Not input / Testmode.
This input is low active and requires CMOS logic levels. The serial data
transfer between L99DZ70 and the microcontroller is enabled by pulling the
input CSN to low level.
Serial data output.
The diagnosis data is available via the SPI and this tristate-output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high)
Supply voltage.
12 VCC
For this input a ceramic capacitor as close as possible to GND is
recommended.
Serial clock input.
13 CLK
This input controls the internal shift register of the SPI and requires CMOS
logic levels.
16,17
20,21
22
OUT4,
OUT5,
OUT6
Halfbridge outputs 4,5,6: see OUT1 (pin 3).
Important: For the capability of driving the full current at the outputs both
pins of OUT4 (OUT5, respectively) must be externally connected!
Electrocromic driver output.
If the electrochrome mode is selected this pin is used to control the gate of
25 ECDR
an external MOSFET, otherwise it remains in high-impedance state.
Note: It is possible to connect the pin to VS as in L9950/53/54 applications,
as long as the electrochome mode is not enabled via SPI.
Charge pump output.
26 CP
This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection (see Figure 1.).
Doc ID 15162 Rev 3 7/47
Block diagram and pin description L99DZ70XP
Table 2. Pin definition and functions (continued)
Pin
Symbol Function
27 PWM1
30
31
OUT7,
OUT8,
32 ECV
33 OUT9
34 OUT10
PWM1 input.
This input signal can be used to control the drivers OUT1-4, OUT6-7, OUT9
and OUT11 and ECV by an external PWM signal.
Highside driver outputs 7,8: see OUT9.
By selection of one of the 2 power DMOS at same output is it possible to
supply a bulb with low on-resistance or a LED with higher on-resistance in a
different application.
Electrochrome voltage input and lowside driver output.
This input senses voltage in electrocrome mode for charge monitoring.
The lowside switch provides a fast discharge of electrocromic mirror and can
be used 'stand alone' as lowside switch beside electrocromic mode.
Highside driver output 9.
The output is built by a highside switch and is intended for resistive loads,
hence the internal reverse diode from GND to the output is missing. For
ESD reason a diode to GND is present but the energy which can be
dissipated is limited. The highside driver is a power DMOS transistor with an
internal parasitic reverse diode from the output to VS (bulk-drain-diode). The
output is over-current and open load protected.
Highside driver output 10: see OUT9.
Important: beside the bit10 in control register 1 this output can be switched
on setting bit1 for electrocromic control mode with higher priority.
8/47 Doc ID 15162 Rev 3
L99DZ70XP Block diagram and pin description
Figure 2. Configuration diagram (top view)
GND
1
OUT11
OUT1
OUT2
OUT3
CM / PWM2
OUT4
OUT4
GND
CSN
DO
Vcc
CLK
Vs
Vs
Vs
Vs
DI
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
PowerSSO-36
9
Note: All pins with the same name must be externally connected.
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
OUT11
OUT10
OUT9
ECV
OUT8
OUT7
Vs
Vs
PWM1
CP
ECDR
Vs
Vs
OUT6
OUT5
OUT5
GND
Doc ID 15162 Rev 3 9/47
Electrical specifications L99DZ70XP
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
Vs
Vcc Stabilized supply voltage, logic supply -0.3 to 5.5 V
VDI, V
DO, VCLK,
V
CSN, VPWM
V
CM
V
CP
V
OUTn, ECDR, ECV
I
OUT,2,3,9,10,
ECV
I
OUT1,6,7,8,
I
OUT4,5,11
DC supply voltage -0.3...28 V
Single pulse t
Digital input / output voltage -0.3 to VCC + 0.3 V
< 400 ms 40 V
max
Current monitor output -0.3 to VCC + 0.3 V
Charge pump output -25 .. VS + 11 V
Static output voltage (n= 1 to 11) -0.3 to VS + 0.3 V
Output current ±1.25 A
Output current ±5 A
Output current ±10 A
2.2 ESD protection
Table 4. ESD protection
Parameter Value Unit
All pins ± 2
Output pins: OUT1 - OUT6, ECV ± 4
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
2. HBM with all unzapped pins grounded.
10/47 Doc ID 15162 Rev 3
(1)
(2)
kV
kV
L99DZ70XP Electrical specifications
2.3 Thermal data
Table 5. Operating junction temperature
Symbol Parameter Value Unit
T
Operating junction temperature -40 to 150 °C
j
Table 6. Temperature warning and thermal shutdown
Symbol Parameter Min. Typ. Max. Unit
T
jTW ON
T
jSD ON
T
jSD OFF
T
jSD HYS
Temperature warning threshold junction
temperature
Thermal shutdown threshold junction
temperature
Thermal shutdown threshold junction
temperature
Thermal shutdown hysteresis 5 °K
2.4 Electrical characteristics
VS = 8 to 16V, VCC= 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 7. S u p ply
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.1 VS Operating voltage range 7 28 V
7.2
7.3
7.4
(1)
VS DC supply current
I
S
quiescent supply
V
S
current
T
130 150 °C
j
Tj
increasing
decreasing
=16V, VCC=5.3V
V
S
Tj
150 °C
active mode
OUT1 - OUT11, ECV,
ECDR floating
=16V, VCC=0V
V
S
standby mode
OUT1 - OUT11, ECV,
ECDR floating
= -40°C, 25°C
T
test
T
= 85°C 6 25
test
170 °C
720mA
412
µA
Doc ID 15162 Rev 3 11/47
Electrical specifications L99DZ70XP
Table 7. Supply (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
VS=16V, VCC=5.3V
7.5
VCC DC supply current
CSN = V
OUT1 - OUT11, ECV,
ECDR floating
V
=16V,
S
V
CC
standby mode
OUT1 - OUT11, ECV,
ECDR floating
T
test
T
test
7.6
7.7
(2)
(1)
I
CC
VCC quiescent supply
current
1. This parameter is guaranteed by design.
2. CM/ PWM 2 = V
Table 8. Overvoltage and under voltage detection
or 0 V.
CC
Item Symbol Parameter Test condition Min. Typ. Max. Unit
, active mode
CC
=5.3V
CSN=VCC
13mA
36
= -40°C, 25°C
= 85°C 5 10
µA
8.1 V
8.2 V
8.3 V
8.4 V
8.5 V
8.6 V
8.7 V
8.8 V
8.9 V
Table 9. Current monitor output CM / PWM 2
SUV onVS
SUV offVS
SUV hystVS
SOV offVS
SOV onVS
SOV hystVS
POR off
POR on
POR hyst
UV-threshold voltage VS increasing 5.6 7.2 V
UV-threshold voltage VS decreasing 5.2 6.1 V
UV-hysteresis V
SUV ON
- V
SUV OFF
0.5 V
OV-threshold voltage VS increasing 18 24.5 V
OV-threshold voltage VS decreasing 17.5 23.5 V
OV-hysteresis V
SOV OFF
- V
SOV ON
1V
Power-on-reset threshold VCC increasing 2.9 V
Power-on-reset threshold VCC decreasing 2.0 V
Power-on-reset hysteresis V
POR OFF
- V
POR ON
0.11 V
Item Symbol Parameter Test condition Min. Typ. Max Unit
9.1 V
Functional voltage
CM
range
0V
-1V V
CC
Current monitor
output ratio:
9.2
I
9.3
CM,r
I
CM/IOUT1,4,5,6,11
and 7,8
(low on-resistance)
I
CM/IOUT2,3,9,10
and 7,8
(high on-resistance)
0V <= VCM <= 4V
=5V
V
CC
1
----------------- -
10.000
1
------------ -
,
2000
12/47 Doc ID 15162 Rev 3
L99DZ70XP Electrical specifications
Table 9. Current monitor output CM / PWM 2 (continued)
Item Symbol Parameter Test condition Min. Typ. Max Unit
Current monitor
accuracy
9.4
I
CM acc
9.5
1. FS (full scale)= I
Table 10. Charge pump output CP
accI
CMOUT1,4,5,6,
11and 7, 8
(low on-res.)
accI
CMOUT2,3,9,10,
and 7, 8
(high on-res.)
OUTmax * ICM,r .
V
CM
3.8V,
V
CC
Item Symbol Parameter Test condition Min. Typ. Max Unit
10.1
10.2 V
V
Charge pump output
CP
voltage
10.3 V
10.4 I
Charge pump output
CP
current
2.4.1 Outputs OUT1 - OUT11, ECV
= 500mA
I
Out,min
I
Out4,5,11max
I
<=
= 5V
Out1,6 max
I
Out7,8 max
I
Out,min
I
Out2,3 max
I
Out9,10max
I
Out8 max
VS = 8V, I
= 10V, I
S
>=12V, ICP = -100µA VS+10 VS+13 V
S
= VS+10V,
V
CP
=13.5V
V
S
= 5.9A
= 2.9A
= 1.3A
4% +
1%FS
(1)
= 100 mA
= 0.6 A
= 0.4 A
= 0.3 A
= -60µA VS+6 VS+13 V
CP
= -80µA VS+8 VS+13 V
CP
95 150 300 µA
8% +
2%FS
(1)
Table 11. On-resistance and switching times
Item Symbol Parameter Test condition Min. Typ. Max. Unit
V
= 13.5 V,
S
11.1
r
ON OUT1,
r
ON OUT6
On-resistance to
supply or GND
11.2
11.3
r
ON OUT2,
r
ON OUT3
On-resistance to
supply or GND
11.4
=25°C,
T
j
=±1.5A
I
OUT1,6
V
= 13.5 V,
S
=125°C,
T
j
I
=±1.5A
OUT1,6
= 13.5 V,
V
S
=25°C,
T
j
I
= ± 0.4A
OUT2,3
V
= 13.5 V,
S
Tj=125°C,
=±0.4A
I
OUT2,3
300 400 mΩ
450 600 mΩ
1600 2200 mΩ
2500 3400 mΩ
Doc ID 15162 Rev 3 13/47
Electrical specifications L99DZ70XP
Table 11. On-resistance and switching times (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
V
= 13.5 V,
S
11.5
r
ON OUT4,
r
ON OUT5
On-resistance to
supply or GND
11.6
11.7
r
ON OUT9,
r
ON OUT10
On-resistance
to supply
11.8
11.9
On-resistance
rON OUT11
to supply
11.10
11.11
On-resistance to
supply in low mode
(control register 1
11.12
11.13
r
ON OUT7
r
ON OUT8
bits 12 to15: 0101)
On-resistance to
supply in high mode
(control register 1
11.14
bits 12 to15: 1010)
11.15
r
ON ECV
On-resistance to
GND
11.16
11.17
I
QLH
11.18
Switched-off output
current highside
drivers of OUT1-6,
8-11
=25°C,
T
j
=±3.0A
I
OUT4,5
V
= 13.5 V,
S
=125°C,
T
j
I
=±3.0A
OUT4,5
= 13.5 V,
V
S
Tj=25°C,
V
= 13.5 V,
S
=125°C,
T
j
= 13.5 V,
V
S
=25°C,
T
j
OUT11
V
= 13.5 V,
S
=125°C,
T
j
OUT11
= 13.5 V,
V
S
=-0.4A
=-0.4A
=-3.0A
=-3.0A
I
OUT9,10
I
OUT9,10
I
I
Tj=25°C,
OUT7,8
V
S
=125°C,
T
j
OUT7,8
V
S
=25°C,
T
j
OUT7,8
V
S
=-0.8A
= 13.5 V,
=-0.8A
= 13.5 V,
=-0.2A
= 13.5 V,
I
I
I
Tj=125°C,
OUT7,8
V
S
=25°C,
T
j
V
S
=125°C,
T
j
V
OUT
=-0.2A
= 13.5 V,
=+0.4A
= 13.5 V,
=+0.4A
= 0V,
I
I
OUTECV
I
OUTECV
standby mode
V
= 0V,
OUT
active mode
150 200 mΩ
225 300 mΩ
1600 2200 mΩ
2500 3400 mΩ
90 130 mΩ
130 180 mΩ
500 700 mΩ
700 950 mΩ
1800 2400 mΩ
2500 3400 mΩ
1600 2200 mΩ
2500 3400 mΩ
-5 -2 µA
-10 -7 µA
14/47 Doc ID 15162 Rev 3
L99DZ70XP Electrical specifications
Table 11. On-resistance and switching times (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
= 0V,
V
11.19
11.20
11.21
I
QLH7,8
Switched-off output
current highside
drivers of OUT7-8
Switched-off output
current lowside
11.22
11.23
I
QLL
drivers of OUT1-6
Switched-off output
current lowside
11.24
drivers of ECV
Output delay time,
11.25
highside driver on
except
(OUT
X
OUT
)
7,8
Output delay time,
11.26
t
d ON H
highside driver on
(OUT
R
DSon
in high
7,8
mode)
Output delay time,
11.27
highside driver on
(OUT
R
DSon
in low
7,8
mode)
Output delay time,
11.28
t
d OFF H
highside driver off
(OUT
1, 4, 5, 6, 11
)
Output delay time,
highside driver off
11.29
11.30 t
d ON L
(OUT
R
DSon , 8
R
DSon , 9, 10
Output delay time,
lowside driver On
2,3,7,
high/low
high/low
)
Output delay time,
11.31 t
d OFF L 1-6
lowside driver OUT
1-6 off
Output delay time,
11.32 t
d OFF L ECV
lowside driver ECV
off
OUT
standby mode
V
= 0V,
OUT
active mode
= VS,
V
OUT
standby mode
V
= 0V,
OUT
active mode
= VS,
V
OUT
standby mode
V
= VS,
OUT
active mode
V
= 13.5 V,
S
VCC=5V
(1)(2)(3)
VS= 13.5 V,
(1)(2)(3)
=5V
V
CC
= 13.5 V,
V
S
VCC=5V,
corresponding
highside driver is not
active
V
V
CC
(1)(2)(3)
=13.5V,
S
(1)(2)(3)
=5V
-5 -2 µA
-15 -10 µA
80 120 µA
-10 -7 µA
-15 15 µA
-10 10 µA
20 40 80 µs
15 35 60 µs
10 35 80 µs
60 150 200 µs
40 70 100 µs
15 30 70 µs
40 150 300 µs
15 45 80 µs
Doc ID 15162 Rev 3 15/47
Electrical specifications L99DZ70XP
Table 11. On-resistance and switching times (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
t
11.33 t
D HL
Cross current
protection time
11.34 t
11.35 dV
1. Rload = 16Ω at OUT1, 6 and 7,8 in low on-resistance mode.
2. Rload = 4
3. Rload = 64
is the switch-on delay time if complement in half bridge has to switch-off.
4. t
cc
Table 12. Current monitoring
D LH
OUT
/dt
Slew rate of OUTx
on/off
Ω at OUT4, 5 and 11.
Ω at OUT2, 3, 9, 10, ECV and 7, 8 in high On-resistance mode.
cc ONLS_OFFHS -
t
d OFFH
t
cc ONHS_OFFLS
t
d OFFL
VS= 13.5V,
=5V
V
CC
(4)
(4)
(1)(2)(3))
50 200 400 µs
-
0.1 0.2 0.6 V/µs
Item Symbol Parameter Test condition Min. Typ. Max. Unit
|I
|,
12.1
12.2
12.3
12.4
12.5 |I
12.6
12.7
OC1
|I
|
OC6
|I
|I
|I
|I
|I
|I
OC2
OC3
OC4
OC5
OC9
OC10
OC11
Over-current threshold
|,
|
to supply or GND
|,
|
|,
Over-current threshold
|
to supply
| 6 10 A
Over-current threshold
to supply in low
|I
|I
OC7
OC8
|,
|
on-resistance mode
Over-current threshold
to supply in high
on-resistance mode
V
=13.5V,
S
=5V,
V
CC
sink and source
VS=13.5V,
VCC= 5 V, source
=13.5V, VCC=5V,
V
S
source, control register
1 bits 12 to 15: 0101
=13.5V, VCC=5V,
V
S
source, control register
1 bits 12 to 15: 1010
35A
0.75 1.25 A
610A
0.5 1.0 A
1.5 2.5 A
0.35 0.65 A
12.8 |I
12.9 t
12.10 f
12.11 f
OCECV
FOC
rec0
rec1
|
Output current
limitation to GND
Filter time of
over-current signal
Recovery frequency for OC
recovery duty cycle bit= 0
Recovery frequency for OC
recovery duty cycle bit= 1
16/47 Doc ID 15162 Rev 3
V
=13.5V,
S
VCC= 5 V, source
Duration of over-current
condition to set the
status bit
0.75 1.25 A
10 55 100 µs
1 4 kHz
2 6 kHz
L99DZ70XP Electrical specifications
Table 12. Current monitoring (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
II
I,
12.12
12.13
12.14
12.15
12.16 II
12.17
12.18
12.19
12.20 t
OLD1
II
OLD6
II
OLD2
II
OLD3
II
OLD4
II
OLD5
II
OLD9
II
OLD10
OLD11
II
OLD7
II
OLD8
II
OLDECV
FOL
I
I,
Under-current threshold
I
to supply or GND
I,
I
I,
I
Under-current
=13.5V,
V
S
=5V,
V
CC
sink and source
10 30 80 mA
10 20 30 mA
60 150 300 mA
51015mA
threshold to supply
I30150300mA
Under-current threshold
to supply in low
I,
on-resistance mode
I
Under-current threshold
to supply in high
VS=13.5V,
VCC= 5 V, source
15 40 60 mA
51015mA
on-resistance mode
I
threshold to GND
Under-current
VS=13.5V,
VCC = 5V, sink
10 20 30 mA
Duration of under-
Filter time of under-current
current condition to set
0.5 3 ms
the status bit
Table 13. Electrochrome control
Item Symbol Parameter Test condition Min. Typ. Max. Unit
(3)
-V
(1)
1.4 1.6 V
(1)
1.12 1.28 V
-5%
-1
ECV
LSB
(3)
+5%
+1
LSB
(3)
(2)
mV
13.1
13.2
V
CTRLmax
Maximum EC-control
voltage
bit 0= 1 control reg. 2
bit 0= 0 control reg. 2
13.3 DNL Differential non linearity -1 1 LSB
13.4 IdV
ECV
Voltage deviation
I
between target and
ECV
dV
ECV =Vtarget
II
ECDR
I < 1µA
Toggle
=
ECV
bit 1=1
status
reg. 2
Toggle
bit 0= 1
status
120 mV
-120 mV
is:
Below
it
Above
it
dV
V
target
ECV
- V
13.5 dV
ECVnr
Difference
voltage
between target
and ECV sets
13.6 dV
ECVhi
flag if V
ECV
reg. 3
I
13.7 V
13.8 V
ECDRmin_high
ECDRmax_low
Output voltage range
= -10 µA 4.5 5.5 V
ECDR
I
= 10 µA 0 0.7 V
ECDR
Doc ID 15162 Rev 3 17/47
Electrical specifications L99DZ70XP
Table 13. Electrochrome control (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
13.9
13.10
13.11 R
13.12 I
I
ECDR
ecdrdis
QECDR
Current into ECDR
Pulldown resistance at
ECDR in fast
discharge mode
Quiescent current
V
target >VECV
V
V
target
V
V
V
ECDR
Cntrl Reg 1: bit 8 and bit
1 = 1, all other bits = 0
V
Cntrl. reg 1 bit 1 = 0
ECDR
< V
ECDR
target
V
ECV
ECDR
+ 500mV
= 3.5V
- 500mV,
ECV
= 1.0V;
=1 LSB;
=0.5V
= 0.7V ;
= VS;
,
-100 -10 µA
10 100 µA
5kΩ
1µA
1. Bit 7 to 2 = ‘1’ control register 1: ECV voltage, where II
ECDR
2. 1 LSB (Least Significant Bit)= 23.8 mV.
is set by bit 7 to 2 of control register 1 and bit 0 of control register 2; tested for each individual bit.
V
3.
target
Figure 3. Electrochrome control block diagram
D
A
C
can change sign.
Ω
Ω
2.5 SPI - Electrical characteristics
VS = 8 to 16V, VCC = 4.5 to 5.5V, Tj = - 40 to 150°C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
18/47 Doc ID 15162 Rev 3
the pin.
L99DZ70XP Electrical specifications
Table 14. Delay time from standby to active mode
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Switching from standby to active
14.1 t
Table 15. Inputs: CSN, CLK, PWM1/2 and DI
set
Delay time
Item Symbol Parameter Test condition Min. Typ. Max. Unit
mode. Time until output drivers are
enabled after CSN going to high and
set bit 0=1 of control register 0.
256 300 µs
15.1 V
15.2 V
15.3 V
15.4 R
15.5 R
15.6 R
15.7 R
PWM1 in
15.8 C
inL
inH
in Hyst
CSN in
CLK in
DI in
(1)
in
Input low level VCC = 5V
Input high level VCC = 5V
0.7*
Vcc
Input hysteresis VCC = 5V 500 mV
V
= 5V
CSN pull up resistor
CLK pull down resistor
DI pull down resistor
PWM1 pull down resistor
Input capacitance at input
CSN, CLK, DI and PWM1/2
0V<V
V
V
CLK
V
V
V
V
PWM1
0 V < V
CC
<0.7V
CSN
= 5V
CC
= 1.5V
= 5V
CC
= 1.5V
DI
= 5V
CC
= 1.5V
< 5.3V 10 pF
CC
30 120 250 kΩ
CC
30 60 150 kΩ
30 60 150 kΩ
30 60 150 kΩ
0.3*
Vcc
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16. SDI timing
(1)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
16.1 t
Clock period VCC = 5V 1000 ns
CLK
V
V
16.2 t
16.3 t
16.4 t
16.5 t
16.6 t
16.7 t
CLKH
CLKL
set CSN
set CLK
set DI
hold DI
Clock high time VCC = 5V 115 ns
Clock low time VCC = 5V 115 ns
CSN setup time, CSN low
before rising edge of CLK
CLK setup time, CLK high
before rising edge of CSN
= 5V 400 ns
V
CC
= 5V 400 ns
V
CC
DI setup time VCC = 5V 200 ns
DI hold time VCC = 5V 200 ns
Doc ID 15162 Rev 3 19/47
Electrical specifications L99DZ70XP
Table 16. SDI timing (continued)
(1)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
16.8 t
16.9 t
1. DI timing parameters tested in production by a passed / failed test:
Tj= -40°C / +25°C: SPI communication @ 2MHz.
Tj= +125°C SPI communication @ 1.25 MHz.
Table 17. D O
Rise time of input signal DI,
r in
CLK, CSN
Fall time of input signal DI,
f in
CLK, CSN
= 5V 100 ns
V
CC
V
= 5V 100 ns
CC
Item Symbol Parameter Test condition Min. Typ. Max. Unit
17.1 V
17.2 V
17.3 I
17.4 C
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
DOLK
DO
Output low level I
DOL
Output high level I
DOH
Tristate leakage
current
Tristate input
(1)
capacitance
= -5 mA 0.2V
DO
= 5 mA 0.8 V
DO
V
CSN
0V < V
V
CSN
0V < V
= VCC,
< V
DO
= VCC,
< 5.3V
CC
CC
CC
-10 10 µA
CC
10 pF
V
V
Table 18. DO timing
Item Symbol Parameter Test condition Min. Typ. Max. Unit
18.1 t
18.2 t
18.3 t
18.4 t
18.5 t
18.6 t
18.7 t
r DO
f DO
en DO tri L
dis DO L tri
en DO tri H
dis DO H tri
d DO
DO rise time C
DO fall time C
DO enable time
from tristate to low
level
DO disable time
from low level to
tristate
DO enable time
from tristate to high
level
DO disable time
from high level to
tristate
DO delay time
= 100 pF 80 140 ns
DO
= 100 pF 50 100 ns
DO
= 100 pF, I
C
DO
pull-up load to V
= 100 pF, I
C
DO
pull-up load to V
=100 pF, I
C
DO
pull-down load to GND
= 100 pF, I
C
DO
pull-down load to GND
V
< 0.3 VCC,
DO
V
> 0.7 VCC,
DO
= 100 pF
C
DO
load
CC
load
CC
load
load
= 1mA
= 4 mA
= -1mA
= -4mA
100 250 ns
380 450 ns
100 250 ns
380 450 ns
50 250 ns
20/47 Doc ID 15162 Rev 3
L99DZ70XP Electrical specifications
Table 19. CSN timing
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Mimimum CSN HI time,
19.1 t
CSN_HI,stb
switching from standby
mode
19.2 t
CSN_HI,min
Minimum CSN HI time,
active mode
Figure 4. SPI - Transfer timing diagram
CSN high to low: DO enabled
CSN high to low: DO enabled
CSN high to low: DO enabled
CSN
CSN
CSN
CLK
CLK
CLK
DI
DI
DI
DO
DO
DO
Input
Input
Input
Data
Data
Data
Register
Register
Register
123456 70
123456 70
123456 70
DI: data will be accepted on the rising edge of CLK signal
DI: data will be accepted on the rising edge of CLK signal
DI: data will be accepted on the rising edge of CLK signal
123 45670
123 45670
123 45670
DO: data will change on the falling edge of CLK signal
DO: data will change on the falling edge of CLK signal
DO: data will change on the falling edge of CLK signal
123 45670
123 45670
123 45670
CSN low to high: actual data is
CSN low to high: actual data is
fault bit
fault bit
fault bit
CSN low to high: actual data is
transfered to output power switches
transfered to output power switches
transfered to output power switches
Transfer of SPI-command
to input register
Transfer of SPI-command
to input register
X
X
X
X
XX
XX
XX
XX
old data new data
old data new data
old data new data
232221201918
232221201918
232221201918
232221201918
232221201918
232221201918
20 50 µs
24µs
01
01
01
time
time
time
01
01
01
time
time
time
0 1
0 1
0 1
time
time
time
time
time
time
time
time
time
Figure 5. SPI - Input timing
CSN
t
set C SN
t
CLKH
t
se t CLK
CLK
set DI
Valid
t
hold DI
t
DI
t
CLKL
Va lid
Doc ID 15162 Rev 3 21/47
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Electrical specifications L99DZ70XP
t
f
f
t
t
Figure 6. SPI - DO valid data delay time and valid time
t
in
CLK
t
r DO
DO
(low to high)
t
d DO
t
DO
DO
(high to low)
Figure 7. SPI - DO enable and disable time
f in r in
CSN
r i n
0.8 VCC
0.5 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
50%
0.2 VCC
DO
50%
pull-up load to VCC
C = 100 pF
L
DO
t t
en DO tri L
dis DO L tri
50%
pull-down load to GND
C = 100 pF
L
t t
22/47 Doc ID 15162 Rev 3
L99DZ70XP Electrical specifications
C
S
t
r
f
OFF
t
OFF
t
t
FFstat
t
O
p
t
e
r
t
e
r
f
rom shif
t
r
r
r
Figure 8. SPI - driver turn on/off timing, minimum CSN HI time
CSN low to high: data
ansf e
is
ed to output powerswitches
tregister
N
ut curren
out
output voltage
of a driv
of a driver
output curren
output voltage
of a driv
of a driver
t
in
d
eO
ON st a
dON
t
N
OFF state
t
CSN_HI,min
ON sta
e
e
t
in
80%
50%
20%
80%
50%
20%
80%
50%
20%
Doc ID 15162 Rev 3 23/47
Application information L99DZ70XP
3 Application information
3.1 Dual power supply: VS and V
CC
The power supply voltage VS supplies the half bridges and the highside drivers. An internal
charge-pump is used to drive the highside switches. The logic supply voltage V
for the logic part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be
lost, if there are temporary spikes or glitches on the power supply voltage.
3.2 Wake up and active mode / standby mode
After power up of VS and Vcc the device operates in standby-mode. Pulling the signal CSN
to low level wakes the device up and the analog part will be activated (active mode).
After at least 10µs, the first SPI communication is valid and bit 0 of the Control Register 0
can be used to set the EN-mode. If bit 0 is not set to 1, the device doesn't remain in the
active mode. After at least 256µs all latched data will be cleared and the inputs and outputs
are switched to high impedance. In standby mode the current at V
(5 µA) for CSN = high (DO in tristate).
3.3 Charge pump
In standby mode the chargepump is turned off. After enabling the device by SPI command
(bit0=1 Control Register 0) the oscillator starts and the voltage begins to increase. The
output drivers are enabled after at least 256 µs after CSN went to high.
is used
CC
(VCC) is less than 6 µA
S
3.4 Diagnostic functions
All diagnostic functions (over/under-current, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered. The condition has to be valid for at
least 32 µs (open load: 1ms) before the corresponding status bit in the status registers is
set.
The filters are used to improve the noise immunity of the device. The under-current and
temperature warning functions are intended for information purpose and will not change the
state of the output drivers. On contrary, the over-current condition disables the
corresponding driver and thermal shutdown disables all drivers. Without setting the overcurrent recovery bits in the input data register, the microcontroller has to clear the overcurrent status bits to reactivate the corresponding drivers.
24/47 Doc ID 15162 Rev 3
L99DZ70XP Application information
3.5 Overvoltage and undervoltage detection at V
If the power supply voltage VS rises above the overvoltage threshold V
21 V), the outputs OUT1 to OUT11, ECDR and ECV are switched to high impedance state
to protect the load. When the voltage VS drops below the undervoltage threshold V
(UV-switch-OFF voltage), the output stages are switched to high impedance to avoid the
operation of the power devices without sufficient gate driving voltage (increased power
dissipation). If the supply voltage V
recovers (control register 3: bit 4=0) to normal
S
operating voltage then the outputs stages return to the programmed state. If the
undervoltage/overvoltage recovery disable bit is set (control register 3: bit 4=1), the
automatic turn-on of the drivers is deactivated.
The microcontroller needs to clear the status bits to reactivate the drivers. It is
recommended to set bit1 control register 3 to avoid a possible high current oscillation in
case of a shorted output to GND and low battery voltage.
3.6 Overvoltage and undervoltage detection at V
In case of power-on (VCC increases from undervoltage to V
initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases
below the minimum threshold (V
POR ON
= 2.0 V), the outputs are switched to tristate (high
impedance) and the status registers are cleared.
POR OFF
S
SOV OFF
(typical
SUV OFF
CC
= 2.9 V) the circuit is
3.7 Temperature warning and thermal shutdown
If the junction temperature rises above T
32 µs and it can be read via the SPI. If the junction temperature increases above the second
threshold T
, the thermal shutdown bit is set and the power DMOS transistors of all output
jSD
stages are switched off to protect the device after at least 32 µs.
The temperature warning and thermal shutdown flags are latched and the bits must be
cleared by the microcontroller. This is possible only if the temperature has decreased below
trigger temperature. If the thermal shutdown bit has been cleared the output stages are
reactivated.
, a temperature warning flag is set after at least
j TW
3.8 Inductive loads
Each half bridge is built by internally connected highside and lowside power DMOS
transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can
be driven at the outputs OUT1 to OUT6 without external free-wheeling diodes. The highside
drivers OUT7 to OUT11 are intended to drive resistive loads. Therefore only a limited energy
(E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L>100µH) an external free-wheeling diode connected between GND and
the corresponding output is required.
The low side driver at ECV does not have a freewheel diode built into the device.
Doc ID 15162 Rev 3 25/47
Application information L99DZ70XP
3.9 Open load detection
The open load detection monitors the load current in each activated output stage. If the load
current is below the open load detection threshold for at least 1 ms (t
) the corresponding
dOL
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without
changing the mechanical/electrical state of the loads.
3.10 Over-load detection
In case of an over-current condition a flag is set in the status register in the same way as
during open load detection. If the over-current signal is valid for at least t
(typ) = 55 µs, the
ISC
over-current flag is set and the corresponding driver is switched off to reduce the power
dissipation and to protect the integrated circuit. If the over-current recovery bit of the output
is zero, the microcontroller has to clear the status bits to reactivate the corresponding driver.
3.11 Current monitor
The current monitor output sources a current image at the current monitor output which has
two fixed ratios of the instantaneous current of the selected highside driver. Outputs with a
resistance of 500 mΩ and higher have a ratio of 1/2000 and those with a lower resistance of
1/10000. The signal at output CM is blanked after switching on the driver until correct
settlement of the circuitry (at least for 64 µs). The bits 0 to 3 of the control register 3 define
which of the outputs are multiplexed to the current monitor output CM/PWM2. The current
monitor output allows a more precise analysis of the actual state of the load rather than the
detection of an open- or overload condition. For example it can be used to detect the motor
state (starting, free-running, stalled). Moreover, it is possible to control the power of the
defroster more precisely by measuring the load current. The current monitor output is
bidirectional (PWM inputs).
3.12 PWM inputs
Each driver has a corresponding PWM enable bit, which can be programmed by the SPI
interface. If the PWM enable bit is set in control registers 2 or 3, the output is controlled by
the logically AND-combination of the PWM signal and the output control bit in Control
Registers 0 and 1. The outputs OUT1-4, 6, 7, 9, OUT11 are controlled by the PWM1 input
and the outputs OUT5, 8 and OUT10 are controlled by the bidirectional input CM/PMW2.
For example, the two PWM inputs can be used to dim two lamps independently by external
PWM signals. In case of switching off a high/low side switch in PWM mode a minimum off
time of appr. (256 µs – td
the high/low side again during the negative slope. For a PWM frequency of 100Hz this
means the maximum duty cycle is about 98%. Larger duty cycles can be realized by
applying pulse skipping.
26/47 Doc ID 15162 Rev 3
on
+ td
) is predefined by the state machine, to avoid switching on
off
L99DZ70XP Application information
3.13 Cross-current protection
The six half-brides of the device are cross-current protected by an internal delay time. If one
driver (LS or HS) is turned off, the activation of the other driver of the same half bridge will
be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver is changed to a
fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this
behaviour it is always guaranteed that the previously activated driver is completely turned off
before the opposite driver starts to conduct.
3.14 Programmable soft-start function to drive loads with higher inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device automatically switches
the outputs on again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition. The PWM frequency settles at 1.7kHz
and 3kHz. The device itself cannot distinguish between a real overload and a non linear load
like a light bulb. A real overload condition can only be qualified by time. For over-load
detection the microcontroller can switch on the light bulbs by setting the over-current
recovery bit for the first e.g. 50ms. After clearing the recovery bit the output will be
automatically switched off, if the overload condition remains. This over-load detection
procedure has to be followed in order make it possible to switch on the low-side driver of a
bridge output, if the associated high-side driver has been used in recovery mode before.
Figure 9. Example of programmable soft-start function for inductive loads
Doc ID 15162 Rev 3 27/47
Application information L99DZ70XP
3.15 Controller for electrochromic glass
The voltage of an electrochromic element connected at pin ECV can be controlled to a
target value, which is set by the bits 7 down to 2 of control register 1. Setting bit 1 of control
register 1 enables this function. An on-chip differential amplifier and an external MOS
source follower, with its gate connected to pin ECDR and which drives the electrochrome
mirror voltage at pin ECV, form the control loop. The drain of the external MOS transistor is
supplied by OUT10. A diode from pin ECV (anode) to pin ECDR (cathode) has been placed
on the chip to protect the external MOS source follower. A capacitor of at least 5 nF has to
be added to pin ECDR for loop-stability.
The target voltage is binary coded with a full scale range of 1.5V. If Bit 0 of control register 2
is set to '1', the maximum controller output voltage is clamped to 1.2V without changing the
resolution of bits 7-2 of control register 1. When setting the target voltage to 0V and
programming the ECVLS driver to on-state, the voltage at pin ECV is pulled to ground by a
1.6 Ohm low-side switch (fast discharge).
The status of the voltage control loop is reported via SPI. Bit 0 in the status register 2 is set,
if the voltage at pin ECV is higher, whereas Bit 1 in the same status register is set, if the
voltage at pin ECV is lower than the target value. Both status bits are valid, if they are stable
for at least 150 µs.
Since OUT10 is the output of a high-side driver, it contains the same diagnose functions as
the other high-side drivers (e.g. During an over current detection, the control loop is
switched off). In electrochrome mode OUT10 cannot be controlled by PWM mode. For EMS
reasons the loop capacitor at pin ECDR as well as the capacitor between ECV and GND
have to be placed to the respective pins as close as possible.
28/47 Doc ID 15162 Rev 3
L99DZ70XP Functional description of the SPI
4 Functional description of the SPI
4.1 General description
Standard ST-SPI Interface Version 3.0.
The SPI communication is based on a Serial Peripheral Interface interface structure using
CSN (Chip Select Not), DI (Serial Data In), DO (Serial Data Out/Error) and CLK (Serial
Clock) signal lines.
4.1.1 Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal wakes up the device and a serial
communication can be started. The state when CSN is going low until the rising edge of
CSN will be called a communication frame.
4.1.2 Serial Data In (DI)
The input pin is used to transfer data serially into the device. The data applied to the DI will
be sampled at the rising edge of the CLK signal.
4.1.3 Serial Clock (CLK)
This input signal provides the timing of the serial interface. The Data Input (DI) is latched at
the rising edge of Serial Clock CLK . The SPI can be driven by a micro controller with its SPI
peripheral running in following mode: CPOL = 0 and CPHA = 0. Data on Serial Data Out
(DO) is shifted out at the falling edge of the serial clock (CLK). The serial clock CLK must be
active only during a frame (CSN low). Any other switching of CLK close to any CSN edge
could generate set up/hold violations in the SPI logic of the device.
The clock monitor counts the number of clock pulses during a communication frame (while
CSN is low). If the number of CLK pulses does not correspond to the frame width indicated
in the <SPI-frame-ID> (ROM address 03H) the frame is ignored and the <frame error> bit in
the <Global Status Byte> is set.
Note: Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
4.1.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the global status bit 7 (Global Error
Flag). The first rising edge of the CLK input after a high to low transition of the CSN pin will
transfer the content of the selected status register into the data out shift register. Each
subsequent falling edge of the CLK will shift the next bit out.
Doc ID 15162 Rev 3 29/47
Functional description of the SPI L99DZ70XP
4.1.5 SPI communication flow
At the beginning of each communication the master can read the contents of the <SPIframe-ID> register (ROM address 03H) of the slave device. This 8-bit register indicates the
SPI frame length (24 bit) and the availability of additional features.
Each communication frame consists of a command byte which is followed by 2 data bytes.
The data returned on DO within the same frame always starts with the <Global Status>
Byte. It provides general status information about the device. It is followed by 2 data bytes (i.
e. ‘In-frame-response’).
For Write cycles the <Global Status> Byte is followed by the previous content of the
addressed register.
Figure 10. Write and read SPI
30/47 Doc ID 15162 Rev 3
L99DZ70XP Functional description of the SPI
Table 20. SPI frame
Bit 23 22 212919181716 151413121110 9 8
Name OC1 OC0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Command Byte Data Byte Data Byte
76543210
Ocx: Operation code
Ax: Address
Dx: Data Bit
4.2 Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Read>, <Write>, <Read and Clear>, <Read Device
Information>) and a 6 bit address. If less than 6 address bits are required, the remaining bits
are unused but are reserved.
4.2.1 Operation code definition
Table 21. Operation code definition
OC1 OC0 Meaning
0 0 <Write Mode>
0 1 <Read Mode>
1 0 <Read and Clear Mode>
1 1 <Read Device Information>
The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.
A <Read and Clear Mode> operation is used to read a status register and subsequently
clear its content.
The <Read Device Information> allows access to the ROM area which contains device
related information such as <ID-Header>, <Product Code>, <Silicon Version and Category>
and <SPI-frame-ID>.
Doc ID 15162 Rev 3 31/47
Functional description of the SPI L99DZ70XP
4.3 Global status byte
Table 22. Global status byte
Bit 7 6 5 4 3 2 1 0
Name GL_ER CO_ER C_RESET TSD TW UOV_OC OL NR
Reset 0 0 1 0 0 0 0 0
Description:
● GL_ER : Global Error Flag. Failures of Bits 0-6 are always linked to the Global Error
Flag. This flag is generated by an OR combination of all failure events of the device. It
is reflected via the DO pin while CSN is held low and no clock signal is available. The
flag will remain as long as CSN is low. This operation does not cause the
Communication Error bit in the <Global Status> to be set. The signal TW bit3 and OL
bit1can be masked.
● CO_ER : Communication Error. If the number of clock pulses within the previous frame
is not 24 the frame is ignored and this bit is set.
● C_RESET : Chip RESET. If a stuck at ‘1’ on input DI during any SPI frame occurs, or if
a Power On Reset (VCC monitor) occurs. C_RESET will be reset (‘1’) with any SPI
command. When STK_RESET_Q is active (‘0’), the Gate drivers are switched off
(resistive path to source).
After a startup of the circuit the STK_RESET_Q is active because of the POR pulse
and the Gate drivers are switched off. The Gate drivers can only be activated after the
STK_RESET_Q has been reset with a SPI command.
● TSD : Thermal shutdown due to an internal sensor. All the gate drivers and the charge
pump must be switched off (resistive path to source). The TSD bit has to be cleared
through a software reset to reactivate the gate drivers and the charge pump.
● TW : Thermal Warning. This bit is maskable by configuration register.
● UOV_OC : Logical OR among the filtered under-/over-voltage signals and over-current
signals.
● OL : Open Load. Logical OR among the filtered under-current signals. This bit is
maskable by configuration register.
● NR : Not Ready. After switching the device from standby mode to active mode an
internal timer is started to allow chargepump to settle before the outputs can be
activated. This bit is cleared automatically after start up time has finished.
32/47 Doc ID 15162 Rev 3
L99DZ70XP Functional description of the SPI
Figure 11. Global error flag definition
4.4 Address mapping
Table 23. RAM memory map
Address Name Access Content
00h Control register 0 Read/write Enable of device and bridge control
01h Control register 1 Read/write
02h Control register 2 Read/write
03h Control register 3 Read/write
High/low-side control and Electrocrome block set
up
Bridge recovery mode and PWM set up and
Electrocrome block set up
Highside recovery mode and PWM set up and
current monitor selection
10h Status register 0 Read only Bridge over-current diagnosis
11h Status register 1 Read only Bridge open load (under-current) diagnosis
12h Status register 2 Read only
3Fh
Table 24. ROM memory map
Configuration
register
Read/write
Open load (under-current) diagnosis, VS and
electrocrome diagnosis
Mask of bits in global status register and for global
error bit
Address Name Access Content
00h ID header Read only 4300h (ASSP ST_SPI)
01h Version Read only 0300h
02h Product code 1 Read only 4300h (67 ST_SPI)
03h Product code 2 Read only 4800h (H ST_SPI)
3Eh SPI-frame ID Read only 0200h SPI-Frame-ID register (ST_SPI)
Doc ID 15162 Rev 3 33/47
SPI - control and status registers L99DZ70XP
5 SPI - control and status registers
5.1 Control register 0
Table 25. Control register 0 (read/write)
Bit Name Comment
9
8
7
6
5
4
OUT1 – HS
on/off
OUT1 – LS
on/off
OUT2 – HS
on/off
OUT2 – LS
on/off
OUT3 – HS
on/off
OUT3 – LS
on/off
OUT4 – HS
on/off
OUT4 – LS
on/off
OUT5 – HS
on/off
OUT5 – LS
on/off
OUT6 – HS
on/off
OUT6 – LS
on/off
15
14
13
12
11
10
30
If a bit is set the selected output driver is switched on. If the corresponding
PWM enable bit is set the driver is only activated if PWM1 (PWM2) input
signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of
HS- and LS-driver of the same half bridge are set, the internal logic
prevents that both drivers of this output stage can be switched on
simultaneously in order to avoid a high internal current from Vs to GND.
Reserved (has to be set to '0')20
10
0 Enable bit
If enable bit is set the device will be switched in active mode. If enable bit is
cleared, the device enters standby mode and all bits are cleared.
34/47 Doc ID 15162 Rev 3
L99DZ70XP SPI - control and status registers
5.2 Control register 1
Table 26. Control register 1 (read/write)
Bit Name Comment
OUT7 – HS1
15
14
13
12
11
10
9
on/off
OUT7 – HS2
on/off
OUT8 – HS1
on/off
OUT8 – HS2
on/off
OUT9 – HS
on/off
OUT10 – HS
on/off
OUT11 – HS
on/off
8 ECV – LS on/off
7EC bit 5
6EC bit 4
5EC bit 3
4EC bit 2
3EC bit 1
2EC bit 0
OUT
7/8
HS1 HS2 Mode
11 Off
1 0 Low on-resistance
0 1 High on-resistance
00 Off
If a bit is set, the selected output driver is switched on. If the corresponding
PWM enable bit is set the driver is only activated if PWM1 (PWM2) input
signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of HSand LS-driver of the same half bridge are set, the internal logic prevents that
both drivers of this output stage can be switched on simultaneously in order to
avoid a high internal current from VS to GND.
Reference value for difference voltage amplifier at pin ECV is binary coded.
Full scale value is set in control register 2. If all EC bits are set to zero the
reference value is 0V. For fast discharge a lowside switch can be activated at
pin ECV, if the ECV – LS on/off bit is set to '1'..
In case this bit is set to 1, the electrochrome control is active and enables the
driver at pin ECDR for the external MOS transistor. The bit switches the
1 EC switch
highside OUT10 directly on, ignoring bit 10 in control register 1. If the drain of
the external MOS transistor is connected to OUT10, the current from supply
VS to the load at ECV can be monitored.
0 0 Reserved (has to be set to '0')
Doc ID 15162 Rev 3 35/47
SPI - control and status registers L99DZ70XP
5.3 Control register 2
Table 27. Control register 2 (read/write)
Bit Name Comment
15
14
13
12
11
10
9
OUT1 – OCR
enable
OUT2 – OCR
enable
OUT3 – OCR
enable
OUT4 – OCR
enable
OUT5 – OCR
enable
OUT6 – OCR
enable
ECV – OCR
enable
In case of an over-current event the over-current status bit (Status
Register 0) is set and the output is switched off. If the Over-current
Recovery Enable bit (OCR) is set, the output will be automatically
reactivated after a delay time resulting in a PWM modulated current with
a programmable duty cycle (bit 5 of control register 3).
Depending on occurrence of over-current event and internal clock phase
it is possible that one recovery cycle is executed even if this bit is set to
zero. The ECV-OCR enable bit is disabled in electrochrome mode
(bit1=1 control register 1).
8 0 Reserved (has to be set to '0')
7
6
5
4
3
2
OUT1 PWM1
enable
OUT2 PWM1
enable
OUT3 PWM1
enable
OUT4 PWM1
enable
OUT5 PWM2
enable
OUT6 PWM1
enable
If the PWM1/2 Enable bit is set and the output is enabled (control
register 0 or 1) the output is switched on if PWM1/2 input is high and
switched off if PWM1/2 input is low. OUT5, 8 and OUT10 are controlled
by PWM2 input, all other outputs are controlled by PWM1 input.
1
ECV PWM1
enable
The maximum ECV voltage in electrochrome mode is 1.5V. It
corresponds to the full scale range of the digital to analog converter DAC
0ECV-low voltage
set by the bits 7 to 2 of control register 1. If the ECV_low voltage bit is
set to '0', the maximum voltage is limited to 1.2V without changing the
resolution of the DAC. This is the default mode.
36/47 Doc ID 15162 Rev 3
L99DZ70XP SPI - control and status registers
5.4 Control register 3
Table 28. Control register 3 (read/write)
Bit Name Comment
15 OUT7-OCR enable In case of an over-current event the over-current status bit (Status
14 OUT8-OCR enable
13 OUT9-OCR enable
12 OUT10-OCR enable
11 OUT11-OCR enable
10 OUT7 PWM1 enable
9 OUT8 PWM2 enable
8 OUT9 PWM1 enable
7 OUT10 PWM2 enable
6 OUT11 PWM1 enable
register 1) is set and the output is switched off. If the Over-current
Recovery Enable bit (OCR) is set the output will be automatically
reactivated after a delay time resulting in a PWM modulated current
with a programmable duty cycle (bit 5). Depending on the
occurrence of the over-current event and the internal clock phase it
is possible that one recovery cycle is executed even if this bit is set
to zero.
If the PWM1/2 Enable bit is set and the output is enabled (control
register 0 or 1) the output is switched on if PWM1/2 input is high and
switched off if PWM1/2 input is low. OUT5, 8 and OUT10 are
controlled by PWM2 input all other outputs are controlled by PWM1
input.
OCR frequency
5
0: 1.7 kHz
1: 3 kHz
4 OV/UVR disable
3 CM select bit 3
2 CM select bit 2
1 CM select bit 1
This bit defines in combination with the over-current recovery bit
(Input Register 1) the over-current recovery frequency of an
activated driver.
If this bit is set the microcontroller has to clear the status register
after undervoltage/overvoltage event to enable the outputs.
Depending on combination of bit 3 to 0 the current image of
the selected highside output OUTn will be multiplexed to the
CM/PWM2 output (see table below).
Other combinations deactivate the current monitor.
Bit 3 Bit 2 Bit 1 Bit 0 Current image of
00 0 0 OUT1
00 0 1 OUT2
00 1 0 OUT3
00 1 1 OUT4
01 0 0 OUT5
01 0 1 OUT6
01 1 0 OUT7
01 1 1 OUT8
10 0 0 OUT9
10 0 1 OUT10
10 1 0 OUT11
0 CM select bit 0
Doc ID 15162 Rev 3 37/47
SPI - control and status registers L99DZ70XP
5.5 Status register 0
Table 29. Status register 0 (read)
Bit Name Comment
15 OUT1 – HS OC
14 OUT1 – LS OC
13 OUT2 – HS OC
12 OUT2 – LS OC
11 OUT3 – HS OC
10 OUT3 – LS OC
9 OUT4 – HS OC
8 OUT4 – LS OC
7 OUT5 – HS OC
6 OUT5 – LS OC
5 OUT6 – HS OC
4 OUT6 – LS OC
30
In case of an over-current event the corresponding status bit is set and the
output driver is disabled. If the over-current Recovery Enable bit is set the
output will be automatically reactivated after a delay time resulting in a
PWM modulated current with a programmable duty cycle.
If the over-current recovery bit is not set, the micro controller has to clear
the over-current bit to reactivate the output driver.
20
Reserved
10
00
38/47 Doc ID 15162 Rev 3
L99DZ70XP SPI - control and status registers
5.6 Status register 1
Table 30. Status register 1 (read)
Bit Name Comment
15 OUT1 – HS UC
14 OUT1 – LS UC
13 OUT2 – HS UC
12 OUT2 – LS UC
11 OUT3 – HS UC
10 OUT3 – LS UC
9 OUT4 – HS UC
8 OUT4 – LS UC
7 OUT5 – HS UC
6 OUT5 – LS UC
5 OUT6 – HS UC
4 OUT6 – LS UC
30
20
10
00
Maskable by the
configuration register
The open load detection monitors the load current in each activated output
stage. If the load current is below the under-current detection threshold for
at least 1 ms (t
) , the corresponding under-current bit UC is set. Due to
dOL
mechanical/electrical inertia of typical loads a short activation of the outputs
(e.g. 3ms) can be used to test the open load status without changing the
mechanical/electrical state of the loads.
Reserved
Doc ID 15162 Rev 3 39/47
SPI - control and status registers L99DZ70XP
5.7 Status register 2
Table 31. Status register 2 (read)
Bit Name Comment
15 OUT7 – OC
14 OUT7 – UC
13 OUT8 – OC
12 OUT8 – UC
11 OUT9 – OC
10 OUT9 – UC
9 OUT10 – OC
8OUT10 – UC
7 OUT11 – OC
6OUT11 – UC
5ECV – OC
4 ECV – UC
3
2
1
0
VS
under-voltage
VS
over-voltage
ECV voltage not
reached
ECV voltage
too high
In case of an over-current event the corresponding status bit OC is set and
the output driver is disabled. If the over-current recovery enable bit is set
the output will be automatically reactivated after a delay time resulting in a
PWM modulated current with a programmable duty cycle.
If the over-current recovery bit is not set the micro controller has to clear the
over-current bit to reactivate the output driver.
The open load detection monitors the load current in each activated output
stage. If the load current is below the under-current detection threshold for
at least 1 ms (t
) the corresponding under-current bit UC is set. Due to
dOL
mechanical/electrical inertia of typical loads a short activation of the outputs
(e.g. 3ms) can be used to test the open load status without changing the
mechanical/electrical state of the loads.
In case of an over-voltage or under-voltage event the corresponding bit is
set and the outputs are deactivated. If VS voltage recovers to normal
operating conditions outputs are reactivated automatically (if bit 4 of control
register 3 is not set).
Two comparators monitor the voltage at pin ECV in electrocrome mode. If
this voltage is below / above the programmed target these bits signal the
difference after at least 32 µs. The bits are not latched and may toggle after
at least 32 µs, if the ECV voltage has not yet reached the target. They are
not assigned to the Global Error Flag.
40/47 Doc ID 15162 Rev 3
L99DZ70XP SPI - control and status registers
5.8 Configuration register
Table 32. Configuration register (read/write)
Bit Name Comment
15 0
14 0
13 0
12 0
11 0
10 0
90
80
70
60
Reserved (has to be set to '0')
Mask for bit 15 of
5
Mask for bit 14 of
4
3
Mask for bit 3 of
global status reg.
status reg. 1
status reg. 1
Openload event (under-current status bit of OUT1 HS) is not
considered in openload bit 1 of global status register.
Openload event (under-current status bit of OUT1 LS) is not
considered in openload bit 1 of global status register.
Temperature warning event is not considered in the 'Global Error
Flag'.
2 0 Reserved (has to be set to '0')
1
Mask for bit 1 of
global status reg.
Openload event (under-current status bit of OUTn) is not considered
in the 'Global Error Flag'.
0 0 Reserved (has to be set to '0')
Doc ID 15162 Rev 3 41/47
Packages thermal data L99DZ70XP
6 Packages thermal data
Figure 12. Packages thermal data
42/47 Doc ID 15162 Rev 3
L99DZ70XP Package and packing information
7 Package and packing information
7.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.
7.2 PowerSSO-36 package information
Figure 13. PowerSSO-36 package dimensions
.
Doc ID 15162 Rev 3 43/47
Package and packing information L99DZ70XP
Table 33. PowerSSO-36 mechanical data
Symbol
Min. Typ. Max.
A- -2.45
A2 2.15 - 2.35
a1 0 - 0.1
b 0.18 - 0.36
c 0.23 - 0.32
(1)
D
10.10 - 10.50
E7.4 - 7.6
e-0.5-
e3 - 8.5 -
F-2.3-
G- -0.1
G1 - - 0.06
H 10.1 - 10.5
Millimeters
h--0.4
k0°-8°
L 0.55 - 0.85
M-4.3-
N- -10°
O-1.2-
Q-0.8-
S-2.9-
T-3.65-
U-1-
X4.3 - 5.2
Y6.9 - 7.5
1. “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm
per side (0.006”).
44/47 Doc ID 15162 Rev 3
L99DZ70XP Package and packing information
7.3 PowerSSO-36 packing information
Figure 14. PowerSSO-36 tube shipment (no suffix)
Base Qty 49
C
B
A
Figure 15. PowerSSO-36 tape and reel shipment (suffix “TR”)
Bulk Qty 1225
Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6
All dimensions are in mm.
Reel dimensions
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2
End
All dimensions are in mm.
Start
Top
cover
tape
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
No componentsNo components Components
500mm min
Doc ID 15162 Rev 3 45/47
Revision history L99DZ70XP
8 Revision history
Table 34. Document revision history
Date Revision Description of changes
12-Nov-2008 1 Initial release.
Table 33: PowerSSO-36 mechanical data:
– Deleted A (min) value
02-Jul-2009 2
19-Nov-2010 3 Updated Figure 1: Block diagram
– Changed A (max) value from 2.50 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed L (max) value from 0.90 to 0.85
46/47 Doc ID 15162 Rev 3
L99DZ70XP
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Doc ID 15162 Rev 3 47/47
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