L9954
L9954XP
Door actuator driver
Features
■ Three half bridges for 1.5A load (R
■ One highside driver for 6A load (R
■
Two highside drivers for 1.5A load (Ron=800mΩ)
■ Programmable softstart function to drive loads
with higher inrush currents (i.e. current >6A,
>1.5A)
■ Very low current consumption in standby mode
(I
< 6µA typ; Tj ≤ 85 °C)
S
■ All outputs short circuit protected
■ Current monitor output for highside OUT1,
OUT4, OUT5 and OUT6
■ All outputs over temperature protected
■ Open load diagnostic for all outputs
■ Overload diagnostic for all outputs
■ PWM control of all outputs
■ Charge pump output for reverse polarity
protection
=800mΩ)
on
=100mΩ)
on
PowerSO-36
PowerSSO-36
Applications
■ Door actuator driver with bridges for mirror axis
control and highside driver for mirror defroster
and two 10W-light bulbs.
Description
The L9954 and L9954XP are microcontroller
driven, multifunctional door actuator drivers for
automotive applications. Up to two DC motors
and three grounded resistive loads can be driven
with three half bridges and three highside drivers.
The integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
diagnostic information is available via the SPI.
Table 1. Device summary
Order codes
Package
PowerSO-36 L9954 L9954TR
PowerSSO-36 L9954XP L9954XPTR
May 2010 Doc ID 14279 Rev 3 1/37
Tube Tape and reel
www.st.com
1
Contents L9954 / L9954XP
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Programmable softstart function to drive loads with higher inrush current 22
4 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/37 Doc ID 14279 Rev 3
L9954 / L9954XP Contents
4.8 SPI - Input data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 PowerSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 PowerSSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4 PowerSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5 PowerSSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 14279 Rev 3 3/37
List of tables L9954 / L9954XP
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. OUT1 - OUT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 12. Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 13. Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 14. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 15. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 16. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 17. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 18. SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. PowerSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 21. PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4/37 Doc ID 14279 Rev 3
L9954 / L9954XP List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. SPI - driver turn on / off timing, minimum CSN HI time. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. PowerSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. PowerSO-36
Figure 14. PowerSO-36
Figure 15. PowerSSO-36
Figure 16. PowerSSO-36
TM
tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TM
tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TM
tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TM
tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 14279 Rev 3 5/37
Block diagram and pin description L9954 / L9954XP
1 Block diagram and pin description
Figure 1. Block diagram
V
BAT
Reverse Polarity
Protection
100k
*
100µF
* Note: Value of capacitor has to be choosen carefully to li mit the VS voltage below absolute
maximum ratings in case of an unexpected freewheeling condition (e.g. TSD, POR)
VS
VCC
10k
Charge
Pump
VCC
**
1k
**
1k
**
1k
**
1k
**
1k
DO
CLK
CSN
PWM1
DI
SPI
Interface
Driver Interface & Diagnostic
µC
PWM2 / CM
**
1k
** Note: Resistors between µC and L9954LXP are recommended to limit currents
for negative voltage transients at VBAT ( e.g. ISO type 1 pulse)
Table 2. Pin definitions and functions
MUX
GND
Pin Symbol Function
OUT1
OUT2
OUT3
M
M
Mirror Common
Mirror Vertical
Mirror Horizontal
Lock / Folder
OUT4
Programmable
OUT5
OUT6
4
Bulb (10W) or
LED Mode
Defroster
Ground :
1, 18, 19, 36 GND
Reference potential
Important: for the capability of driving the full current at the outputs all
pins of GND must be externally connected.
Highside-driver-output 6
The output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
2, 35 OUT6
which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the
output to VS (bulk-drain-diode). The output is over-current and open
load protected.
Important: for the capability of driving the full current at the outputs both
pins of OUT6 must be externally connected.
6/37 Doc ID 14279 Rev 3
L9954 / L9954XP Block diagram and pin description
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
Half-bridge-output 1,2,3
3
4
5
6, 7, 14, 25,
28, 32
OUT1
OUT2
OUT3
V
8DI
9
CM/PWM2
10 CSN
11 DO
The output is built by a highside and a lowside switch, which are
internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal parasitic reverse diode
(bulk-drain-diode: highside driver from output to VS, lowside driver from
GND to output). This output is over-current and open load protected.
Power supply voltage (external reverse protection required)
For this input a ceramic capacitor as close as possible to GND is
recommended.
S
Important: for the capability of driving the full current at the outputs all
pins of VS must be externally connected.
Serial data input
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is an 24bit control word and the least
significant bit (LSB, bit 0) is transferred first.
Current monitor output/PWM2 input
Depending on the selected multiplexer bits of Input Data Register this
output sources an image of the instant current through the
corresponding highside driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overdrive the current monitor
signal to provide a second PWM input for the output OUT5.
Chip select not input / testmode
This input is low active and requires CMOS logic levels. The serial data
transfer between L9954 and micro controller is enabled by pulling the
input CSN to low level.
Serial data output
The diagnosis data is available via the SPI and this tristate-output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high)
Logic supply voltage
12 V
CC
For this input a ceramic capacitor as close as possible to GND is
recommended.
Serial clock input
13 CLK
This input controls the internal shift register of the SPI and requires
CMOS logic levels.
Charge pump output
26 CP
This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection.
PWM1 input
27 PWM1
This input signal can be used to control the drivers OUT1-OUT4 and
OUT6 by an external PWM signal.
Doc ID 14279 Rev 3 7/37
Block diagram and pin description L9954 / L9954XP
/
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
Highside-driver-output 4 and 5
Each output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
31
33
OUT4,
OUT5
missing. For ESD reason a diode to GND is present but the energy
which can be dissipated is limited. Each highside driver is a power
DMOS transistor with an internal parasitic reverse diode from each
output to VS (bulk-drain-diode). Each output is over-current and open
load protected.
15, 16, 17, 20,
21, 22, 23, 24,
NC Not connected pins.
29, 30, 34
Figure 2. Configuration diagram (top view)
1
CM
GND
OUT6
OUT1
OUT2
OUT3
Vs
Vs
DI
PWM2
CSN
DO
Vcc
CLK
Vs
NC
NC
NC
GND
2
3
4
5
6
7
8
9
10
PowerSO-36
PowerSSO-36
11
12
13
14
15
16
17
18
35
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND 36
OUT6
NC 34
OUT5
Vs
OUT4
NC
NC
Vs
PWM1
CP
Vs
NC
NC
NC
NC
NC
GND
8/37 Doc ID 14279 Rev 3
L9954 / L9954XP Electrical specifications
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
S
V
CC
V
, V
DI
DO, VCLK
V
CSN, Vpwm1
V
CM
V
CP
I
OUT1,2,3,4,5
I
OUT6
,
2.2 ESD protection
Table 4. ESD protection
All pins ± 2
Output pins: OUT1 - OUT6
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
2. HBM with all unzapped pins grounded.
DC supply voltage -0.3 to28 V
Single pulse t
< 400ms 40 V
max
Stabilized supply voltage, logic supply -0.3 to 5.5 V
Digital input / output voltage -0.3 to V
+ 0.3 V
CC
Current monitor output -0.3 to VCC + 0.3 V
Charge pump output -25 to VS + 11 V
Output current ±5 A
Output current ±10 A
Parameter Value Unit
(1)
(2)
± 8
kV
kV
2.3 Thermal data
Table 5. Operating junction temperature
Symbol Parameter Value Unit
T
j
Operating junction temperature -40 to 150 °C
Doc ID 14279 Rev 3 9/37
Electrical specifications L9954 / L9954XP
Table 6. Temperature warning and thermal shutdown
Symbol Parameter Min. Typ. Max. Unit
T
jTW ON
T
jSD ON
T
jSD OFF
T
jSD HYS
Temperature warning threshold junction
temperature
Thermal shutdown threshold junction
temperature
Thermal shutdown threshold junction
temperature
Thermal shutdown hysteresis 5 °K
2.4 Electrical characteristics
VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin.
Table 7. S u pply
Symbol Parameter Test condition Min. Typ. Max Unit
V
Operating supply voltage
S
range
VS DC supply current
increasing
decreasing
V
= 16V, VCC = 5.3V
S
active mode
OUT1 - OUT6 floating
T
130 150 °C
j
Tj
Tj
150 °C
170 °C
728V
720mA
= 16V, VCC = 0V
V
I
S
V
quiescent supply current
S
VCC DC supply current
I
CC
V
quiescent supply
CC
current
I
+ I
S
1. Guaranteed by design.
Sum quiescent supply
CC
current
S
standby mode
OUT1 - OUT6 floating
T
= -40°C, 25°C
test
T
= 85°C
test
= 16V, VCC = 5.3V
V
S
CSN = V
V
= 16V, VCC = 5.3V
S
CSN = V
(1)
active mode
CC ,
standby mode
CC
OUT1 - OUT6 floating
V
= 16V, VCC = 5.3V
S
CSN = V
CC
standby mode
OUT1 - OUT6 floating
= 130°C
T
test
412µA
625µA
13mA
25 50 µA
50 100 µA
10/37 Doc ID 14279 Rev 3
L9954 / L9954XP Electrical specifications
Table 8. Overvoltage and undervoltage detection
Symbol Parameter Test condition Min. Typ. Max Unit
V
SUV ON
V
SUV OFF
V
SUV hyst
V
SOV OFF
V
SOV ON
V
SOV hyst
V
POR OFF
V
POR ON
V
POR hyst
Table 9. Current monitor output
VS UV-threshold voltage VS increasing 5.7 7.2 V
VS UV-threshold voltage VS decreasing 5.5 6.9 V
VS UV-hysteresis V
SUV ON
- V
SUV OFF
0.5 V
VS OV-threshold voltage VS increasing 18 24.5 V
VS OV-threshold voltage VS decreasing 17.5 23.5 V
VS OV-hysteresis V
SOV OFF
- V
SOV ON
1V
Power-On-reset threshold VCC increasing 4.4 V
Power-On-reset threshold VCC decreasing 3.1 V
Power-On-reset hysteresis V
POR OFF
- V
POR ON
0.3 V
Symbol Parameter Test condition Min. Typ. Max. Unit
V
I
CM,r
I
CM acc
Functional voltage range VCC = 5V 0 4 V
CM
Current monitor output
ratio:
I
CM/IOUT1,4,5,6
Current monitor accuracy
0V ≤ V
0 V
V
CC
I
Out max
≤ 4V, VCC=5V -
CM
≤ V
≤ 3.8V,
CM
= 5V, I
Out,min
=500mA,
= 6A
(FS = full scale= 600
μA)
1
----------------- -
10.000
4% +
1%FS
8% +
2%FS
-
Table 10. Charge pump output
Symbol Parameter Test condition Min. Typ. Max. Unit
= 8V, I
V
V
I
Charge pump output
CP
voltage
Charge pump output
CP
current
S
V
= 10V, I
S
V
≥ 12V, I
S
V
= VS+10V, VS =13.5V 95 150 300 µA
CP
= -60μAVS+6 VS+13 V
CP
= -80μAVS+8 VS+13 V
CP
= -100μAVS+10 VS+13 V
CP
Doc ID 14279 Rev 3 11/37
Electrical specifications L9954 / L9954XP
Table 11. OUT1 - OUT6
Symbol Parameter Test condition Min. Typ. Max. Unit
= 13.5 V, Tj = 25 °C,
V
r
ON OUT1,
r
ON OUT2
r
ON OUT3
r
ON OUT4,
r
ON OUT5
r
ON OUT6
I
OUT1
I
OUT2
I
OUT3
I
OUT1
I
OUT2
I
OUT3
I
OUT4
I
OUT5
I
OUT6
t
d ON H
t
d OFF H
t
d ON L
t
d OFF L
t
d HL
On-resistance to supply
or GND
On-resistance to supply
On-resistance to supply
Output current limitation
to GND
Output current limitation
to supply
Output current limitation
to GND
Output current limitation
to GND
Output delay time,
highside driver On
Output delay time,
highside driver Off
Output delay time,
lowside driver On
Output delay time,
lowside driver Off
Cross current protection
time, source to sink
S
I
OUT1,2,3
= ± 0.8A
VS = 13.5 V, Tj = 125 °C,
I
OUT1,2,3
V
S
I
OUT4,5
= ± 0.8 A
= 13.5 V, Tj = 25 °C,
= −0.8 A
VS = 13.5 V, Tj = 125 °C,
I
= −0.8 A
OUT4,5
VS = 13.5 V, T
= − 3 A
I
OUT6
= 25 °C,
j
VS = 13.5 V, Tj = 125 °C,
I
= −3 A
OUT6
Source, V
Sink, V
Source, V
Source, V
=13.5 V,
V
S
corresponding lowside
=13.5 V -3.0 -1.5 A
S
=13.5 V 1.5 3.0 A
S
=13.5 V -3.0 -1.5 A
S
=13.5 V -10.5 -6 A
S
20 40 80 µs
driver is not active
=13.5 V 50 150 300 µs
V
S
=13.5 V,
V
S
corresponding highside
15 30 70 µs
driver is not active
=13.5 V 80 150 300 µs
V
S
t
CC ONLS_OFFHS
- td
OFF H
(1)
800 1100 m
1250 1700 m
500 700 m
700 950 m
100 150 m
150 200 m
200 400 µs
Ω
Ω
Ω
Ω
Ω
Ω
t
d LH
I
QLH
Cross current protection
time, sink to source
Switched-off output
current highside drivers of
OUT1-6
t
CC ONHS_OFFLS
V
mode
V
12/37 Doc ID 14279 Rev 3
OFF L
(1)
200 400 µs
0-2-5µA
- td
= 0V, standby
OUT1-6
= 0V, active mode -40 -15 0 µA
OUT1-6
L9954 / L9954XP Electrical specifications
Table 11. OUT1 - OUT6 (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
I
dV
dV
dV
1. t
I
QLL
OLD123
I
OLD45
I
OLD6
t
d OL
t
ISC
f
rec0
f
rec1
OUT123
OUT45
OUT6
CC ON
Switched-off output
current lowside drivers of
OUT1-3
Open load detection
current of OUT1, OUT2
and OUT3
Open load detection
current of OUT4 and
OUT5
Open load detection
current of OUT6
Minimum duration of
open load condition to set
the status bit
Minimum duration of
over-current condition to
switch off the driver
Recovery frequency for
OC recovery duty cycle
bit=0
Recovery frequency for
OC recovery duty cycle
bit=1
/dt
Slew rate of OUT
OUT
/dt
/dt
45
Slew rate of OUT
is the switch on delay time t
123
6
V
mode
V
= VS, standby
OUT1-3
= VS, active mode -40 -15 0 µA
OUT1-3
0 80 120 µA
Source and sink 15 40 60 mA
Source and sink 15 40 60 mA
Source 30 150 300 mA
500 3000 µs
10 100 µs
14kHz
26kHz
VS =13.5 V
and
= 16.8 Ω
R
load
VS =13.5 V
= 4.5 Ω
R
load
if complement in half bridge has to switch Off.
d ON
0.08 0.2 0.4 V/µs
0.08 0.2 0.4 V/µs
2.5 SPI - electrical characteristics
(VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin).
Table 12. Delay time from standby to active mode
Symbol Parameter Test condition Min. Typ. Max. Unit
Switching from standby to active mode.
t
set
Delay time
Time until output drivers are enabled
after CSN going to high.
Doc ID 14279 Rev 3 13/37
160 300 µs
Electrical specifications L9954 / L9954XP
Table 13. Inputs: CSN, CLK, PWM1/2 and DI
Symbol Parameter Test condition Min. Typ. Max. Unit
V
V
V
inHyst
I
CSN in
I
CLK in
I
DI in
I
PWM1 in
C
Input low level VCC = 5V 1.5 2.0 V
inL
Input high level VCC = 5V 3.0 3.5 V
inH
Input hysteresis VCC = 5V 0.5 V
Pull up current at input CSN V
Pull down current at input CLK V
= 3.5V VCC = 5V -40 -20 -5 µA
CSN
= 1.5V 10 25 50 µA
CLK
Pull down current at input DI VDI = 1.5V 10 25 50 µA
Pull down current at input
PWM1
Input capacitance at input
(1)
in
CSN, CLK, DI and PWM1/2
V
PWM
0 V < V
= 1.5V 10 25 50 µA
< 5.3V 10 15 pF
CC
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 14. DI timing
(1)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
CLK
t
CLKH
t
CLKL
t
set CSN
Clock period VCC = 5V 1000 ns
Clock high time VCC = 5V 400 ns
Clock low time VCC = 5V 400 ns
CSN setup time, CSN low
before rising edge of CLK
V
= 5V 400 ns
CC
t
set CLK
t
set DI
t
hold DI
t
r in
t
f in
CLK setup time, CLK high
before rising edge of CSN
DI setup time VCC = 5V 200 ns
DI hold time VCC = 5V 200 ns
Rise time of input signal DI,
CLK, CSN
Fall time of input signal DI,
CLK, CSN
V
= 5V 400 ns
CC
V
= 5V 100 ns
CC
= 5V 100 ns
V
CC
1. DI timing parameters tested in production by a passed / failed test:
Tj= -40°C / +25°C: SPI communication @ 2MHz.
Tj= +125°C SPI communication @ 1.25 MHz.
Table 15. D O
Symbol Parameter Test condition Min. Typ. Max. Unit
V
V
DOL
DOH
Output low level VCC = 5 V, ID = -2mA 0.2 0.4 V
Output high level VCC = 5 V, ID = 2 mA V
-0.4 VCC-0.2 V
CC
14/37 Doc ID 14279 Rev 3
L9954 / L9954XP Electrical specifications
Table 15. DO (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
= VCC,
V
I
C
DOLK
DO
Tristate leakage current
Tristate input
(1)
capacitance
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16. DO timing
Symbol Parameter Test condition Min. Typ. Max. Unit
CSN
0V < V
V
CSN
0V < V
< V
DO
= VCC,
< 5.3V
CC
CC
-10 10 µA
10 15 pF
t
r DO
t
f DO
t
en DO tri L
t
dis DO L tri
t
en DO tri H
t
dis DO H tri
t
d DO
Table 17. CSN timing
DO rise time CL = 100 pF, I
DO fall time CL = 100 pF, I
DO enable time
from tristate to low level
DO disable time
from low level to tristate
DO enable time
from tristate to high level
DO disable time
from high level to tristate
DO delay time
CL = 100 pF, I
pull-up load to V
CL = 100 pF, I
pull-up load to V
CL =100 pF, I
pull-down load to GND
CL = 100 pF, I
pull-down load to GND
V
< 0.3 VCC, V
DO
= 100pF
C
L
= -1mA 80 140 ns
load
= 1mA 50 100 ns
load
= 1mA
load
load
load
load
CC
= 4 mA
CC
= -1mA
= -4mA
> 0.7VCC,
DO
100 250 ns
380 450 ns
100 250 ns
380 450 ns
50 250 ns
Symbol Parameter Test condition Min. Typ. Max. Unit
t
CSN_HI,stb
t
CSN_HI,min
CSN HI time, switching from
standby mode
CSN HI time, active mode
Transfer of SPI-command
to Input Register
Transfer of SPI-command
to input register
20 µs
4µs
Doc ID 14279 Rev 3 15/37
Electrical specifications L9954 / L9954XP
Figure 3. SPI - transfer timing diagram
CSN high to low: DO enabled
CSN high to low: DO enabled
CSN high to low: DO enabled
CSN
CSN
CSN
time
time
time
01
01
CLK
CLK
CLK
DI
DI
DI
DO
DO
DO
Input
Input
Input
Data
Data
Data
Register
Register
Register
X
X
X
123456 70
123456 70
123456 70
DI: data will be accepted on the rising edge of CLK signal
DI: data will be accepted on the rising edge of CLK signal
DI: data will be accepted on the rising edge of CLK signal
123 45670
123 45670
123 45670
DO: data will change on the falling edge of CLK signal
DO: data will change on the falling edge of CLK signal
DO: data will change on the falling edge of CLK signal
123 45670
123 45670
123 45670
fault bit
fault bit
fault bit
transfered to output power switches
transfered to output power switches
transfered to output power switches
X
XX
XX
XX
XX
CSN low to high: actual data is
CSN low to high: actual data is
CSN low to high: actual data is
old data new data
old data new data
old data new data
232221201918
232221201918
232221201918
232221201918
232221201918
232221201918
01
time
time
time
0 1
0 1
0 1
time
time
time
01
01
01
time
time
time
time
time
time
Figure 4. SPI - input timing
CSN
0.8 VCC
0.2 VCC
t
set C SN
t
CLKH
t
se t CLK
0.8 VCC
CLK
0.2 VCC
t
set DI
t
hold DI
t
CLKL
0.8 VCC
DI
Valid
Va lid
0.2 VCC
16/37 Doc ID 14279 Rev 3
L9954 / L9954XP Electrical specifications
t
f
f
t
t
Figure 5. SPI - DO valid data delay time and valid time
t
in
CLK
t
r DO
DO
(low to high)
t
d DO
t
DO
DO
(high to low)
Figure 6. SPI - DO enable and disable time
f in r in
CSN
r i n
0.8 VCC
0.5 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
50%
0.2 VCC
DO
50%
pull-up load to VCC
C = 100 pF
L
DO
t t
en DO tri L
dis DO L tri
50%
pull-down load to GND
C = 100 pF
L
t t
Doc ID 14279 Rev 3 17/37
Electrical specifications L9954 / L9954XP
CS
Figure 7. SPI - driver turn on / off timing, minimum CSN HI time
N low to high: data from shift register
is transferred to output power switches
t
r in f in
t
CSN_HI,min
CSN
t
dOFF
output current
of a driver
output current
of a driver
ON state OFF state
t
OFF
t
dON
t
ON
OFF state
Figure 8. SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
ON state
t
80%
50%
20%
80%
50%
20%
80%
50%
20%
CSN
time
CLK
time
DI
time
DI: data is not accepted
DO
0
-
time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
18/37 Doc ID 14279 Rev 3
L9954 / L9954XP Application information
3 Application information
3.1 Dual power supply: VS and V
The power supply voltage VS supplies the half bridges and the highside drivers. An internal
charge-pump is used to drive the highside switches. The logic supply voltage V
5 V) is used for the logic part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be
lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (V
increases from undervoltage to V
CC
internally generated power-on-reset (POR). If the voltage V
minimum threshold (V
POR ON
= 3.4 V), the outputs are switched to tristate (high impedance)
and the status registers are cleared.
3.2 Standby mode
The standby mode of the L9954 is activated by clearing the bit 23 of the Input Data Register
0. All latched data will be cleared and the inputs and outputs are switched to high
impedance. In the standby mode the current at V
CSN = high (DO in tristate). By switching the V
be achieved. If bit 23 is set, the device will be switched to active mode.
3.3 Inductive loads
Each half bridge is built by an internally connected highside and a lowside power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The highside
drivers OUT4 to OUT6 are intended to drive resistive loads. Hence only a limited energy
(E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L>100μH) an external free-wheeling diode connected to GND and the
corresponding output is needed.
CC
POR OFF
CC
(stabilized
CC
= 4.2 V) the circuit is initialized by an
decreases under the
CC
(VCC) is less than 6 µA (50µA) for
S
voltage a very low quiescent current can
3.4 Diagnostic functions
All diagnostic functions (over/open load, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32 µs (open load: 1ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Open
load and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the overload condition will disable the
corresponding driver (over-current) and overtemperature will switch off all drivers (thermal
shutdown). Without setting the over-current recovery bits in the Input Data register, the
microcontroller has to clear the over-current status bits to reactivate the corresponding
drivers.
Doc ID 14279 Rev 3 19/37
Application information L9954 / L9954XP
3.5 Overvoltage and undervoltage detection
If the power supply voltage VS rises above the overvoltage threshold V
V), the outputs OUT1 to OUT6 are switched to high impedance state to protect the load.
When the voltage V
drops below the undervoltage threshold V
S
SUV OFF
voltage), the output stages are switched to the high impedance to avoid the operation of the
power devices without sufficient gate driving voltage (increased power dissipation). If the
supply voltage V
recovers (register 0: bit 20=0) to normal operating voltage the outputs
S
stages return to the programmed state after at least 32 µs.
If the undervoltage/overvoltage recovery disable bit is set, the automatic turn-on of the
drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers. It is strongly recommended to set bit 20 to avoid a possible high current oscillation in
case of a shorted output to GND and low battery voltage.
3.6 Charge pump
The charge pump runs under all conditions in normal mode. In standby the charge pump is
out of action.
3.7 Temperature warning and thermal shutdown
If junction temperature rises above T
µs and is detectable via the SPI. If junction temperature increases above the second
threshold T
, the thermal shutdown bit will be set and power DMOS transistors of all
j SD
output stages are switched off to protect the device after at least 32 µs. Temperature
warning flag and thermal shutdown bit are latched and must be cleared by the
microcontroller. The related bit is only cleared if the temperature decreases below the
trigger temperature. If the thermal shutdown bit has been cleared the output stages are
reactivated.
a temperature warning flag is set after at least 32
j TW
SOV OFF
(typical 21
(UV-switch-OFF
3.8 Open-load detection
The open load detection monitors the load current in each activated output stage. If the load
current is below the open load detection threshold for at least 1 ms (t
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open load status without
changing the mechanical/electrical state of the loads.
3.9 Over load detection
In case of an over-current condition a flag is set in the status register in the same way as
open load detection. If the over-current signal is valid for at least t
current flag is set and the corresponding driver is switched off to reduce the power
20/37 Doc ID 14279 Rev 3
dissipation and to protect the integrated circuit. If the over-current recovery bit of the output
is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
) the corresponding
dOL
= 32 µs, the over-
ISC
L9954 / L9954XP Application information
3.10 Current monitor
The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. Signal at
output CM is blanked after switching on of driver until correct settlement of circuitry (at least
for 32 µs).
The bits 18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4,
OUT5 and OUT6 will be multiplexed to the current monitor output. The current monitor
output allows a more precise analysis of the actual state of the load rather than the detection
of an open- or overload condition. For example this can be used to detect the motor state
(starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster
more precise by measuring the load current. The current monitor output is bidirectional (c.f.
PWM inputs).
3.11 PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit in Input Data Register 1 is set , the output is controlled by
the logically AND-combination of the PWM signal and the output control bit in Input Data
Register 0. The outputs OUT1-OUT4 and OUT6 are controlled by the PWM1 input and the
output OUT5 is controlled by the bidirectional input CM/PMW2. For example, the two PWM
inputs can be used to dim two lamps independently by external PWM signals.
3.12 Cross-current protection
The three half-bridges of the device are cross-current protected by an internal delay time. If
one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge
will be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver will be changed
to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to
this behavior it is always guaranteed that the previously activated driver is totally turned-off
before the opposite driver will start to conduct.
Doc ID 14279 Rev 3 21/37
Application information L9954 / L9954XP
3.13 Programmable softstart function to drive loads with higher inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 15% ...25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition. The PWM frequency settles at 1.5 kHz
or 3 kHz. The device itself cannot distinguish between a real overload and a non linear load
like a light bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.
Figure 9. Example of programmable softstart function for inductive loads
22/37 Doc ID 14279 Rev 3
L9954 / L9954XP Functional description of the SPI
4 Functional description of the SPI
4.1 Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPIcommunication cycle.
Note: In contrast to the SPI-standard the least significant bit (LSB) will be transferred first
(see Figure 3).
4.2 Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started. The state when CSN is going low until the rising
edge of CSN will be called a communication frame. If the CSN-input pin is driven above
7.5V, the L9954 will go into a test mode. In the test mode the DO will go from tri-state to
active mode.
4.3 Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register. The writing to the selected Data Input Register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety function
is implemented to avoid an activation of the output stages by a wrong communication frame.
Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
4.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
Doc ID 14279 Rev 3 23/37
Functional description of the SPI L9954 / L9954XP
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.5 Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
4.6 Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of
the two Input Registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected Input Data
Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents
of the selected status register will be transferred to DO during the current communication
frame. Bit 1-17 controls the behavior of the corresponding driver.
If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to
control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status
registers. The bits in the status registers will be cleared after the current communication
frame (rising edge of CSN).
4.7 Status register
This devices uses two status registers to store and to monitor the state of the device. No
error bit (bit 0) is used as a fault bit and is a logical-NOR combination of bits 1-22 in both
status registers. The state of this bit can be polled by the microcontroller without the need of
a full SPI-communication cycle. If one of the over-current bits is set, the corresponding
driver will be disabled. If the over-current recovery bit of the output is not set the
microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown
bit is set, all drivers will go into a high impedance state. Again the microcontroller has to
clear the bit to enable the drivers.
24/37 Doc ID 14279 Rev 3
L9954 / L9954XP Functional description of the SPI
4.8 SPI - Input data and status registers
Table 18. SPI - input data and status registers 0
Input register 0 (write) Status register 0 (read)
Bit
Name Comment Name Comment
If Enable Bit is set the
A broken VCC-or SPIconnection of the L9954 can
be detected by the
microcontroller, because all 24
bits low or high is not a valid
frame.
23 Enable bit
device switches in active
mode. If Enable Bit is
cleared the device goes
into standby mode and all
bits are cleared. After
power-on reset device
starts in standby mode.
Always 1
If Reset Bit is set both
22 Reset bit
status registers will be
cleared after rising edge of
CSN input.
V
overvoltage
S
In case of an overvoltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated. If
OC recovery
duty cycle
21
0: 12% 1: 25%
This bit defines in
combination with the overcurrent recovery bit (Input
Register 1) the duty cycle
in over-current condition of
V
undervoltage
S
VS voltage recovers to normal
operating conditions outputs
are reactivated automatically
(if Bit 20 of status register 0 is
not set).
an activated driver.
In case of a thermal shutdown
all outputs are switched off.
The microcontroller has to
clear the TSD bit by setting the
Reset Bit to reactivate the
outputs.
The TW bit can be used for
thermal management
by the microcontroller to avoid
a thermal shutdown. The
microcontroller has to clear the
TW bit.
After switching the device from
standby mode to active mode
an internal timer is started to
allow chargepump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this bit
Overvoltage/
Undervoltage
20
recovery
19
Current monitor
select bits
18
disable
If this bit is set the
microcontroller has to
clear the status register
after undervoltage /
overvoltage event to
enable the outputs.
Depending on
combination of bit 18 and
19 the current image
(1/10.000) of the selected
HS-output will be
multiplexed to the CM
output:
Bit 19Bit
18
Output
00 OUT6
10 OUT1
01 OUT4
11 OUT5
Thermal
shutdown
Temperature
warning
Not ready bit
is controlled by internal clock it
can be used for synchronizing
testing events (e.g. measuring
filter times).
Doc ID 14279 Rev 3 25/37
Functional description of the SPI L9954 / L9954XP
Table 18. SPI - input data and status registers 0 (continued)
Input register 0 (write) Status register 0 (read)
Bit
Name Comment Name Comment
17
OUT6 – HS
on/off
OUT6 – HS
over-current
16 x (don’t care) 0
15
14
OUT5 – HS
on/off
OUT4 – HS
on/off
OUT5 – HS
over-current
OUT4 – HS
over-current
If a bit is set the selected
13 x (don’t care) 0
12 x (don’t care) 0
11 x (don’t care) 0
10 x (don’t care) 0
9 x (don’t care) 0
8 x (don’t care) 0
7 x (don’t care) 0
OUT3 – HS
6
5
on/off
OUT3 – LS
on/off
output driver is switched
on. If the corresponding
PWM enable bit is set
(Input Register 1) the
driver is only activated if
PWM1 (PWM2) input
signal is high. The outputs
of OUT1-OUT3 are half
bridges. If the bits of HSand LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
OUT3 – HS
over-current
OUT3 – LS
over-current
avoid a high internal
4
3
2
OUT2 – HS
on/off
OUT2 – LS
on/off
OUT1 – HS
on/off
current from VS to GND.
OUT2 – HS
over-current
OUT2 – LS
over-current
OUT1 – HS
over-current
In case of an over-current
event the corresponding status
bit is set and the output driver
is disabled. If the over-current
Recovery Enable bit is set
(Input Register 1) the output
will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable
duty cycle (Bit 21).
If the over-current recovery bit
is not set the microcontroller
has to clear the over-current
bit (Reset Bit) to reactivate the
output driver.
OUT1 – LS
1
on/off
0 0 No error bit
26/37 Doc ID 14279 Rev 3
OUT1 – LS
over-current
A logical NOR-combination of
all bits 1 to 22 in both status
registers.
L9954 / L9954XP Functional description of the SPI
Table 19. SPI - input data and status registers 1
Bit
Input register 1 (write) Status register 1 (read)
Name Comment Name Comment
23 Enable bit
OUT6 OC
22
Recovery
Enable
If Enable bit is set the device
will be switched in active mode.
If Enable Bit is cleared device
goes into standby mode and all
bits are cleared. After poweron reset device starts in
standby mode.
Always 1
VS overvoltage
A broken VCC-or SPIconnection of the L9954
can be detected by the
microcontroller, because
all 24 bits low or high is
not a valid frame.
In case of an overvoltage
or undervoltage event
the corresponding bit is
set and the outputs are
deactivated. If Vs voltage
21 x (don’t care) VS undervoltage
recovers to normal
operating conditions
outputs are reactivated
automatically.
In case of a thermal
shutdown all outputs are
20
19
OUT5 OC
Recovery
Enable
OUT4 OC
Recovery
Enable
In case of an over-current
event the over-current status
bit (Status Register 0) is set
and the output is switched off.
If the over-current Recovery
Enable bit is set the output will
be automatically reactivated
after a delay time resulting in a
PWM modulated current with a
programmable duty cycle (Bit
21 of Input Data Register 0).
Depending on occurrence of
Overcurrent Event and internal
clock phase it is possible that
one recovery cycle is executed
even if this bit is set to zero.
Thermal shutdown
Temperature
warning
switched off. The
microcontroller has to
clear the TSD bit by
setting the Reset Bit to
reactivate the outputs.
The TW bit can be used
for thermal management
by the microcontroller to
avoid a thermal
shutdown. The
microcontroller has to
clear the TW bit.
After switching the
device from standby
mode to active mode an
internal timer is started
to allow chargepump to
settle before the outputs
can be activated. This bit
18 x (don’t care) Not ready bit
is only present during
start up time.
Since this bit is
controlled by internal
clock it can be used for
synchronizing testing
events(e.g. measuring
filter times).
Doc ID 14279 Rev 3 27/37
Functional description of the SPI L9954 / L9954XP
Table 19. SPI - input data and status registers 1 (continued)
Bit
17 x (don’t care)
16 x (don’t care) 0
15 x (don’t care)
OUT3 OC
14
Recovery
Enable
OUT2 OC
13
Recovery
Enable
OUT1 OC
12
Recovery
Enable
OUT6 PWM1
11
Enable
10 x (don’t care) 0
OUT5 PWM2
9
8
Enable
OUT4 PWM1
Enable
7 x (don’t care) 0
6 x (don’t care)
5 x (don’t care)
4 x (don’t care)
OUT3 PWM1
3
2
1
Enable
OUT2 PWM1
Enable
OUT1 PWM1
Enable
0 1 No Error bit
Input register 1 (write) Status register 1 (read)
Name Comment Name Comment
OUT6 – HS
open load
OUT5 – HS
open load
After 50ms the bit can be
cleared. If over-current
condition still exists, a wrong
OUT4 – HS
open load
load can be assumed.
0
The open load detection
monitors the load current
0
in each activated output
stage. If the load current
is below the open load
0
detection threshold for at
least 1 ms (t
dOL
) the
corresponding open load
bit is set. Due to
0
mechanical/electrical
inertia of typical loads a
short activation of the
outputs (e.g. 3ms) can
be used to test the open
load status without
changing the
mechanical/electrical
state of the loads.
If the PWM1/2 Enable Bit is set
and the output is enabled
(Input Register 0) the output is
switched on if PWM1/2 input is
high and switched off if
PWM1/2 input is low. OUT5 is
controlled by PWM2 input. All
other outputs are controlled by
PWM1 input.
0
OUT3 – HS
open load
OUT3 – LS
open load
OUT2 –HS
open load
OUT2– LS
open load
OUT1 – HS
open load
OUT1 – LS
open load
A logical NORcombination of all bits 1
to 22 in both status
registers.
28/37 Doc ID 14279 Rev 3
L9954 / L9954XP Packages thermal data
5 Packages thermal data
Figure 10. Packages thermal data
Doc ID 14279 Rev 3 29/37
Package and packing information L9954 / L9954XP
6 Package and packing information
6.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.
6.2 PowerSO-36™ package information
Figure 11. PowerSO-36™ package dimensions
.
30/37 Doc ID 14279 Rev 3
L9954 / L9954XP Package and packing information
Table 20. PowerSO-36™ mechanical data
Millimeters
Symbol
Min. Typ. Max.
A 3.60
a1 0.10 0.30
a2 3.30
a3 0 0.10
b 0.22 0.38
c 0.23 0.32
D * 15.80 16.00
D1 9.40 9.80
E 13.90 14.5
E1 * 10.90 11.10
E2 2.90
E3 5.80 6.20
e0.65
e3 11.05
G 0 0.10
H 15.50 15.90
h 1.10
L 0.8 1.10
M
N 10 deg
R
s8 deg
Doc ID 14279 Rev 3 31/37
Package and packing information L9954 / L9954XP
6.3 PowerSSO-36™ package information
Figure 12. PowerSSO-36™ package dimensions
Table 21. PowerSSO-36™ mechanical data
Millimeters
Symbol
Min. Typ. Max.
A- -2.45
A2 2.15 - 2.35
a1 0 - 0.1
b 0.18 - 0.36
c 0.23 - 0.32
D * 10.10 - 10.50
E * 7.4 - 7.6
e-0.5-
e3 - 8.5 -
F-2.3-
G- -0.1
G1 - - 0.06
H 10.1 - 10.5
h--0.4
k0°-8°
L 0.55 - 0.85
N - - 10 deg
32/37 Doc ID 14279 Rev 3
L9954 / L9954XP Package and packing information
Table 21. PowerSSO-36™ mechanical data (continued)
Symbol
Min. Typ. Max.
X4.3 - 5.2
Y6.9 - 7.5
Millimeters
6.4 PowerSO-36™ packing information
TM
Figure 13. PowerSO-36
tube shipment (no suffix)
Doc ID 14279 Rev 3 33/37
Package and packing information L9954 / L9954XP
TM
Figure 14. PowerSO-36
tape and reel shipment (suffix “TR”)
TAPE DIMENSIONS
A0 15.20 ± 0.1
B0 16.60 ± 0.1
K0 3.90 ± 0.1
K1 3.50 ± 0.1
F 11.50 ± 0.1
P1 24.00 ± 0.1
W 24.00 ± 0.3
All dimensions are in mm.
REEL DIMENSIONS
Base Qty 600
Bulk Qty 600
A (max) 330
B (min) 1.5
C (±0.2) 13
D (min) 20.2
G (+2 / -0) 24.4
N (min) 60
T (max) 30.4
34/37 Doc ID 14279 Rev 3
L9954 / L9954XP Package and packing information
6.5 PowerSSO-36™ packing information
TM
Figure 15. PowerSSO-36
C
B
A
Figure 16. PowerSSO-36
tube shipment (no suffix)
Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6
All dimensions are in mm.
TM
tape and reel shipment (suffix “TR”)
Reel dimensions
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2
End
All dimensions are in mm.
Start
Top
cover
tape
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
No componentsNo components Components
500mm min
Doc ID 14279 Rev 3 35/37
Revision history L9954 / L9954XP
7 Revision history
Table 22. Document revision history
Date Revision Description of changes
23-Jan-2008 1 Initial release.
Table 21: PowerSSO-36™ mechanical data:
– Deleted A (min) value
24-Jun-2009 2
17-May-2010 3
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows
Table 21: PowerSSO-36™ mechanical data:
– Changed X: minimum value from 4.1 to 4.3 and maximum value
from 4.7 to 5.2
– Changed Y: minimum value from 6.5 to 6.9 and maximum value
from 7.1 to 7.5
36/37 Doc ID 14279 Rev 3
L9954 / L9954XP
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Doc ID 14279 Rev 3 37/37
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