ST L9952GXP User Manual

L9952GXP

Power management system IC

Features

■Two 5V low-drop voltage regulators (250mA, 100mA continuous mode

■Low stand-by current: VBAT stby, 7µA; ,V1 stby, 45µA, (75µA in cycl. sense)

■Window watchdog and fail-safe output

■Interrupt output

■Wake-up logic with cyclic contact monitoring

■LIN 2.1 compliant (SAEJ2602 compatible) transceiver

■24 bit SPI interface for mode control and diagnostic

■Output drivers

■4 High side drivers for e.g. LED or HALL (RDSon,typ = 7 Ω )

■1 High side driver Out_HS ( RDSon,typ = 1 Ω )

■2 Relay drivers ( RDSon,typ = 2 Ω )

■Outputs are short circuit protected

■2 Op amp's for current sensing in GND return lines

■Temperature warning and thermal shutdown

PowerSSO-36

Applications

■Automotive ECU’ s such as door zone and body control modules.

Description

The L9952GXP is a power management system IC containing two low drop regulators with advanced contact monitoring and additional peripheral functions.

The integrated standard serial peripheral interface (SPI) controls all L9952GXP operation modes and provides driver diagnostic functions.

Table 1.	Device summary
	Package		Order codes
		Tube		Tape and reel
	PowerSSO-36	L9952GXP		L9952GXPTR

July 2009

Doc ID 13518 Rev 5

1/68

www.st.com

Contents	L9952GXP

Contents

1	Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.1	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

2.1.1 Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.2 Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2	Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	2.2.1	Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.2.2	Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.2.3	V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.2.4	VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
2.3	Wake up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
2.4	Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
2.5	Wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
2.6	Hall sensor ports: WU3,4, Dig_Out 3,4 . . . . . . . . . . . . . . . . . . . . . . . . . .		16
2.7	Interrupt	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
2.8	Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
2.9	Window – watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
2.10	Fail safe output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
2.11	Reset – generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
2.12	V1, V2 fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
2.13	Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
2.14	PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
2.15	Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
2.16	LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
2.17	Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	2.17.1	Dominant TxD time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	2.17.2	Short to battery time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	2.17.3	Short to ground mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
2.18	Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	2.18.1	Normal wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	2.18.2	Wake up from short to GND condition . . . . . . . . . . . . . . . . . . . . . . . . . .	22

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L9952GXP	Contents

2.18.3 RxD pin in V1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.19 LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20.1 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20.2 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20.3 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20.4 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20.5 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3	Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
	3.1	Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25

3.1.1 Over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25 3.3 SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 High side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
5	ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
6	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
	6.1	Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	6.2	Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . .	30
	6.3	Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
7	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		34
	7.1	Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	7.2	Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
	7.3	Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
	7.4	Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
	7.5	Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	7.6	Reset generator (V1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
	7.7	Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37

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Contents	L9952GXP

7.8 High side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

		7.8.1	Output (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
		7.8.2	Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
	7.9	Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
	7.10	Wake up inputs ( WU1..WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
	7.11	Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
	7.12	LIN . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
	7.13	Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		47
	7.14	SPI . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
		7.14.1	Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
		7.14.2	Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
		7.14.3	Input PWM 2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
		7.14.4	DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
		7.14.5	DO, FSO, Dig_Out3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
		7.14.6	DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
		7.14.7	CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
8	SPI control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			54
	8.1	SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		54

8.1.1 Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.2 Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.1.3 Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.1.4 Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1.5 Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9	Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		64
	9.1	ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64
	9.2	PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64
	9.3	PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		67

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L9952GXP	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pins definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10. Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11. Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 12. Power-on Reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 13. Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 14. Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 15. Reset generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 16. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 17. High side outputs (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 18. High side outputs (OUT 1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 19. Relay drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 20. Wake up inputs(WU1...WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 21. Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 22. LIN receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 23. LIN DC parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 24. LIN transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 25. LIN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 26. LIN DC values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 27. Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 28. SPI (Input CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 29. Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30. Input PWM2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 31. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 32. DO, FSO, Digout3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 33. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 34. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 35. SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 36. Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 37. Configuration bit HSxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 38. Configuration bit OUT_HSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 39. Configuration bit RELx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 40. Configuration bit On_V2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 41. Configuration bit TRIG, GO_VBAT, GO_V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 42. Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 43. Configuration bit Wx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 44. Configuration bit Ux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 45. Configuration bit Lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 46. Configuration bit Txx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 47. Configuration bit INT_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 48. Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 49. Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and TXD_TOUT. . . . . . . 59

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List of tables	L9952GXP

Table 50. Configuration bit LEVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 51. Configuration bit ICxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 52. Configuration bit LIN slope, LS_ovuv and ICMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 53. Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 54. Configuration bit HSx_OL, HSx_OC and Relx_OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 55. Configuration bit SHT5V2, WUx, INH, LIN and Cold Start . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 56. Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 57. Configuration bit OV, UV, TW, TSDx and Vx Fail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 58. Configuration bit STx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 59. Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD . . . . . . . . . . . . . 63 Table 60. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 61. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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L9952GXP	List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. Operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. FSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. NReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Lin master pull up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 9. PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 10. PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area (V1 ON) . . . . . 32 Figure 11. PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON) . . . . . . . . . . . . 32 Figure 12. PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 13. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 14. Watchdog, closed and open window tolerances and save trigger area . . . . . . . . . . . . . . . 39 Figure 15. LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 16. SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 17. SPI - Edges timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 18. SPI - CSN low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 19. SPI - High to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 20. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 21. PowerSSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 22. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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Pin definitions and functions	L9952GXP

1 Pin definitions and functions

Figure 1. Block diagram

			VBat
				Vs			VBat
			Vs			VS
		V2		Temp Prewarning
			Voltage	& Shutdown
		220nF	Regulator 2
				Undervoltage-
				Overvoltage -
CAN	CAN			Shutdown			M
		INH	Wake Up IN
					Rel1	R
			Vs	Low Side
				Output Clamp	C
		V1	Voltage
						R
					Rel2
			Regulator 1	Low Side
		220nF
				Output Clamp	C
			Voltage
			Monitor
		PWM1		+	OP1+
					OP1-
		PWM2		-
					OP1out
		NReset
	Microcontroller	CSN	Window	+	OP2+	µC (ADC)
			Watchdog		OP2-
		CLK		-
					OP2out
		DI	SPI	LOGIC
		DO
							e. g. Bulb,
					OUT_HS
		Dig_Out3		High Side			LED, Hall
							Sensor
		Dig_Out4 /
		Interrupt			Out1
		TxD		High Side
		RxD			Out2
			LIN 2.1 1)	High Side			e. g. LED,
		LINPU
			SAEJ2602				Hall Sensor
					Out3
				High Side
LIN		LIN
For detailed information			1) LIN 2.1 certified		Out4
		WU3		High Side
see
	ESDLIN1524BJ		Wake Up IN				Cyclic Contact
EMC test report from
IBEE Zwickau					WU1		Monitoring
		WU4		Wake Up IN
			Wake Up IN
		FSO		Wake Up IN	WU2
	Fail-safe Logic
				GND

Table 2.	Pins definitions and functions
Pin		PowerSS0-36	Function
name
GND		1	Ground
V2		2	Voltage regulator 2 output : 5 V supply for external loads e.g. IR
			receiver, potentiometer
V1		3	Voltage regulator 1 output : 5 V supply e.g. micro controller, Can
			transceiver
NReset		4	NReset output to micro controller - Internal pull-up of typ. 100KΩ
			( reset state = low )
INH		5	Wake-up input e.g. from CAN transceiver
RxD		6	Receiver output of the LIN 2.1 transceiver

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L9952GXP				Pin definitions and functions
	Table 2.	Pins definitions and functions (continued)
	Pin		PowerSS0-36	Function
	name
	TxD		7	Transmitter input of the LIN 2.1 transceiver
	OP2+		8	Non inverting input of operational sense amplifier
	OP2-		9	Inverting input of operational sense amplifier
	OP2OUT		10	Output of operational sense amplifier
	DI		11	SPI : serial data input
	DO		12	SPI : serial data output
	CLK		13	SPI : serial clock input
	CSN		14	SPI : chip select not input
	PWM1		15	Pulse width modulation input
	PWM2		16	Pulse width modulation input
	Dig_Out3		17	Digital output
	Dig_Out4/INT		18	Digital output (configurable as Interrupt Output)
	Wu4..1		19 to 22	Wake-up input: input pins for static or cyclic monitoring of external
				contacts
	OP1OUT		23	Output of operational sense amplifier
	OP1-		24	Inverting input of operational sense amplifier
	OP1+		25	Non inverting input of operational sense amplifier
	Out4..1		26 to 29	High side driver (7 Ω, typ.) - to supply e.g. LED’ s, HALL sensors or
				external contacts
	Out_HS		30	High side drivers (1 Ω, typ.) - to supply e.g. LED’ s, Bulbs, HALL
				sensors or external contacts
	Vs		31	Power supply voltage
	LINPU		32	LIN master pull up
	LIN		33	LIN bus line
	Rel1		34	Low side driver (2 Ω, typ.) - e.g. relay
	Rel2		35	Low side driver (2 Ω, typ.) - e.g. relay
				Fail safe output - used to supervise or control applications in case of
	FSO		36	watchdog and/or V1 under-voltage failure (e.g. to activate
				emergency lights)

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Pin definitions and functions	L9952GXP

Figure 2. Pins configuration

GND 1

36

FSO

V2 2

PowerSSO-

36

35

REL2

V1 3

34

REL1

NRESET 4

33

LIN

INH 5

32

LINPU

RxD 6

31

Vs

TxD 7

30

OUT_HS

OP2+ 8

L9952GXP

29

OUT 1

OP2 - 9

28

OUT 2

OPOUT2 10

27

OUT 3

DI 11

26

OUT 4

DO 12

25

OP1+

CLK 13

24

OP1-

CSN 14

23

OPOUT1

PWM1 15

22

WU1

PWM2 16

21

WU2

Dig_Out 3 17

TAB = GND

20

WU3

Dig_Out4/ INT 18

19

WU4

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L9952GXP	Description

2 Description

2.1Voltage regulator

The L9952GXP contains 2 independent and fully protected low drop voltage regulators, which are designed for very fast transient response.

The output voltage is stable with loads capacitors > 220nF.

2.1.1Voltage regulator: V1

The voltage regulator V1 provides 5V supply voltage and up to 250mA continuous load current for the external digital logic (micro controller, CAN transceiver ...). In addition the regulator V1 drives the L9952GXP internal 5V loads. The voltage regulator is protected against overload and over-temperature. An external reverse current protection has to be provided by the application circuitry to prevent the output capacitor from being discharged by negative transients or low input voltage. The output voltage precision is better than +/-2% (incl. temperature drift and line-/load regulation) for operating mode; respectively +/-3% during low current mode. Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors > 220nF.

If device Temperature exceeds TSD1 threshold, all outputs (Hsx, Lsx, V2, LIN) will be deactivated except V1. Hence the micro controller has the possibility for interaction or error logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V1 will be deactivated (see state chart Fig. 3.1: “Protection and diagnosis”). A timer is started and the voltage regulator is deactivated for tTSD = 1sec. During this time, all other wakeup sources (CAN, LIN, and WU1...4) are disabled. After 1 sec, the voltage regulator will try to restart automatically. If TSD2 occurs within one minute and for 8 consecutive times, the L9952GXP enters the VBAT - standby mode.

In case of short to GND at “V1” after initial turn on (V1 < 2V for at least 4ms) the L9952GXP enters the VBAT - standby mode. Reactivation (wake-up) of the device can be achieved with signals from CAN, LIN, WU1..4, SPI.

2.1.2Voltage regulator: V2

The voltage regulator V2 supplies additional 5V loads (e.g. Logic components, external sensors, external potentiometers). The continuous load current is 50mA. The regulator provides accuracy better than + 3% @ 50mA (4% @ 100mA) load current.

In case of short to GND at “V2” after initial turn on (V2 < 2V for at least 4ms) the V2 regulator is switched off. Micro processor has to send a clear command to reactivate the V2 regulator.

V2 is protected against:

●Overload

●Over temperature

●Short circuit (short to ground and battery supply voltage)

●Reverse biasing

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Description	L9952GXP

2.2Power control in operating modes

The L9952GXP can be operated in 4 different operating modes:

●Active

●Flash

●V1- standby

●VBAT - standby

Acyclic monitoring of wake-up inputs is available in stand-by modes.

2.2.1Active mode

All functions are available.

2.2.2Flash mode

	To disable the watchdog feature a FLASH program mode is available.
	The mode can be entered by VPWM2 ≥ 9V
	In this case all other functions are the same as in active mode
	Watchdog can be disabled as well as soon as L9952GXP enters the V1 standby mode (see
	section 2.9 for details)
Note:	“High” level for flash mode selection is VPWM2 ≥ 9V. For all other operation modes, standard
	5V logic signals are required. For proper operation PWM1 must not be set to a voltage level
	above standard 5V logic.

2.2.3 V1 standby mode

Outputs and internal loads are switched off. To supply the micro controller in a low power mode, the voltage regulator1 (V1) remains active. The intention of the V1 standby mode is to preserve the RAM contents. A cyclic contact supply and wake-up input sense feature (for cyclic monitoring of external contacts) can be activated by SPI.

2.2.4 VBAT standby mode

To achieve minimum current consumption during VBAT standby mode, all L9952GXP functions (except the ones for wake up functionality) are switched off.

In VBAT - standby mode the current consumption of the L9952GXP is reduced to 7µA, typical (without cyclic sense feature selected).

The transitions from active mode to either V1-standby or VBAT - standby are controlled by SPI.

VBAT - standby mode is dominant; i.e. if both bits, V1 - standby and VBAT - standby are set to “1”, the L9952GXP will enter VBAT - standby mode.

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L9952GXP	Description

2.3Wake up events

A wake-up from standby mode will switch the device to active mode. This can be initiated by one or more of the following sources:

●Change of the LIN state at LIN bus interfaces

●A current at the INH pin (I ≥200uA) controlled by the CAN-transceiver (the CAN transceiver is not a part of the IC).

●Positive/negative edge at wake up pins WU1...WU4 -> change of level after going into stand-by

●Change of open-load state at OUT1 to 4

●SPI access in V1-standby mode (CSN is low and first rising edge on CLK)

Table 3. Wake up events

	Wake up source	Description
	LIN	Always active
	INH	Always active
	WU1...4	Can be individually disabled via SPI
	Open Load at HS outputs	Can be individually disabled via SPI
	SPI Access	Always active
		(except in VBAT - standby mode)
	High level at PWM2 input	VPWM2 > 9V (1)

1. Only if internal oscillator is running (e. g. in cyclic sense configuration or after wake-up request).

All wake-up events (except wake-up by LIN, INH or SPI from V1standby mode) generate a Reset pulse (NReset low for 2ms).

Wake-up events from V1standby by LIN, INH or SPI do not cause a Reset and the Reset generation is blocked for 2ms, i. e. a watchdog failure during this timeframe will not cause a reset.

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Description	L9952GXP

2.4Functional overview (truth table)

Table 4.		Functional overview (truth table)
					Operating modes
		Function	Comments	Active mode		V1-standby	VBAT-standby
						static mode		static mode
						(cyclic sense)		(cyclic sense)
2.3.1		Voltage-regulator, V1	VOUT= 5V	On		On (1)		Off
2.3.2		Voltage-regulator, V2	VOUT= 5V	On / Off (2)		On (2) / Off		On (2) / Off
2.3.3		Reset-generator		On		On		Off
						Off if
2.3.4		Window watchdog	V1 monitor	On		(I_V1 < ICMP		Off
						and ICMP=0)
						or ICMP = 1
2.3.5		Wake up		Off (3)		Active (4)		Active (4)
2.3.6		HS-cyclic supply	Oscillator	On / Off		On (2) / Off		On (2) / Off
			timebase
2.3.7		Relay driver		On		Off		Off
2.3.8		Operational amplifiers		On		Off		Off
2.3.9		LIN line driver	LIN 2.1	On		Off		Off
2.3.10		LIN line receiver		On		On		On
			Fail-safe	Hi – no error		Hi – no error		Lo -> because
2.3.11		FSO		Lo – WD or V1		Lo – WD or V1
			output					V1= off
				fail		fail (5)
2.3.12		Oscillator		On		(6)		(6)
2.3.13		Vs-Monitor		On		(7)		(7)

1.Supply the processor in low current mode

2.Only active when selected via SPI

3.Input Status can be read by SPI (Status Register 0); Inputs should be configured for static sense (Control Register 2)

4.Unless disabled by SPI

5.Watchdog is active in V1 standby mode, until I(V1) is below ICMP current threshold

6.Activation = ON if cyclic sense is selected

7.Cyclic activation = pulsed ON during cyclic sense

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L9952GXP	Description

Figure 3. Operating modes, main states

Flash Mode

Watchdog: OFF

Vpwm2>9V

Note 1

Vpwm2>9V

Vpwm2<7V

SPI command: ‚Go Vbat’ (D20 CR0) OR

Thermal Shutdown

OR

V1 fail (V1 < 2,5V for 4ms after POR)

		=> short to GND
		Or
		15 x WD Failure
	Vpwm2>9V	Wake-up
		Event
	Note 1

Vs > Vpor

Vbat startup

All registers cleared to ‚0',

Cold start bit (D19, SR0) set to ‚1'

Active

Mode

V1: on

Reset Generator: active

Watchdog: active

Fail Safe Out: active

Wake-up	SPI command: ‚Go Vcc’
Event	(D21 CR0)

		V1: on
V1: off		Reset Generator: active
V2: according to SPI settings		Watchdog:
Reset Generator: off (Nreset=low)	Thermal Shutdown TSD2	OFF (if Iv1<Icmp or ICMP = 1)
Watchdog: off		Fail Safe Out: active
Vbat Standby		V1 Standby
Mode		Mode
Fail Safe Out: low	OR IV1 > 1mA AND ICMP = 0 AND 15 x WD fail
HSD, LSD: Off
Note 1: only if internal oscillator is running

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Description	L9952GXP

2.5Wake up inputs

The de-bounced digital inputs WU1...WU4 can be used to wake up the L9952GXP from standby modes. These inputs are sensitive to any level transition (positive and negative edge)

For static contact monitoring, a filter time of 64 µs is implemented at WU1-4. The filter is started when the input voltage passes the specified threshold. At Vin > 1V and Vin < (Vs – 2V), a Wake-up request is processed. During Wake-up request, the internal oscillator and other circuit blocks are activated in order to allow more accurate monitoring of the inputs.

In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a cyclic wake up feature is implemented. This feature allows periodical activation of the wakeup inputs to read the status of the external contacts. The periodical activation can be linked to Timer 1 (0.5sec to 4.0sec in 0.5sec steps) or Timer 2 (50ms). The input signal is filtered with a filter time of 16us after a programmable delay (80us or 800us). A Wake-up will be processed if the status has changed versus the previous cycle.

The Outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the timing according to the cyclic monitoring of the wake-up inputs.

If the wake-up inputs are configured for cyclic sense mode (Icxx in control register 2), the same input filter timing (Timer1 or Timer2) and the corresponding input filter delay (control register 2) must be used for the HS Outputs (Hsxx in control register 0) which supply the external contact switches.

In Standby mode, the inputs WU1-4 are SPI configurable for pull-up or pull-down current source configuration according to the setup of the external contacts (pull-up for active low contacts, pull-down for active high contacts). In active mode the inputs have a pull down resistor of 100 kOhm (typ).

In Active mode, the input status can be read by SPI (Status Register 0). Static sense should be configured (Control Register 2) before the read operation is started (In cyclic sense configuration, the input status is updated according to the cyclic sense timing; Therefore, reading the input status in this mode may not reflect the actual status).

2.6Hall sensor ports: WU3,4, Dig_Out 3,4

Applications like Hall sensor outputs need high processing speed. The 12V signals connected to the wakeup inputs WU3 and WU4 can be looped through to the digital outputs Dig_Out 3 and Dig_Out 4 (5V) in order to avoid read out of the input state by SPI.

The setup is programmable by SPI.

The open load states of the High Side Drivers OUT1 and OUT2 can be looped through the digital outputs Dig_Out3 and Dig_Out4 without delay. In addition, the status of OUT1 and OUT2 can be accessed through the SPI interface. This feature is intended for 2-pin HALL sensors. Open Load information is only valid during ON state.

The Open Load threshold at pins OUT1...4 can be switched from IOLD1 = 2mA to

IOLD2 = 8 mA via SPI .

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Doc ID 13518 Rev 5

L9952GXP	Description

2.7Interrupt

Dig_Out4 can be configured via SPI as Interrupt output (INT) by setting Bit 20 / CR1:INT_enable=’1’.

This configuration will enable the following behaviour:

●INT pin is pulled high for 2ms in case of any wake-up from V1 standby mode (WU inputs, LIN, INH, SPI, open load HS, Iv1 > ICMP_ris)

●Wake-up events from V1 standby do not generate a reset (i.e. NRESET is not pulled low)

●The Dig_Out4 settings in CR1 (Bits 12..14) will be ignored

2.8Cyclic contact supply

	In V1 and VBAT - standby mode, any high side driver output (OUT1..4, OUTHS) can be used
	to periodically supply external contacts.
	The timing is selectable by SPI
	Timer 1: period is X sec, the on-time is 10ms resp. 20ms
	With X {0.5, 1.0, 1.5, ... 4 }
	Timer 2: period is 50ms, the ontime is 100us resp. 1ms:
Note:	Cyclic sense setup: if cyclic sense feature is used for wake-up inputs (Icxx in control register
	2), same input filter timing (Timer1 or Timer2) must be used for HS Outputs (Hsxx in control
	register 0).

2.9 Window – watchdog

During normal operation the watchdog monitors the micro controller within a nominal trigger cycle of 10ms.

In VBAT -standby , V1-standby and Flash program modes, the watchdog circuit is automatically disabled. However, the watchdog will remain enabled in V1-standby mode until the current at V1 decreases below ICMP_fall. The V1 current monitoring can be disabled, if the ICMP bit (CR2, D20) is set to '1'.

After ‘power-on’, ‘standby mode’ or reset, the window watchdog starts with a long open window (65ms). The long open window allows the micro controller to run its own setup and then to trigger the watchdog via the SPI. The trigger is finally accepted when the CSN input becomes HIGH after the transmission of the SPI word.

A correct watchdog trigger will start the window watchdog with a closed window (< 6ms) followed by an open window (< 10ms), see timing diagrams. Subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit (CR0, D19). The “negative” or “positive” edge has to meet the open window time. A correct watchdog trigger signal will immediately start the next closed window.

After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. In case of 7 further watchdog failures, the V1 regulator is completely turned off and the device goes into VBAT -standby mode until a wakeup occurs. (e.g. via LIN, CAN/INH).

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Description	L9952GXP

The watchdog is triggered by toggling the trigger bit (CR0, D19).

Note: The active trigger window will be reset after each correct trigger write operation. In case of reset (NReset low for 2ms) the trigger bit is set to “0”.

In case of a WD failure, the outputs (Lsx, Hsx, V2) are switched off and NReset is pulled low for 2ms.

Writing to control register 0 without inverting the WD trigger bit is possible at any time.

Figure 4. Watchdog

Watchdog Failure

Wake up event

	Vbatstdby
	Mode
		8+7	Toggle WD Trigger Bit
		WD Failures
V1 off			Within nominal window
for 200ms
t=200ms	8x WD Failure
			Watchdog active
			With
			Normal window
			(10ms)
Reset			HSD, LSD : according to
(Nreset =low for 2ms)			CR0
LSD: Off (control bits set to 0')‚
HSD: Off (control bits remain
unchanged)
Watchdog Failure (‚long
open window’ passed
without TRIG=1			Set WD Trigger Bit = ‚1' or
2ms			toggle trigger bit if wake-up
			from V1standby

Wake-up event or exit Flash Mode

Power-on

Reset

Watchdog active with

‚long open window’ (65ms nom)

HS and LS outputs are off

Go to standby mode or

Flash Mode (PWM2>9V)

INH, LIN, SPI

I(V1)>1mA and ICMP=0

Go to standby mode

or Flash Mode (PWM2>9V)

Set

WD Trigger Bit = ‚0' or write non-inverting value to trigger bit after wake-up from V1standby mode

Watchdog

Inactive

(standby modes, Flash Mode)

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Doc ID 13518 Rev 5

L9952GXP	Description

2.10Fail safe output

After power-on (Vs > VPOR) or wakeup from VBAT -standby mode, the output FSO is set to “HIGH”, if V1 is above the V1 threshold. FSO is set to “LOW” in case of V1 under voltage or

watchdog failure.

During V1-standby mode, FSO is HIGH unless a V1 under-voltage or watchdog reset occurs. WD remains enabled in V1 standby mode until IV1 drops below 150uA. In VBAT - standby mode, FSO is low. At exit from VBAT - standby mode, it goes to high as soon as V1 is stable.

At wakeup FSO remains high, provided that the watchdog is triggered successfully. It is set low if the watchdog is not served during the long open window of if a V1 under-voltage occurs.

Figure 5. FSO

V1 undervoltage

TSD2	Watchdog Failure

Vbatstdby Mode

FSO = 0

2.11Reset – generator

IF V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output “NRESET” is switched to “HIGH” after a 2ms reset delay time. This is necessary for a defined start of the micro controller when the application is switched on.

As soon as an under voltage condition of the output voltage (V1 < VRT) for more than 8us appears, the reset output is switched low again.

Figure 6. NReset

V1 Undervoltage

Wake-up Event 1)

Vpwm2 < 9V	Watchdog
(Exit Flash Mode)	Failure

NReset = 0

1) Only if

(INT_en = 0) and (wake-up by WU-input or High Side Open Load)

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Description	L9952GXP

2.12V1, V2 fail

The V1, and V2 regulator output voltages are monitored.

In case of a drop below the V1, V2 – fail thresholds (V1,2 < 2V,typ for t > 2us), the V1,2 - fail bits are latched. The fail bits are cleared by a dedicated SPI command.

If 4ms after turn on of the regulator the V1,2 voltage is below the V1,2 fail thresholds, (independent for V1,2 ), the L9952GXP will identify a short circuit condition at the related regulator output and the regulator will be switched off.

In case of a V1 failure the device enters VBAT - standby mode automatically.

In case of a V2 failure the SHT5V2 bit (SR0 Bit12) is set.

2.13Low side driver outputs Rel1, Rel2

The outputs Rel1, Rel2 (RDSon = 2 Ω typ. @25 °C) are specially designed to drive relay loads.

Typical relays used have the following characteristics:

Relay type 1:

–closed armature: R = 160 Ω +10%, L= 300mH

–open armature: R = 160 Ω +10%, L= 240mH

Relay type 2:

–closed armature: R= 220 Ω +10%, L= 420mH

–open armature: R= 220 Ω +10%, L= 330mH

The outputs provide an active output zener clamping (40V) feature for the demagnetisation of the relay coil, even though a load dump condition exists. In case of watchdog failure the relay drivers will be switched off and the low side driver control bits are cleared.

Note: 1 Due to relays bouncing, high dV/dt and/or dI/dt transients may occur on the low side driver outputs. In case high currents are switched (for example window lift motor), due to parasitic capacitive inductive coupling from load side of relays to the relays coils, the Absolute Maximum Ratings of the Low Side driver outputs may be exceeded. In order to avoid this, it is recommended to place a 10nF capacitor at the Rel1, Rel2 outputs to GND.

2If a hard short circuit to VBAT is possible at the "Low Side Driver" outputs, an RC network is required with TRC > 1µs, R ≥ 1 Ω (see block diagram, the value is given for an output short circuit of given di/dt = 5A/µs).

2.14PWM inputs

The inputs PWM 1,2 can be used to control the output drivers Out1..4 and OUT_HS with a PWM signal. Each PWM input can be mapped individually to each of the above listed outputs according to the SPI settings.

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L9952GXP	Description

2.15Operational amplifiers

The operational amplifiers are especially designed to be used for sensing and amplifying the voltage drop across ground connected shunt resistors. Therefore the input common mode range includes - 0.2 ... 3V.

The operational amplifiers are designed for GND + 3V... GND – 0.2V input voltage swing and rail-to-rail output voltage range. All Pins (positive, negative and outputs ) are available to be able to operate in non-inverting and inverting mode. Both operational amplifiers are on-chip compensated for stability over the whole operating range within the defined load impedance.

Figure 7. Lin master pull up

LIN

Vs

con t r ol

TS W

LIN PU

con trol

3 0 k

1 k

Ma ster node

LIN

pu ll u p

Gn d

A dedicated built-in switch “Tsw” enables the LIN to act as a master. (see chapter 2.18)

2.16LIN bus interface

General requirements:

●Speed communication up to 20kbit/s

●LIN 2.0 compliant (SAEJ2602 compatible) transceiver

●Function range from +40V to -18V DC at LIN Pin

●GND disconnection fail safe at module level

●Off mode: does not disturb network

●GND shift operation at system level

●Microcontroller Interface with CMOS compatible I/O pins.

●Pull up resistor internal.

●ESD: immunity against automotive transients per ISO7637 specification (see application note)

●Matched output slopes and propagation delay

In order to further reduce the current consumption in standby mode, the integrated LIN bus interface offers an ultra low current consumption.

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