Datasheet L9950, L9950XP Datasheet (ST)

L9950

L9950XP

Door actuator driver

Features

■ One full bridge for 6A load (R

■ Two half bridges for 3A load (R

■ Two half bridges for 1.5A load (R

■ One highside driver for 6A load (R

■ Four highside drivers for 1.5 A load

(R

=800 mΩ )

on

■ Programmable softstart function to drive loads

with higher inrush currents (i.e. current
>6 A,>3 A,>1.5 A)

■ Very low current consumption in standby mode

(I

< 6 μA typ; ICC <25 μA typ; Tj ≤ 85 °C)

S

■ All outputs short circuit protected

■ Current monitor output for 300 mΩ, 150 mΩ

and 100 m highside drivers

■ All outputs over temperature protected

■ Open load diagnostic for all outputs

■ Overload diagnostic for all outputs

■ Seperated half bridges for door lock motor

■ PWM control of all outputs

■ Charge pump output for reverse polarity

protection

=150 mΩ )

on

=300 mΩ )

on

=800 mΩ )

on

=100 mΩ )

on

PowerSO-36

PowerSSO-36

Applications

■ Door actuator driver with bridges for door lock

and safe lock, mirror axis control, mirror fold
and highside driver for mirror defroster and four
10W-light bulbs.

Description

The L9950 and L9950XP are microcontroller
driven multifunctional door actuator driver for
automotive applications.Up to five DC motors and
five grounded resistive loads can be driven with
six half bridges and five highside drivers. The
integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
diagnostic informations are available via SPI.

Table 1. Device summary

Order codes

Package

PowerSO-36 L9950 L9950TR

PowerSSO-36 L9950XP L9950XPTR

June 2009 Doc ID 10311 Rev 10 1/39

Part number (tube) Part number (tape and reel)

www.st.com

1

Contents L9950 - L9950XP

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10

2.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.5 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 21

3.7 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.8 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.11 Cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.12 Programmable soft start function to drive loads with higher inrush current .
22

4 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.6 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/39 Doc ID 10311 Rev 10

L9950 - L9950XP Contents

4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.8 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2 PowerSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4 PowerSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.5 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 10311 Rev 10 3/39

List of tables L9950 - L9950XP

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9. Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11. OUT1 - OUT11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 12. Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13. Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 14. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 15. DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 16. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 17. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 18. Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 19. SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20. SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. PowerSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 22. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4/39 Doc ID 10311 Rev 10

L9950 - L9950XP List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4. SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. SPI - driver turn-on/off timing, minimum csn hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. Example of programmable soft start function for inductive loads . . . . . . . . . . . . . . . . . . . . 23

Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. PowerSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. PowerSSO-36 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. PowerSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. PowerSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 10311 Rev 10 5/39

Block diagram and pin description L9950 - L9950XP

1 Block diagram and pin description

Figure 1. Block diagram

V

BAT

* Note: Value of capacitor has to be choosen carefully to limit the VS
voltage below absolute maximum ratings in case of an unexpected

freewheeling condition of inductive loads (e.g. TSD, POR)

Reverse

Polarity

Protection

100k

VREG

VCC

*

100µF

100nF

EMC

Optimization

100 10

100nF

**

1k

**

1k

**

1k

**

1k

**

1k

+

PWM1

DO
CLK
CSN

DI

VCC

VS

Charge

Pump

SPI

CP

Interface

µC

CM / PWM2

**

1k

Table 2. Pin definitions and functions

MUX

10k

xy-Mirror

OUT1

Motors

OUT2

M

OUT3

M

OUT4

M

Lock

OUT5

Safe Lock

OUT6

OUT7

OUT8

Driver Interface & Diagnostic

GND

** Note: Resistors between µC and L9950 are recommended to limit currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse)

+ Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior

OUT9

OUT10

OUT11

5

M

Folder

M

Exterior Light

Footstep Light

Safety Light

Turn Indicator

Defroster

Pin Symbol Function

Ground.

1, 18, 19, 36 GND

Reference potential.
Important: for the capability of driving the full current at the outputs all

pins of GND must be externally connected.

Highside driver output 11.
The output is built by a highside switch and is intended for resistive

loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy

2, 35 OUT11

which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the
output to VS (bulk-drain-diode). The output is over-current and open
load protected.

Important: for the capability of driving the full current at the outputs both
pins of OUT11 must be externally connected.

6/39 Doc ID 10311 Rev 10

L9950 - L9950XP Block diagram and pin description

Table 2. Pin definitions and functions (continued)

Pin Symbol Function

Hal bridge output 1,2,3.

3
4
5

OUT1
OUT2

OUT3

6, 7, 14, 15,

23, 24, 25, 28,

VS

29, 32

8DI

9

CM/PWM2

The output is built by a highside and a lowside switch, which are
internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal parasitic reverse diode
(bulk-drain-diode: highside driver from output to VS, lowside driver from
GND to output). This output is over-current and open load protected.

Power supply voltage (external reverse protection required.
For this input a ceramic capacitor as close as possible to GND is

recommended.
Important: for the capability of driving the full current at the outputs all

pins of VS must be externally connected.

Serial data input.
The input requires CMOS logic levels and receives serial data from the

microcontroller. The data is an 24bit control word and the least
significant bit (LSB, bit 0) is transferred first.

Current monitor output/PWM2 input.
Depending on the selected multiplexer bits of Input Data Register this

output sources an image of the instant current through the
corresponding highside driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overdrive the current monitor
signal to provide a second PWM input for the outputs OUT9 and
OUT10.

Chip select not input/test mode.
This input is low active and requires CMOS logic levels. The serial data

10 CSN

transfer between L9950 and micro controller is enabled by pulling the
input CSN to low level. If an input voltage of more than 7.5V is applied
to CSN pin the L9950 will be switched into a test mode.

Serial data output.

11 DO

The diagnosis data is available via the SPI and this tristate output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high).

Logic supply voltage.

12 VCC

For this input a ceramic capacitor as close as possible to GND is
recommended.

Serial clock input.

13 CLK

This input controls the internal shift register of the SPI and requires
CMOS logic levels.

16,17, 20,21,

22

OUT4
OUT5
OUT6

Half bridge output 4,5,6: see OUT1 (pin 3).
Important: for the capability of driving the full current at the outputs both

pins of OUT4 (OUT5, respectively) must be externally connected.

Charge pump output.

26 CP

This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection

Doc ID 10311 Rev 10 7/39

Block diagram and pin description L9950 - L9950XP

Table 2. Pin definitions and functions (continued)

Pin Symbol Function

PWM1 input.

27 PWM1

This input signal can be used to control the drivers OUT1-OUT8 and
OUT11 by an external PWM signal.

Highside driver output 7,8,9,10.

30
31
33
34

OUT7,
OUT8,
OUT9,

OUT10

The output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the
output to VS (bulk-drain-diode). The output is over-current and open
load protected.

Figure 2. Configuration diagram (top view)

GND 1

OUT11 2

OUT1 3

OUT2 4

OUT3 5

VS 6

VS 7

DI

CM/PWM2 9

CSN 10

DO 11

VCC 12

CLK 13

VS 14

VS 15

OUT4 16

OUT4

GND 18

GND36

Power SO36

8

Chip

17

Leadframe

OUT1135

OUT1034

OUT933

VS32

31 OUT8

30

OUT7

VS

29

VS28

PWM127

CP26

VS25

VS24

VS23

OUT622

OUT521

OUT5

20

GND19

8/39 Doc ID 10311 Rev 10

L9950 - L9950XP Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

S

V

CC

V

, V

DI

DO, VCLK

V

CSN, Vpwm1

V

CM

V

CP

I

OUT1,2,3,6,7,8,9,10

I

OUT4,5,11

,

2.2 ESD protection

Table 4. ESD protection

Output pins: OUT1 - OUT11 ±8

1. HBM according to CDF-AEC-Q100-002.

2. HBM with all unzapped pins grounded.

DC supply voltage -0.3 to 28 V

Single pulse t

< 400 ms 40 V

max

Stabilized supply voltage, logic supply -0.3 to 5.5 V

Digital input/output voltage -0.3 to V

+ 0.3 V

CC

Current monitor output -0.3 to VCC + 0.3 V

Charge pump output -25 to VS + 11 V

Output current ±5 A

Output current ±10 A

Parameter Value Unit

All pins ±4

(1)

(2)

kV

kV

2.3 Thermal data

Table 5. Thermal data

Symbol Parameter Value Unit

T

j

Operating junction temperature -40 to 150 °C

Doc ID 10311 Rev 10 9/39

Electrical specifications L9950 - L9950XP

2.4 Temperature warning and thermal shutdown

Table 6. Temperature warning and thermal shutdown

Symbol Parameter Min. Typ. Max. Unit

T

jTW ON

T

jTW OFF

T

jTW HYS

T

jSD ON

T

jSD OFF

T

jSD HYS

Temperature warning threshold junction
temperature

Temperature warning threshold junction
temperature

Temperature warning hysteresis - 5 - °K

Thermal shutdown threshold junction
temperature

Thermal shutdown threshold junction
temperature

Thermal shutdown hysteresis - 5 - °K

2.5 Electrical characteristics

VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified.

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.

Table 7 . Suppl y

Symbol Parameter Test condition Min. Typ. Max. Unit

V

I

IS + I

Operating supply voltage

S

range

VS DC supply current

I

S

VS quiescent supply current

VCC DC supply current

CC

VCC quiescent supply
current

Sum quiescent supply

CC

current

increasing

decreasing

increasing

decreasing

V

= 16 V, VCC = 5.3 V

S

active mode
OUT1 - OUT11 floating

VS = 16 V, VCC = 0 V
standby mode
OUT1 - OUT11 floating

=-40 °C, 25 °C

T

test

V

= 16 V, VCC = 5.3 V

S

CSN = V

= 16 V, VCC = 5.3 V

V

S

CSN = V

active mode

CC ,

standby mode

CC

OUT1 - OUT11 floating

=-40 °C, 25 °C

T

test

= 16 V, VCC = 5.3 V

V

S

CSN = V

CC

standby mode
OUT1 - OUT11 floating

=-40 °C, 25 °C

T

test

Tj

Tj

Tj

Tj

--150°C

130 - - °C

--170°C

150 - - °C

7-28V

-720mA

- 4 12 µA

-13mA

-2550µA

-3175µA

10/39 Doc ID 10311 Rev 10

L9950 - L9950XP Electrical specifications

0

-

Table 8. Overvoltage and under voltage detection

Symbol Parameter Test condition Min. Typ. Max. Unit

V

SUV ON

V

SUV OFF

V

SUV hyst

V

SOV OFF

V

SOV ON

V

SOV hyst

V

POR OFF

V

POR ON

V

POR hyst

Table 9. Current monitor output

VS UV-threshold voltage VS increasing 5.9 - 7.2 V

VS UV-threshold voltage VS decreasing 5.5 - 6.5 V

VS UV-hysteresis V

SUV ON

- V

SUV OFF

-0.5- V

VS OV-threshold voltage VS increasing 18 - 24.5 V

VS OV-threshold voltage VS decreasing 17.5 - 22 V

VS OV-hysteresis V

SOV OFF

- V

SOV ON

-1-V

Power-on-reset threshold VCC increasing - - 4.4 V

Power-on-reset threshold VCC decreasing 3.1 - - V

Power-on-reset hysteresis V

POR OFF

- V

POR ON

-0.3- V

Symbol Parameter Test condition Min. Typ. Max. Unit

V

I

CM,r

I

CM acc

Functional voltage range VCC = 5 V 0 4 V

CM

Current monitor output
ratio:

I

CM/IOUT1,4,5,6,11

Current monitor accuracy

0V ≤ V

CM

0V ≤ V

CM

= 5 V, I

V

CC

I

Out4,5,11,max

I

Out1,6,max

≤ 4V, VCC=5V - - -

≤ 3.8 V,

=500 mA,

Out,min

= 5.9 A

-

= 2.9 A

1

-----------------

10.00

4% +

1%FS

8% +

2%FS

(FS = full scale= 600 µA)

-

Table 10. Charge pump output

Symbol Parameter Test condition Min. Typ. Max. Unit

V

= 8 V, I

V

I

Charge pump output

CP

voltage

Charge pump output

CP

current

S

= 10 V, I

V

S

V

≥ 12 V, ICP = -100 µA 10 - 13 V

S

V

= VS+10 V, VS =13.5 V 95 150 300 µA

CP

= -60 µA 6 - 13 V

CP

= -80 µA 8 - 13 V

CP

Doc ID 10311 Rev 10 11/39

Electrical specifications L9950 - L9950XP

Table 11. OUT1 - OUT11

Symbol Parameter Test condition Min. Typ. Max. Unit

VS = 13.5 V, Tj = 25 °C,
I

= ± 1.5A

OUT1,6

V

r

ON OUT1,

r

ON OUT6

On-resistance to supply or
GND

= 13.5 V, Tj = 125 °C,

S

I

= ± 1.5 A

OUT1,6

V

= 8.0 V, Tj = 25 °C,

S

I

= ± 1.5 A

OUT1,6

VS = 13.5 V, Tj = 25 °C,
I

= ± 0.8A

OUT2,3

V

r

ON OUT2,

r

ON OUT3

r

ON OUT4,

r

ON OUT5

r

ON OUT7,

r

ON OUT8,

r

ON OUT9 ,

r

ON OUT10

r

ON OUT11

|I

OUT1

|I

OUT6

|I

OUT2

|I

OUT3

|I

OUT4

|I

OUT5

|I

OUT7

|I

OUT8

|I

OUT9

|I

OUT10

On-resistance to supply or
GND

On-resistance to supply or
GND

On-resistance to supply

On-resistance to supply

|,

Output current limitation to

|

supply or GND

Output current limitation to

|,

|

supply or GND

Output current limitation to

|,

|

supply or GND

|,

Output current limitation to

|,

GND

|,

|

= 13.5 V, Tj = 125 °C,

S

I

= ± 0.8 A

OUT2,3

V

= 8.0 V, Tj = 25 °C,

S

I

= ± 0.8 A

OUT2,3

VS = 13.5 V, T

= ± 3.0 A

I

OUT4,5

V

= 13.5 V, Tj = 125 °C,

S

= ± 3.0 A

I

OUT4,5

V

= 8.0 V, Tj = 25 °C,

S

= ± 3.0 A

I

OUT4,5

= 13.5 V, Tj = 25 °C,

V

S

I

OUT7,8,9,10

V

= 13.5 V, Tj = 125 °C,

S

I

OUT7,8,9,10

V

= 8.0 V, Tj = 25 °C,

S

I

OUT7,8,9,10

= 13.5 V, Tj = 25 °C,

V

S

= - 3.0 A

I

OUT11

V

= 13.5 V, Tj = 125 °C,

S

= - 3.0A

I

OUT11

V

= 8.0 V, Tj = 25 °C,

S

= - 3.0 A

I

OUT11

= 25 °C,

j

= -0.8 A

= -0.8 A

= -0.8 A

Sink and source,
VS=13.5V

Sink and source,

= 13.5V

V

S

Sink and source,

= 13.5V

V

S

Source, V

= 13.5V 1.5 - 2.5 A

S

-300400mΩ

-450600mΩ

-300400mΩ

- 800 1100 mΩ

- 1250 1700 mΩ

- 800 1100 mΩ

-150200mΩ

-225300mΩ

-150200mΩ

- 800 1100 mΩ

- 1250 1700 mΩ

- 800 1100 mΩ

-100150mΩ

-150200mΩ

-100150mΩ

3-5A

1.5 - 2.5 A

6-10A

12/39 Doc ID 10311 Rev 10

L9950 - L9950XP Electrical specifications

Table 11. OUT1 - OUT11 (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

|I

OUT11

t

d ON H

t

d OFF H

t

d ON L

t

d OFF L

t

D HL

t

D LH

I

QLH

I

QLL

I

OLD1

Output current limitation to

|

GND

Output delay time,
highside driver on

Output delay time,
highside driver off

Output delay time,
lowside driver on

Output delay time,
lowside driver off

Cross current protection time,
source to sink

Cross current protection time,
sink to source

Switched-off output current
highside drivers of OUT1-11

Switched-off output current
lowside drivers of OUT1-6

Open load detection current
of OUT1

Source, V

= 13.5V 6 - 10 A

S

VS = 13.5 V,
corresponding lowside

20 40 80 µs

driver is not active

VS = 13.5 V 50 150 300 µs

VS = 13.5 V,
corresponding highside

15 30 70 µs

driver is not active

VS = 13.5 V 80 150 300 µs

t

d ON L

t

d ON H

V

OUT1-11

mode

V

OUT1-11

mode

V

OUT1-6

mode

V

OUT1-6

- t

d OFF H,

- t

d OFF L

=0 V, standby

=0 V, active

= VS, standby

= VS, active mode -40 -15 0 µA

-200400µs

-200400µs

0-2-5µA

-40 -15 0 µA

0110180µA

53080mA

I

OLD23

I

OLD45

I

OLD6

Open load detection current
of OUT2, OUT3

Open load detection current
of OUT4 and OUT5

Open load detection current
of OUT6

15 40 60 mA

60 150 300 mA

30 70 150 mA

Open load detection current

I

OLD78910

of OUT7, OUT8, OUT9,

15 40 60 mA

OUT10

I

OLD11

Open load detection current
of OUT11

30 150 300 mA

Minimum duration of open

t

dOL

t

ISC

load condition to set the
status bit

Minimum duration of over­current condition to switch off

500 - 3000 µs

10 - 100 µs

the driver

Doc ID 10311 Rev 10 13/39

Electrical specifications L9950 - L9950XP

Table 11. OUT1 - OUT11 (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

=13.5 V

dV

OUT16

dV

OUT23

dV

OUT78910

dV

OUT45

dV

OUT11

/dt Slew rate of OUT1,OUT6

/dt,

Slew rate of OUT2/3 and

/dt

OUT7-OUT10

/dt Slew rate of OUT4, OUT5

/dt Slew rate of OUT11

S

I

load

= 13.5 V

V

S

I

load

V

= 13.5 V

S

I

load

V

= 13.5 V

S

I

load

= ±1.5 A

= -0.8 A

= ±3.0 A

= 3.0 A

0.1 0.2 0.4 V/µs

0.09 0.2 0.4 V/µs

0.1 0.2 0.4 V/µs

0.1 0.2 0.4 V/µs

2.6 SPI - electrical characteristics

VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin.

Table 12. Delay time from standby to active mode

Symbol Parameter Test condition Min. Typ. Max. Unit

Switching from standby to active mode.

t

set

Delay time

Time until output drivers are enabled

- 160 300 µs

after CSN going to high.

Table 13. Inputs: CSN, CLK, PWM1/2 and DI

Symbol Parameter Test condition Min. Typ. Max. Unit

V

V

V

inHyst

I

CSN in

I

CLK in

I

DI in

I

PWM1 in

C

Input low level VCC = 5 V 1.5 2.0 - V

inL

Input high level VCC = 5 V - 3.0 3.5 V

inH

Input hysteresis VCC = 5 V 0.5 - - V

Pull up current at input CSN V

Pull down current at input CLK V

= 3.5 V VCC = 5 V -40 -20 -8 µA

CSN

= 1.5 V 10 25 50 µA

CLK

Pull down current at input DI VDI = 1.5 V 10 25 50 µA

Pull down current at input
PWM1

Input capacitance at input

in

CSN, CLK, DI and PWM1/2

= 1.5 V 10 25 50 µA

V

PWM

V

= 0 to 5.3 V - 10 15 pF

CC

Note: Value of input capacity is not measured in production test. Parameter guaranteed by design.

14/39 Doc ID 10311 Rev 10

L9950 - L9950XP Electrical specifications

Table 14. DI timing

Symbol Parameter Test condition Min. Typ. Max. Unit

t

CLK

t

CLKH

t

CLKL

t

set CSN

t

set CLK

t

set DI

t

hold time

t

t

Clock period VCC = 5 V 1000 - - ns

Clock high time VCC = 5 V 400 - - ns

Clock low time VCC = 5 V 400 - - ns

CSN setup time, CSN low
before rising edge of CLK

CLK setup time, CLK high
before rising edge of CSN

= 5 V 400 - - ns

V

CC

= 5 V 400 - - ns

V

CC

DI setup time VCC = 5 V 200 - - ns

DI hold time VCC = 5 V 200 - - ns

Rise time of input signal DI,

r in

CLK, CSN

Fall time of input signal DI,

f in

CLK, CSN

= 5 V - - 100 ns

V

CC

= 5 V - - 100 ns

V

CC

Note: DI timing parameters tested in production by a passed/failed test:

Tj=-40 °C/+25 °C: SPI communication @2 MHZ.
Tj=+125 °C: SPI communication @1.25 MHZ.

Table 1 5. DO

Symbol Parameter Test condition Min. Typ. Max. Unit

V

V

I

DOLK

C

DO

DOH

Output low level VCC = 5 V, ID = -2 mA - 0.2 0.4 V

DOL

Output high level VCC = 5 V, ID = 2 mA V

V

= VCC,

Tristate leakage current

Tristate input

(1)

capacitance

CSN

0V < V

V

CSN

DO

= VCC,

< V

CC

0V < VCC < 5.3 V

-0.4 VCC-0.2 - V

CC

-10 - 10 µA

-1015pF

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Doc ID 10311 Rev 10 15/39

Electrical specifications L9950 - L9950XP

Table 16. DO timing

Symbol Parameter Test condition Min. Typ. Max. Unit

t

r DO

t

f DO

t

en DO tri L

t

dis DO L tri

t

en DO tri H

t

dis DO H tri

t

d DO

Table 17. CSN timing

DO rise time CL = 100 pF, I

DO fall time CL = 100 pF, I

DO enable time
from tristate to low level

DO disable time
from low level to tristate

DO enable time
from tristate to high level

DO disable time
from high level to tristate

DO delay time

CL = 100 pF, I
pull-up load to V

CL = 100 pF, I
pull-up load to V

CL =100 pF, I
pull-down load to GND

CL = 100 pF, I
pull-down load to GND

V

< 0.3 VCC, V

DO

= 100 pF

C

L

= -1 mA - 80 140 ns

load

= 1 mA - 50 100 ns

load

= 1 mA

load

load

load

load

CC

= 4 mA

CC

= -1 mA

= -4 mA

> 0.7 VCC,

DO

- 100 250 ns

- 380 450 ns

- 100 250 ns

- 380 450 ns

-50250ns

Symbol Parameter Test condition Min. Typ. Max. Unit

t

CSN_HI,stb

t

CSN_HI,min

Minimum CSN HI time,
switching from standby mode

Maximum CSN HI time,
active mode

Transfer of SPI command
to Input Register

Transfer of SPI command
to input register

-2050µs

-24µs

Figure 3. SPI - transfer timing diagram

CSN high to low: DO enabled

CSN high to low: DO enabled

CSN

CSN

CSN

CLK

CLK

CLK

DI

DI

DI

DO

DO

DO

Input

Input

Input
Data

Data

Data

Register

Register

Register

CSN high to low: DO enabled

X

X

X

12345670

12345670

12345670

DI: data will be accepted on the rising edge of CLK signal

DI: data will be accepted on the rising edge of CLK signal

DI: data will be accepted on the rising edge of CLK signal

123 45670

123 45670

123 45670

DO: data will change on the falling edge of CLK signal

DO: data will change on the falling edge of CLK signal

DO: data will change on the falling edge of CLK signal

123 45670

123 45670

123 45670

fault bit

fault bit

fault bit

transfered to output power switches

transfered to output power switches

transfered to output power switches

X

XX

XX

XX

XX

CSN low to high: actual data is

CSN low to high: actual data is

CSN low to high: actual data is

old data new data

old data new data

old data new data

232221201918

232221201918

232221201918

232221201918

time

time

time

01

01

01

time

time

time

0 1

0 1

0 1

time

time

time

01

01

232221201918

232221201918

01

time

time

time

time

time

time

16/39 Doc ID 10311 Rev 10

L9950 - L9950XP Electrical specifications

t

f

f

Figure 4. SPI - input timing

CSN

t

set C SN

t

CLKH

CLK

t

CLKL

Va lid

DI

t

set DI

Valid

t

hold DI

Figure 5. SPI - DO valid data delay time and valid time

t

in

CLK

t

r DO

t

se t CLK

r i n

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.5 VCC

0.2 VCC

DO

(low to high)

0.8 VCC

0.2 VCC

t

DO

0.8 VCC

DO

t

dDO

(high to low)

0.2 VCC

Doc ID 10311 Rev 10 17/39

Electrical specifications L9950 - L9950XP

t

t

CS

Figure 6. SPI - DO enable and disable time

f in r in

0.8 VCC

CSN

50%

0.2 VCC

pull-up load to VCC

DO

C = 100 pF

L

pull-down load to GND

DO

C = 100 pF

L

t t

en DO tri L

t t

Figure 7. SPI - driver turn-on/off timing, minimum csn hi time

N low to high: data from shift register

is transferred to output power switches

t

r in f in

t

CSN_HI,min

CSN

t

dOFF

output current
of a driver

ON state OFF state

t

OFF

t

dON

t

ON

50%

dis DO L tri

50%

t

80%

50%

20%

80%

50%

20%

output current
of a driver

OFF state

18/39 Doc ID 10311 Rev 10

80%

ON state

50%

20%

L9950 - L9950XP Electrical specifications

Figure 8. SPI - timing of status bit 0 (fault condition)

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO

CSN

time

CLK

time

DI

time

DI: data is not accepted

DO

0

-

DO: status information of data bit 0 (fault condition) will stay as long as CSN is low

time

Doc ID 10311 Rev 10 19/39

Application information L9950 - L9950XP

3 Application information

3.1 Dual power supply: VS and V

The power supply voltage VS supplies the half bridges and the highside drivers. An internal
charge-pump is used to drive the highside switches. The logic supply voltage V
5 V) is used for the logic part and the SPI of the device.

Due to the independent logic supply voltage the control and status information will not be
lost, if there are temporary spikes or glitches on the power supply voltage. In case of power­on (V

increases from under voltage to V

CC

internally generated power on reset (POR). If the voltage V
minimum threshold (V

POR ON

= 3.4 V), the outputs are switched to tristate (high impedance)

and the status registers are cleared.

3.2 Standby mode

The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data
Register 0. All latched data will be cleared and the inputs and outputs are switched to high
impedance. In the standby mode the current at V
CSN = high (DO in tristate). By switching the V
be achieved. If bit 23 is set, the device will be switched to active mode.

3.3 Inductive loads

Each half bridge is built by an internally connected highside and a lowside power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT6 without external free wheeling diodes. The highside
drivers OUT7 to OUT11 are intended to drive resistive loads. Hence only a limited energy
(E<1 mJ) can be dissipated by the internal ESD diodes in freewheeling condition. For
inductive loads (L>100
corresponding output is needed.

µH) an external free wheeling diode connected to GND and the

CC

POR OFF

CC

(stabilized

CC

= 4.2 V) the circuit is initialized by an

decreases under the

CC

(VCC) is less than 6 µA (50 µA) for

S

voltage a very low quiescent current can

3.4 Diagnostic functions

All diagnostic functions (over/open load, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32 µs (open load: 1 ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Open
load and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the overload and thermal shutdown
condition will disable the corresponding driver (overload) or all drivers (thermal shutdown),
respectively. Without setting the over-current recovery bits in the Input Data register, the

20/39 Doc ID 10311 Rev 10

microcontroller has to clear the over-current status bits to reactivate the corresponding
drivers.

L9950 - L9950XP Application information

3.5 Overvoltage and under voltage detection

If the power supply voltage VS rises above the overvoltage threshold V
21 V), the outputs OUT1 to OUT11 are switched to high impedance state to protect the load.
When the voltage V

drops below the under voltage threshold V

S

SUV OFF

voltage), the output stages are switched to the high impedance to avoid the operation of the
power devices without sufficient gate driving voltage (increased power dissipation). If the
supply voltage V

recovers to normal operating voltage the outputs stages return to the

S

programmed state (input register 0: bit 20=0).

If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the
drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of
a shorted output to GND and low battery voltage.

3.6 Temperature warning and thermal shutdown

If junction temperature rises above T
via the SPI. If junction temperature increases above the second threshold T
shutdown bit will be set and power DMOS transistors of all output stages are switched off to
protect the device. In order to reactivate the output stages the junction temperature must
decrease below T

j SD

- T

j SD HYS

and the thermal shutdown bit has to be cleared by the

microcontroller.

a temperature warning flag is set and is detectable

j TW

3.7 Open-load detection

SOV OFF

(typical

(UV switch OFF

, the thermal

j SD

The open load detection monitors the load current in each activated output stage. If the load
current is below the open load detection threshold for at least 1 ms (t
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open load status without
changing the mechanical/electrical state of the loads.

3.8 Over load detection

In case of an over-current condition a flag is set in the status register in the same way as
open load detection. If the over-current signal is valid for at least t
current flag is set and the corresponding driver is switched off to reduce the power
dissipation and to protect the integrated circuit. If the over-current recovery bit of the output
is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.

) the corresponding

dOL

= 32 µs, the over-

ISC

Doc ID 10311 Rev 10 21/39

Application information L9950 - L9950XP

3.9 Current monitor

The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits
18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5,
OUT6 and OUT11 will be multiplexed to the current monitor output. The current monitor
output allows a more precise analysis of the actual state of the load rather than the detection
of an open or overload condition. For example this can be used to detect the motor state
(starting, free running, stalled). Moreover, it is possible to regulate the power of the defroster
more precise by measuring the load current. The current monitor output is bidirectional (c.f.
PWM inputs).

3.10 PWM inputs

Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit is set, the output is controlled by the logically AND
combination of the PWM signal and the output control bit in Input Data Register. The outputs
OUT1-OUT8 and OUT11 are controlled by the PWM1 input and the outputs OUT9/10 are
controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be
used to dim two lamps independently by external PWM signals.

3.11 Cross current protection

The six half brides of the device are cross current protected by an internal delay time. If one
driver (LS or HS) is turned off the activation of the other driver of the same half bridge will be
automatically delayed by the cross current protection time. After the cross current protection
time is expired the slew rate limited switch off phase of the driver will be changed to a fast
turn-off phase and the opposite driver is turned on with slew rate limitation. Due to this
behavior it is always guaranteed that the previously activated driver is totally turned off
before the opposite driver will start to conduct.

3.12 Programmable soft start function to drive loads with higher inrush current

Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable soft start function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switch­on the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition.

The device itself cannot distinguish between a real overload and a non linear load like a light
bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.

22/39 Doc ID 10311 Rev 10

L9950 - L9950XP Application information

Figure 9. Example of programmable soft start function for inductive loads

Doc ID 10311 Rev 10 23/39

Functional description of the SPI L9950 - L9950XP

4 Functional description of the SPI

4.1 Serial Peripheral Interface (SPI)

This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO pin will reflect the
status bit 0 (fault condition) of the device which is a logical or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPI
communication cycle.

Note: In contrast to the SPI standard the least significant bit (LSB) will be transferred first

(see Figure 3).

4.2 Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started. The state when CSN is going low until the rising
edge of CSN will be called a communication frame. If the CSN input pin is driven above

7.5V, the L9950 will go into a test mode. In the test mode the DO will go from tri state to
active mode.

4.3 Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register. The writing to the selected Data Input Register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety function
is implemented to avoid an activation of the output stages by a wrong communication frame.

Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.

24/39 Doc ID 10311 Rev 10

L9950 - L9950XP Functional description of the SPI

4.4 Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.

4.5 Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.

4.6 Input data register

The device has two input registers. The first bit (bit 0) at the DI input is used to select one of
the two Input Registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected Input Data
Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents
of the selected status register will be transferred to DO during the current communication
frame. Bit 1-17 controls the behavior of the corresponding driver.

If bit 23 is zero, the device will go into the standby mode. The bits 18 and 19 are used to
control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status
registers. The bits in the status registers will be cleared after the current communication
frame (rising edge of CSN).

4.7 Status register

This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical NOR combination of bits 1-22 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPI
communication cycle. If one of the over-current bits is set, the corresponding driver will be
disabled. If the over-current recovery bit of the output is not set the microcontroller has to
clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers
will go into a high impedance state. Again the microcontroller has to clear the bit to enable
the drivers.

Doc ID 10311 Rev 10 25/39

Functional description of the SPI L9950 - L9950XP

4.8 Test mode

The test mode can be entered by rising the CSN input to a voltage higher than 7.0 V. In the
test mode the inputs CLK, DI, PWM1/2 and the internal 2 MHz CLK can be multiplexed to
data output DO for testing purpose. Furthermore the over-current thresholds are reduced by
a factor of 4 to allow EWS testing at lower current. For EWS testing a special test pad is
available to measure the internal bandgap voltage, the TW and TSD thresholds.

The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can
be switched on at the same time. In the test mode this combination is used to multiplex the
desired signals according to following table:

Table 18. Test mode

LS1 HS1 LS2 HS2 LS3 HS3 DO LS3 HS3 LS4 HS4 LS5 HS5 Test pad

! (both HI) ! (both HI) ! (both HI) No error ! (both HI) ! (both HI) ! (both HI) 5µA Iref

both HI ! (both HI) ! (both HI) DI both HI ! (both HI) ! (both HI) Tsens1

! (both HI) both HI ! (both HI) CLK ! (both HI) both HI ! (both HI) Tsens2

both HI both HI ! (both HI) INT_CLK both HI both HI ! (both HI) Tsens3

! (both HI) ! (both HI) both HI PWM1 ! (both HI) ! (both HI) both HI Tsens4

both HI ! (both HI) both HI PWM2 both HI ! (both HI) both HI Tsens5

! (both HI) both HI both HI Tsens6

both HI both HI both HI Vbandgap

26/39 Doc ID 10311 Rev 10

L9950 - L9950XP Functional description of the SPI

Table 19. SPI - input data and status registers 0

Input register 0 (write) Status register 0 (read)

Bit

Name Comment Name Comment

If Enable Bit is set the

23 Enable bit

22 Reset bit

OC recovery

duty cycle

21

0: 12%

25%

Overvoltage/Un

20

dervoltage

recovery disable

device will be switched in
active mode. If Enable Bit
is cleared device go into
standby mode and all bits
are cleared. After power­on reset device starts in
standby mode.

If Reset Bit is set both
status registers will be
cleared after rising edge
of CSN input.

This bit defines in
combination with the over­current recovery bit (Input
Register 1) the duty cycle

1:

in over-current condition
of an activated driver.

If this bit is set the
microcontroller has to
clear the status register
after
undervoltage/overvoltage
event to enable the
outputs.

Always 1

overvoltage

V

S

undervoltage

V

S

Thermal

shutdown

A broken VCC or SPI
connection of the L9950 can
be detected by the
microcontroller, because all 24
bits low or high is not a valid
frame.

In case of an overvoltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated. If
VS voltage recovers to normal
operating conditions outputs
are reactivated automatically
(if Bit 20 of status register 0 is
not set).

In case of an thermal
shutdown all outputs are
switched off.

The microcontroller has to
clear the TSD bit by setting the
Reset Bit to reactivate the
outputs.

19

Depending on
combination of bit 18 and
19 the current image
(1/10.000) of the selected
HS output will be multi­plexed to the CM output:

Bit 19Bit

18

Output

00OUT11

Temperature

warning

This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.

After switching the device from
standby mode to active mode
an internal timer is started to

OUT1/OUT

6

Not ready bit

Current monitor

18

select bits

10

01 OUT5

11 OUT4

HS driver of OUT1 is only
selected if HS driver
OUT1 is switched on and
HS driver OUT6 is not

allow charge pump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this
bit is controlled by internal
clock it can be used for
synchronizing testing events
(e.g. measuring filter times).

activated.

Doc ID 10311 Rev 10 27/39

Functional description of the SPI L9950 - L9950XP

Table 19. SPI - input data and status registers 0 (continued)

Input register 0 (write) Status register 0 (read)

Bit

Name Comment Name Comment

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

OUT11 – HS

on/off

OUT10 – HS

on/off

OUT9 – HS

on/off

OUT8 – HS

on/off

OUT7 – HS

on/off

OUT6 – HS

on/off

OUT6 – LS

on/off

OUT5 – HS

on/off

OUT5 – LS

on/off

OUT4 – HS

on/off

OUT4 – LS

on/off

OUT3 – HS

on/off

OUT3 – LS

on/off

OUT2 – HS

on/off

OUT2 – LS

on/off

If a bit is set the selected
output driver is switched
on. If the corresponding
PWM enable bit is set
(Input Register 1) the
driver is only activated if
PWM1 (PWM2) input
signal is high. The outputs
of OUT1-OUT6 are half
bridges. If the bits of HS­and LS driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal
current from VS to GND.
In test mode (CSN>7.5 V)
this bit combinations are
used to multiplex internal
signals to the DO output.

OUT11 – HS

over-current

OUT10 – HS

over-current

OUT9 – HS

over-current

OUT8 – HS

over-current

OUT7 – HS

over-current

OUT6 – HS

over-current

OUT6 – LS

over-current

OUT5 – HS

over-current

OUT5 – LS

over-current

OUT4 – HS

over-current

OUT4 – LS

over-current

OUT3 – HS

over-current

OUT3 – LS

over-current

OUT2 – HS

over-current

OUT2 – LS

over-current

In case of an over-current
event the corresponding
status bit is set and the output
driver is disabled. If the over­current Recovery Enable bit is
set (Input Register 1) the
output will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable
duty cycle (Bit 21).

If the over-current recovery bit
is not set the microcontroller
has to clear the over-current
bit (Reset Bit) to reactivate the
output driver.

OUT1 – HS

2

1

on/off

OUT1 – LS

on/off

0 0 No error bit

28/39 Doc ID 10311 Rev 10

OUT1 – HS

over-current

OUT1 – LS

over-current

A logical NOR combination of
all bits 1 to 22 in both status
registers.

L9950 - L9950XP Functional description of the SPI

Table 20. SPI - input data and status registers 1

Bit

Name Comment Name Comment

Input register 1 (write) Status register 1 (read)

23 Enable bit

OUT11 OC

22

Recovery

Enable

OUT10 OC

21

Recovery

Enable

OUT9 OC

20

Recovery

Enable

OUT8 OC

19

Recovery

Enable

OUT7 OC

18

Recovery

enable

If Enable bit is set the device
will be switched in active mode.
If Enable Bit is cleared device
go into standby mode and all
bits are cleared. After power­on reset device starts in
standby mode.

In case of an over-current
event the over-current status
bit (Status Register 0) is set
and the output is switched off.
If the over-current Recovery
Enable bit is set the output will
be automatically reactivated
after a delay time resulting in a
PWM modulated current with a
programmable duty cycle (Bit
21 of Input Data Register 0).
Depending on occurrence of
Overcurrent Event and internal
clock phase it is possible that
one recovery cycle is executed
even if this bit is set to zero.

Always 1

VS overvoltage

VS undervoltage

Thermal shutdown

Temperature

warning

Not ready bit

A broken VCC or SPI
connection of the L9950
can be detected by the
microcontroller, because
all 24 bits low or high is
not a valid frame.

In case of an overvoltage
or undervoltage event
the corresponding bit is
set and the outputs are
deactivated. If VS
voltage recovers to
normal operating
conditions outputs are
reactivated automatically.

In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to
clear the TSD bit by
setting the Reset Bit to
reactivate the outputs.

This bit is for information
purpose only. It can be
used for a thermal
management by the
microcontroller to avoid a
thermal shutdown.

After switching the
device from standby
mode to active mode an
internal timer is started
to allow charge pump to
settle before the outputs
can be activated. This bit
is cleared automatically
after start up time has
finished. Since this bit is
controlled by internal
clock it can be used for
synchronizing testing

events(e.g. measuring
filter times).

Doc ID 10311 Rev 10 29/39

Functional description of the SPI L9950 - L9950XP

Table 20. SPI - input data and status registers 1 (continued)

Bit

Name Comment Name Comment

OUT6 OC

17

Recovery

Enable

OUT5 OC

16

Recovery

Enable

OUT4 OC

15

Recovery

Enable

OUT3 OC

14

Recovery

Enable

OUT2 OC

13

Recovery

Enable

OUT1 OC

12

Recovery

Enable

OUT11 PWM1

11

10

9

8

7

6

5

4

3

2

1

Enable

OUT10 PWM2

Enable

OUT9 PWM2

Enable

OUT8 PWM1

Enable

OUT7 PWM1

Enable

OUT6 PWM1

Enable

OUT4 PWM1

Enable

OUT4 PWM1

Enable

OUT3 PWM1

Enable

OUT4 PWM1

Enable

OUT4 PWM1

Enable

0 1 No Error bit

Input register 1 (write) Status register 1 (read)

OUT11 – HS

open load

The open load detection
monitors the load current
in each activated output

OUT10 – HS

open load

stage. If the load current
is below the open load
detection threshold for at
least 1 ms (t
corresponding open load
bit is set. Due to
mechanical/electrical
inertia of typical loads a
short activation of the

After 50 ms the bit can be
cleared. If over-current
condition still exists, a wrong
load can be assumed.

OUT9 – HS

open load

OUT8 – HS

open load

outputs (e.g. 3 ms) can

OUT7 – HS

open load

be used to test the open
load status without
changing the

OUT6 – HS

open load

mechanical/electrical
state of the loads.

OUT6 – LS

open load

OUT5 – HS

If the PWM1/2 Enable Bit is set
and the output is enabled
(Input Register 0) the output is
switched on if PWM1/2 input is
high and switched off if
PWM1/2 input is low. OUT9
and OUT10 is controlled by
PWM2 input all other outputs
are controlled by PWM1 input.

open load

OUT5 – LS

open load

OUT4 – HS

open load

OUT4 – LS

open load

OUT3 – HS

open load

OUT3 – LS

open load

OUT2 –HS

open load

OUT2– LS

open load

The open load detection
monitors the load current
in each activated output
stage. If the load current
is below the open load
detection threshold for at
least 1 ms (t
corresponding open load
bit is set. Due to
mechanical/electrical
inertia of typical loads a
short activation of the
outputs (e.g. 3 ms) can
be used to test the open
load status without
changing the
mechanical/electrical
state of the loads.

OUT1 – HS

open load

OUT1 – LS

open load

A logical NOR
combination of all bits 1
to 22 in both status
registers.

dOL

dOL

) the

) the

30/39 Doc ID 10311 Rev 10

L9950 - L9950XP Packages thermal data

5 Packages thermal data

Figure 10. Packages thermal data

Doc ID 10311 Rev 10 31/39

Package and packing information L9950 - L9950XP

6 Package and packing information

6.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

®

packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

is an ST trademark.

6.2 PowerSO-36 package information

Figure 11. PowerSO-36 package dimensions

.

32/39 Doc ID 10311 Rev 10

L9950 - L9950XP Package and packing information

Table 21. PowerSO-36 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A- -3.60

a1 0.10 - 0.30

a2 - - 3.30

a3 0 - 0.10

b 0.22 - 0.38

c 0.23 - 0.32

D * 15.80 - 16.00

D1 9.40 - 9.80

E 13.90 - 14.5

E1 * 10.90 - 11.10

E2 - - 2.90

E3 5.80 - 6.20

e - 0.65 -

e3 - 11.05 -

G0 -0.10

H 15.50 - 15.90

h--1.10

L0.8-1.10

M---

N - - 10 deg

R---

s--8 deg

Doc ID 10311 Rev 10 33/39

Package and packing information L9950 - L9950XP

6.3 PowerSSO-36 package information

Figure 12. PowerSSO-36 package dimensions

Table 22. PowerSSO-36 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.15 - 2.45

A2 2.15 - 2.35

a1 0 - 0.10

b 0.18 - 0.36

c 0.23 - 0.32

(1)

D

10.10 - 10.50

E7.4 - 7.6

e-0.5-

e3 - 8.5 -

F-2.3-

G- -0.1

G1 - - 0.06

H 10.1 - 10.5

h--0.4

k0°-8°

34/39 Doc ID 10311 Rev 10

L9950 - L9950XP Package and packing information

Table 22. PowerSSO-36 mechanical data (continued)

Symbol

Min. Typ. Max.

L 0.55 - 0.85

M-4.3-

N- -10°

O-1.2-

Q-0.8-

S-2.9-

T-3.65-

U-1-

X4.3 - 5.2

Y6.9 - 7.5

1. “D” and “E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm

per side (0.006”).

Millimeters

6.4 PowerSO-36 packing information

Figure 13. PowerSO-36 tube shipment (no suffix)

Doc ID 10311 Rev 10 35/39

Package and packing information L9950 - L9950XP

Figure 14. PowerSO-36 tape and reel shipment (suffix “TR”)

TAPE DIMENSIONS

A0 15.20 ± 0.1
B0 16.60 ± 0.1
K0 3.90 ± 0.1
K1 3.50 ± 0.1
F 11.50 ± 0.1
P1 24.00 ± 0.1
W 24.00 ± 0.3

All dimensions are in mm.

REEL DIMENSIONS

Base qty 600
Bulk qty 600
A (max) 330
B (min) 1.5
C (±0.2) 13
D (min) 20.2
G (+2 / -0) 24.4
N (min) 60
T (max) 30.4

36/39 Doc ID 10311 Rev 10

L9950 - L9950XP Package and packing information

6.5 PowerSSO-36 packing information

Figure 15. PowerSSO-36 tube shipment (no suffix)

Base qty 49

C

B

A

Figure 16. PowerSSO-36 tape and reel shipment (suffix “TR”)

Bulk qty 1225
Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6

All dimensions are in mm.

REEL DIMENSIONS

Base qty 1000
Bulk qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24
Tape hole spacing P0 (±0.1) 4
Component spacing P 12
Hole diameter D (±0.05) 1.55
Hole diameter D1 (min) 1.5
Hole position F (±0.1) 11.5
Compartment depth K (max) 2.85
Hole spacing P1 (±0.1) 2

End

All dimensions are in mm.

Start

Top

cover

tape

500mm min

Empty components pockets
sealed with cover tape.

User direction of feed

No componentsNo components Components

500mm min

Doc ID 10311 Rev 10 37/39

Revision history L9950 - L9950XP

7 Revision history

Table 23. Document revision history

Date Revision Description of changes

Apr-2004 1 First Issue

Jun-2004 2

Changed maturity from product preview to final;
Changed values in the Table 4: ESD protection

Jul-2004 3 Minor changes

Jun-2005 4 PowerSSO-36 package insertion

Jul-2005 5 Figure 1 modification

Features modification;

Sep-2005 6

Ta ble 7 modification (ICC; IS + ICC);
Figure 10 modification;

modification.

I

QLL

Document restructured and reformatted.

14-Nov-2007 7

Added PowerSO-36 packing information and PowerSSO-36 packing

information.

05-Nov-2008 8 Updated Table 22: PowerSSO-36 mechanical data.

30-Mar-2009 9

Changed Section : Application on cover page
Changed Section 6.1: ECOPACK

®

Table 22: PowerSSO-36 mechanical data:

09-Jun-2009 10

– Changed A (max) value from 2.50 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed L (max) value from 0.90 to 0.85

38/39 Doc ID 10311 Rev 10

L9950 - L9950XP

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Doc ID 10311 Rev 10 39/39