ST L9942 User Manual

Integrated stepper motor driver for bipolar stepper motors

with microstepping and programmable current profile

Features

■ Two full bridges for max. 1.3 A load

■ Programmable current waveform with look-up

table: 9 entries with 5 bit resolution

■ Current regulation by integrated PWM

controller and internal current sensing

■ Programmable stepping mode: full, half, mini

and microstepping

■ Programmable slew rate for EMC and power

dissipation optimization

■ Programmable Fast-, Slow-, Mixed- and Auto-

Decay Mode

■ Full-scale current programmable with 3 bit

resolution

■ Programmable stall detection

■ Step clock input for reduced µController

requirements

■ Very low current consumption in standby mode

■ All outputs short circuit protected with

openload, overload current, temperature warning and thermal shutdown

■ The PWM signal of the internal PWM controller

is available as digital output.

■

All parameters are guaranteed for 3 V < Vcc <

5.3 V

Applications

Stepper motor driver for bipolar stepper motors in automotive applications like light levelling, Bending light and Throttle control.

Table 1. Device summary

= 500 mΩ)

DSON

< 3 µA, typ. Tj ≤ 85 °C

and for 7 V < Vs < 20 V

L9942

PowerSSO24

Description

The L9942 is an integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile look-up-table to allow a flexible adaptation of the stepper motor characteristics and intended operating conditions. It is possible to use different current profiles depending on target criteria: audible noise, vibrations, rotation speed or torque. The decay mode used in PWM-current control circuit can be programmed to slow-, fast-, mixed-and autodecay. In autodecay mode device will use slow decay mode if the current for the next step will increase and the fast decay or mixed decay mode if the current will decrease. The programmable stall detection is useful in case of head lamp leveling and bending light application, by preventing to run the motor too long time in stall for position alignment. If a stall is detected, the alignment process is closed and the noise is minimized.

Order code Junction temp. range, °CPackage Packing

L9942XP1 -40 to 150 PowerSSO24 Tube

L9942XP1TR -40 to 150 PowerSSO24 Tape and reel

May 2009 Doc ID 11778 Rev 6 1/40

www.st.com

Contents L9942

Contents

1 Block diagram and pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Dual power supply: VS and V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.8 PWM current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.9 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.10 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.11 Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.12 Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.13 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.2 Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.3 Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.4 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4.5 Outputs: Qxn (x = A; B n = 1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4.6 PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Functional description of the logic with SPI . . . . . . . . . . . . . . . . . . . . . 21

4.1 Motor stepping clock input (STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 PWM output (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/40 Doc ID 11778 Rev 6

L9942 Contents

4.4 Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 Serial data in (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6 Serial data out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.8 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4 Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5 Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.6 Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.7 Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.8 Auxiliary logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.8.1 Fault condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.8.2 SPI communication monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.8.3 PWM monitoring for stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 Logic with SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3 Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4 Output: DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.5 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.6 STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2 Step clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.3 Load current control and detection of overcurrent (shortages at outputs) 33

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 11778 Rev 6 3/40

List of tables L9942

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. Outputs: Qxn (x = A; B n =1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 13. PWM control (see Figure 4 and Figure 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 14. Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15. Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18. Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19. Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 20. Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 21. Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22. DI timing (see Figure 11 and Figure 13)

Table 23. Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 24. Output: DO timing (see Figure 12 and Figure 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 25. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 26. STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4/40 Doc ID 11778 Rev 6

L9942 List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4. Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. Thermal data of the package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. VS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Logic to set load current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Switching on minimum time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. SPI and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13. DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 14. Timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15. Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 16. Reference generation for PWM control (switch on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17. Reference generation for PWM control (decay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18. PowerSSO24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 11778 Rev 6 5/40

Block diagram and pin information L9942

1 Block diagram and pin information

Figure 1. Block diagram

VBAT

VCC

SPI + Register + Logic

GND

Charge

Pump

Diagnostic

⇓

Phase Counter+Current Profile

Diagnostic

U/I-

Converter

RREF

PWM Current DAC

Gate-Driver

PWM-Controller

Gate-Driver

PWM-Controller

Oscillator

STEP

PWM

μC

CLK

CSN

Biasing

ReversePolarityProtection

QA1

QA2

QB1

QB2QB2

QB2

GNDP

Note: value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings i n case of an unexpected freewheeling condition (e.g. TSD, POR)

Stepper

Motor

Figure 2. Pin connection (top view)

PGND 1

QA1

CLK

CSN

PWM

STEP 9

VS 10

QB1 11

PGND 12

All pins with the same name must be externally connected!

All pins PGND are internally connected to the heat slug.

Power SSO24

Exposed

Pad

GND

PGND24

QA223

EN21

RREF20

VCC19

TEST18

GND

CP16

VS15

QB214

PGND13

6/40 Doc ID 11778 Rev 6

L9942 Block diagram and pin information

Table 2. Pin description

Pin Symbol Function

1, 12, 13,

3, 10, 15,

2, 23

11, 14

PGND

QA1,QA

QB1,QB

4 CLK

5 DI

6 CSN

7 DO

8 PWM

9 STEP

Power ground: All pins PGND are internally connected to the heat slug. Important: All pins of PGND must be externally connected!

Power supply voltage (external reverse protection required): For EMI reason a ceramic capacitor as close as possible to PGND is recommended. Important: All pins of VS must be externally connected!

Fullbridge-outputs An: The output is built by a high-side and a low-side switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal reverse diode (bulkdrain-diode: highside driver from output to VS, low-side driver from PGND to output). This output is overcurrent protected.

Fullbridge-outputs Bn: The output is built by a highside and a low-side switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal reverse diode (bulkdrain-diode: highside driver from output to VS, low-side driver from PGND to output). This output is overcurrent protected.

SPI clock input: The input requires CMOS logic levels. The CLK input has a pull-down current. It controls the internal shift register of the SPI.

Serial data input: The input requires CMOS logic levels. The DI input has a pull-down current. It receives serial data from the microcontroller. The data is a 16bit control word and the most significant bit (MSB, bit 0) is transferred first.

Chip Select Not input The input requires CMOS logic levels. The CSN input has a pull-up current. The serial data transfer between device and micro controller is enabled by pulling the input CSN to low level.

SPI data output: The diagnosis data is available via the SPI and it is a tristate-output. The output is CMOS compatible will remain highly resistive, if the chip is not selected by the input CSN (CSN = high)

PWM output This CMOS compatible output reflects the current duty cycle of the internal PWM controller of bridge A. It is an high resistance output until VCC has reached minimum voltage ore can switched off via the SPI command.

Step clock input: The input requires CMOS logic levels. The STEP input has a pull-down current. It is clock of up and down counter of control register 0. Rising edge starts new PWM cycle to drive motor in next position.

16 CP

17 GND

18 TEST

19 VCC

Charge Pump Output: A ceramic capacitor (e.g.100 nF) to VS can be connected to this pin to buffer the charge-pump voltage.

Ground: Reference potential besides power ground e.g. for reference resistor RREF. From this pin exist a resistive path via substrate to PGND.

Test in put The TEST input has a pull-down current. Pin used for production test only. In the application it must be connected to GND.

Logic supply voltage: For this input a ceramic capacitor as close as possible to GND is recommended.

Doc ID 11778 Rev 6 7/40

Block diagram and pin information L9942

Table 2. Pin description (continued)

Pin Symbol Function

Reference Resistor The reference resistor is used to generate a

temperature stable reference current used for current control and internal

20 RREF

21 EN

oscillator. At this output a voltage of about 1.28V is present. The resistor should be chosen that a current of about 200uA will flow through the resistor.

Enable input: The input requires CMOS logic levels. The EN input has a pull-down resistor. In standby-mode outputs will be switched off and all registers will be cleared. If EN is set to a logic high level then the device will enter the active mode.

8/40 Doc ID 11778 Rev 6

L9942 Device description

2 Device description

2.1 Dual power supply: VS and VCC

The power supply voltage VS supplies the half bridges. An internal charge-pump is used to drive the highside switches. The logic supply voltage V part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (V typical) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage V are switched to tristate (high impedance) and the internal registers are cleared.

decreases under the minimum threshold (V

2.2 Standby mode

The EN input has a pull-down resistor. The device is in standby mode if EN input isn't set to a logic high level. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 3 µA (1 µA) for CSN = high (DO in tristate). If EN is set to a logic high level then the device will enter the active mode. In the active mode the charge pump and the supervisor functions are activated.

increases from undervoltage to V

(stabilized) is used for the logic

= 2.60 V,

POR ON

POR OFF

= 2.3 V, typical), the outputs

2.3 Diagnostic functions

All diagnostic functions (overload/-current, open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered (t the condition has to be valid for a minimum time before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the bridge drivers. On contrary, the overload/-current and thermal shutdown condition will disable the corresponding driver (overload/-current) or all drivers (thermal shutdown), respectively. The microcontroller has to clear the status bit to reactivate the bridge driver.

2.4 Overvoltage and undervoltage detection

If the power supply voltage Vs rises above the overvoltage threshold V 21 V), an overvoltage condition is detected. Programmable by SPI (OVW) the outputs are switched to high impedance state (default after reset) or the overvoltage bit is set without switching the outputs to high impedance. When the voltage Vs drops below the undervoltage threshold V operation of the power devices without sufficient gate driving voltage (increased power dissipation). Error condition is latched and the microcontroller needs to clear the status bits to reactivate the drivers.

SUV OFF

, the outputs are switched to high impedance state to avoid the

= 32 µs, typical) and

SOV OFF

(typical

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Device description L9942

2.5 Temperature warning and thermal shutdown

If junction temperature rises above T detectable via the SPI. If junction temperature increases above the second threshold T the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below Tj SD -Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller.

a temperature warning flag is set which is

j TW

2.6 Inductive loads

Each half bridge is built by an internally connected highside and a low-side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven without external free-wheeling diodes. In order to reduce the power dissipation during free-wheeling condition the PWM controller will switch-on the output transistor parallel to the freewheeling diode (synchronous rectification).

2.7 Cross-current protection

The four half-brides of the device are cross-current protected by an internal delay time depending on the programmed slew rate. If one driver (LS or HS) is turned-off then activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time.

j SD

2.8 PWM current regulation

An internal current monitor output of each high-side and low-side transistor sources a current image which has a fixed ratio of the instantaneous load current. This current images are compared with the current limit in PWM control. Range of limit can reach from programmed full scale value (register1 DAC Scale) down belonging LSB value of 5 bit DAC (register1 DAC Phase x). The data of the two 5 bit DACs comes form set up in 9 current profiles (register2 to 6). If signal changes to logic high at pin STEP then 2 current profiles are moved in register1 for DAC Phase A and B. Number of profile depends on phase counter reading and direction bit in register0 (Figure 7). The bridges are switched on until the load current sensed at HS switch exceeds the limit. Load current comparator signal is used to detect open load or overcurrent condition also.

2.9 Decay modes

During off-time the device will use one of several decay modes programmable by SPI (Figure 4 top). In slow decay mode HS switches are activated after cross current protection time for synchronous rectification to reduce the power dissipation (Figure 4 detail A). In fast decay opposite half bridge will switched on after cross current protection time, that is same like change in the direction. For mixed decay the duration of fast decay period before slow decay can be set to a fixed time (Figure 4 detail B continuous line) or is triggered by underrun of the load current limit (Figure 4 detail B dashed line), that can be detected at LS switch. The special mode where the actual phase counter value is taken into account to select the decay mode is called auto decay (e.g. in Figure 3 Micro Stepping DIR=1). If the absolute value of the current limit is higher as during step before then PWM control uses

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L9942 Device description

slow decay mode always. Otherwise one of the fast decay modes is automatic selected for a quick decrease of the load current and so it obtains new lower target value.

2.10 Overcurrent detection

The overcurrent detection circuit monitors the load current in each activated output stage. In HS stage it is in function after detection of current limit during PWM cycle and in LS stage it works permanently. If the load current exceeds the overcurrent detection threshold for at least t

= 4 µs, the overcurrent flag is set and the corresponding driver is switched off to

ISC

reduce the power dissipation and to protect the integrated circuit. Error condition is latched and the microcontroller needs to clear the status bits to reactivate the drivers.

2.11 Open load detection

The open load detection monitors the activity time of the PWM controller and is available for each phase. If the limit of load current is below around 100mA then open load condition is detectable. Open load bit for a bridge is set in the register6 if this low current limit can't reached after at least 15 consecutive PWM cycles.

Table 3. Truth table

DC2 DC1 DC0 I4 I3 I2 I1 I0 max. IOL

0000xxxx46mA

0010xxxx68mA

01000xxx52mA

01100xxx81mA

100000xx53mA

101000xx78mA

1100000137mA

1110000144mA

Truth table shows possible profiles for active open load detection. Maximum threshold IOL is shown in left column if x bits are 1 (see also Figure 7). Lowest possible limit is e.g. 3.1 mA for DC2=DC1=DC0=0 and it is set only I0=1.

2.12 Stepping modes

One full revolution can consist of four full steps, eight half steps, sixteen mini steps or 32 microsteps.

Mode is set up in register 0 and it defines increment size of phase counter. Phase counter value defines address of corresponding current profile. Stepping modes with typical profile values can see in Figure 3 (e.g. also so called 'Two Phase On' shown in dashed line).

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Device description L9942

Figure 3. Stepping modes

Full-Stepping Mode: DIR=0

081624

Current Driver A

080 8

Current Driver B

0808

STEP Signal

Half-Stepping Mode: DIR=0

0 4 812162024 28

Current Driver A

04840 484

Current Driver B

04840484

STEP Signal

Phase Counter

Address of Current

Profile Entry

Address of Current

Profile Entry

Phase Counter

Address of Current

Profile Entry

Address of Current

Profile Entry

Full-Stepping Mode: DIR=1

24 16 8 0

Current Driver A

0808

Current Driver B

0808

STEP Signal

Half-Stepping Mode: DIR=1

0 2824 2016128 4

Driver Current A

048 404 84

Driver Current B

04840484

STEP Signal

Mini-Stepping Mode: DIR=0

0 2 4 6 81012141618202224262830

Current Driver A

0246864202468642

Current Driver B

0246864202468642

STEP Signal

Micro Stepping Mode: DIR=0 (e.g auto decay)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 2223 24 25 26 27 28 29 30 31

Current Driver A

012345 678 765 432101 234 5678 76543 21

Slow Decay Mode

Mixed Decay Mode

0123 456 787654 321 012 34567876543 21

Slow Decay Mode

Current Driver B

Slow Decay Mode

Mixed Decay Mode

Slow Decay Mode

Phase Counter

Adress of Current

Profile Entry

Adress of Current

Profile Entry

Phase Counte r

Adress of Current

Profile Entry

Adress of Current

Profile Entry

Mini-Stepping Mode: DIR=1

0 30 28 262422 201816141210 8 6 4 2

Current Driver A

0246864202468642

Current Driver B

0246864202468642

STEP Signal

Micro Stepping Mode: DIR=1 (e.g. auto decay)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1

Current Driver A

Slow Decay Mode

012 345 678 765432 101 2345 67876 543 21

Mixed Decay Mode

0123 456 787 654321 012 345678 76 543 21

Slow Decay Mode

Current Driver B

Mixed Decay Mode

Slow Decay Mode

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