L9904
Fi
MOTOR BRIDGE CONTROLLER
1 FEATURES
■ OPERATING SUPPLY VOLTAGE 8V TO 28V,
OVERVOLTAGE MAX. 40V
■ OPERATING SUPPLY VOLTAGE 6V WITH
IMPLEMENTED STEPUP CONVERTER
■ QUIESCENT CURRENT IN STANDBY MODE
LESS THAN 50µA
■ ISO 9141 COMPATIBLE INTERFACE
■ CHARGE PUMP FOR DRIVING A POWER
MOS AS REVERSE BATTERY PROTECTION
■ PWM OPERATION FREQUENCY UP TO
30KHZ
■ PROGRAMMABLE CROSS CONDUCTION
PROTECTION TIME
■ OVERVOLTAGE, UNDERVOLTAGE, SHORT
CIRCUIT AND THERMAL PROTECTION
■ REAL TIME DIAGNOSTIC
Figure 2. Block Diagram
10
VS
VCC
VCC
-
+
f
Overvolt age
Undervoltage
Thermal shutdown
Timer
=
V
STH
ST
PWM
1
ST
R
DG
2
DG
4
EN
R
EN
5
DIR
R
DIR
R
PWM
3
6
PR
gure 1. Package
SO20
Table 1. Order Codes
Part Number Package
L9904 SO20
L9904TR Tape & Reel
2 DESCRIPTION
Control circuit for power MOS bridge driver in automotive applications with ISO 9141bus interface.
R
Reference
BIAS
VCC
Charge
pump
=
V
S1TH
Control Logic
=
V
S2TH
CP
11
CP
13
CB1
12
GH1
14
S1
R
S1
19
GL1
R
GL1
18
GL2
R
GL2
17
S2
R
S2
15
GH2
16
CB2
October 2005
7
RX
R
RX
VCC
R
TX
8
TX
ISO-Interface
=
0.5 • V
VS
I
KH
9
K
20
GND
REV. 4
1/17
L9904
Table 2. Pin Function
N° Pin Description
1 ST Open Drain Switch for Stepup converter
2 DG Open drain diagnostic output
3 PWM PWM input for H-bridge control
4 EN Enable input
5 DIR Direction select input for H-bridge control
6 PR Programmable cross conduction protection time
7 RX ISO 9141 interface, receiver output
8 TX ISO 9141 interface, transmitter input
9 K ISO 9141 Interface, bidirectional communication K-line
10 VS Supply voltage
11 CP Charge pump for driving a power MOS as reverse battery protection
12 GH1 Gate driver for power MOS highside switch in halfbridge 1
13 CB1 External bootstrap capacitor
14 S1 Source/drain of halfbridge 1
15 GH2 Gate driver for power MOS highside switch in halfbridge 2
16 CB2 External bootstrap capacitor
17 S2 Source/drain of halfbridge 2
18 GL2 Gate driver for power MOS lowside switch in halfbridge 2
19 GL1 Gate driver for power MOS lowside switch in halfbridge 1
20 GND Ground
Figure 3. Pin Connection (Top view)
ST
DG
PWM
EN
DIR
PR
RX
TX
K GH1
VS CP
2
3
4
5
6
7
8
9
10
SO20
20
19
18
17
16
15
14
13
12
11
GND1
GL1
GL2
S2
CB2
GH2
S1
CB1
2/17
L9904
Table 3. Absolute Maximum Ratings
Symbol Parameter Value Unit
V
, V
CB1
, I
I
CB1
V
CP
I
CP
,V
V
DIR
,V
PWM ,VTX
,I
I
DIR
,I
PWM ,ITX
,V
V
DG
,IRX Logic output current -1 mA
I
DG
, V
V
GH1
, I
I
GH1
, V
V
GL1
, I
I
GL1
V
V
PR
I
PR
, V
V
S1
, I
I
S1
V
ST
I
ST
V
VSDC
V
VSP
I
VS
For externally applied voltages or currents exceeding these limits damage of the device may occur!
All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body
model with R=1.5k
0.2mJ.
Bootstrap voltage -0.3 to 40 V
CB2
Bootstrap current -100 mA
CB2
Charge pump voltage -0.3 to 40 V
Charge pump current -1 mA
Logic input voltage -0.3 to 7 V
EN
Logic input current ±1 mA
EN
Logic output voltage -0.3 to 7 V
RX
Gate driver voltage -0.3 to VSX + 10 V
GH2
Gate driver current -1 mA
GH2
Gate driver voltage -0.3 to 10 V
GL2
Gate driver current -10 mA
GL2
K-line voltage -20 to V
K
S
Programming input voltage -0.3 to 7 V
Programming input current -1 mA
Source/drain voltage -2 to VVS + 2 V
S2
Source/drain current -10 mA
S2
Output voltage -0.3 to 40 V
Step up output current -1 mA
DC supply voltage -0.3 to 28 V
Pulse supply voltage (T < 500ms) 40 V
DC supply current -100 mA
Ω
, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of
V
Table 4. Thermal Data
Symbol Parameter Value Unit
T
T
JSD
T
JSDH
R
th j-amb
1. see application note 110 for SO packages.
Operating junction temperature -40 to 150 °C
J
Junction temperature thermal shutdown threshold min 150 °C
Junction thermal shutdown hysteresis typ 15 °C
Thermal resistance junction to ambient
1)
85 °C/W
.
3/17
L9904
Table 5.
Electrical Characteristcs
(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
Supply (VS)
V
VS OVH
V
VS OVh
V
VS UVH
V
VS UVh
I
VSL
I
VSH
I
VSD
Enable input (EN)
V
V
V
R
H-bridge control inputs (DIR, PWM)
V
DIRL
V
PWML
V
DIRH
V
PWMH
V
DIRh
V
PWMh
R
R
PWM
DIAGNOSTIC output (DG)
V
R
Programmable cross conduction protection
N
I
ISO interface, transmission input (TX)
V
Overvoltage disable HIGH
28 33 36 V
threshold
Overvoltage threshold hysteresis
Undervoltage disable HIGH
2)
67V
1.6 V
threshold
Undervoltage threshold
hysteresis
2)
0.66 V
Supply current VEN = 0 ; VVS = 13.5V; TJ< 85°C 50 µA
Supply current, pwm-mode VVS= 13.5V; VEN= HIGH;
= LOW; S1 = S2 = GND
V
DIR
f
PWM
C
GLX
R
PR
= 20kHz; C
= 4.7nF; C
= 10kΩ; C
CBX
GHX
= 150pF
PR
= 0.1µF;
= 4.7nF;
Supply current, dc-mode VVS= 13.5V; VEN= HIGH;
V
= LOW; S1 = S2 = GND
DIR
= LOW; C
V
PWM
= 10kΩ; C
R
PR
Low level 1.5 V
ENL
High level 3.5 V
ENH
ENh
Hysteresis threshold
Input pull down resistance VEN = 5V 16 50 100 kΩ
EN
2)
GHX
= 150pF
PR
= 4.7nF
8.1 13 mA
5.8 10 mA
1V
Input low level 1.5 V
Input high level 3.5 V
Input threshold hysteresis
Internal pull up resistance
DIR
to internal VCC
Output drop IDG = 1mA 0.6 V
DG
Internal pull up resistance
DG
to internal VCC
Threshold voltage ratio V
PR
V
PRL
Current capability
PR
Input low level 1.5 V
TXL
3)
3)
2)
PRH
1V
V
DIR
= 0; V
= 0 16 50 100 kΩ
PWM
VDG = 0V 10 20 40 kΩ
4)
R
V
PR
PR
= 10kΩ
= 2V
/
1.822.2
-0.5 mA
4/17
L9904
Table 5.
(8V < V
Electrical Characteristcs
< 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
VS
(continued)
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
V
R
ISO interface, receiver output (RX)
V
R
R
RXON
t
RXH
t
RXL
ISO interface, K-line (K)
V
V
V
I
R
I
KSC
t
t
t
t
t
Charge pump
V
Input high level 3.5 V
TXH
Input hysteresis voltage 2) 1 V
TXh
Internal pull up resistance to
TX
VTX = 0 102040kΩ
internal VCC 3)
Output voltage high stage
RXL
Internal pull up resistance
RX
to internal VCC
3)
ON resistance to ground TX = LOW;
TX = HIGH; I
TX = HIGH;
= 0V
V
RX
= 1mA
I
RX
RX
= 0; V
= V
K
VS
4.5 5.5 V
51020kΩ
40 90 Ω
Output high delay time Fig. 1 0.5 µs
Output low delay time 0.5 µs
Input low level -20V 0.45 ·
KL
Input high level
KH
Input hysteresis voltage 2) 0.025·
Kh
Input current VTX = HIGH -5 25 µA
KH
ON resistance to ground VTX = LOW; IK=10mA 10 30 Ω
KON
0.55 ·
V
VS
V
VS
Short circuit current VTX = LOW 40 130 mA
Transmission frequency 60 100 kHz
f
K
2. not tested in production: guaranteed by design and verified in characterization
3. Internal V
4. see page 18 for calculation of programmable cross conduction protection time
Rise time VVS = 13.5V; Fig. 1
Kr
is 4.5V ... 5.5V
VCC
26µs
External loads at K-line:
= 510Ω pull up
R
K
to V
VS
C
= 2.2nF to GND
K
Fall time 26µs
Kf
Switch high delay time 4 17 µs
KH
Switch low delay time 4 17 µs
KL
Short circuit detection time VVS = 13.5V;
SH
10 40 µs
TX = LOW
> 0.55 · V
V
Charge pump voltage VVS = 8V
CP
K
VS
V
+
VS
7V
V
VS
= 13.5V
+
V
VS
10V
V
= 20V
VS
+
V
VS
10V
V
VS
V
VS
0.8V
VVS+
14V
V
VS
14V
V
VS
+14V
+
5/17
L9904
Table 5.
(8V < V
Electrical Characteristcs
< 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
VS
(continued)
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
I
t
CP
CP
Charging current
= VVS + 8V
V
CP
Charging time
2)
VCP= VVS + 8V
f
Charge pump frequency VVS = 13.5V 250 500 750 kHz
CP
Drivers for external highside power MOS
V
V
R
R
R
R
V
V
R
R
R
R
GH1L
GH2L
GH1H
GH2H
GH1H
GH2H
Bootstrap voltage VVS = 8V; I
CB1
CB2
ON-resistance of SINK stage
ON-resistance of SOURCE stage I
Gate ON voltage (SOURCE) VVS= VSX = 8V; I
Gate discharge resistance EN = LOW 10 100 kΩ
GH1
GH2
Sink resistance 10 100 kΩ
S1
S2
Drivers for external lowside power MOS
R
GL1L
R
GL2L
R
GL1H,
R
GL2H
V
GL1H,
V
GL2H
R
R
2. not tested in production: guaranteed by design and verified in characterization
ON-resistance of SINK stage I
ON-resistance of SOURCE stage I
Gate ON voltage (SOURCE) VVS = 8V; I
Gate discharge resistance EN = LOW 10 100 kΩ
GL1
GL2
Timing of the drivers
t
GH1LH
t
GH2LH
Propagation delay time Fig. 2
V
= 13.5V -50 -75 µA
VS
V
= 13.5V
VS
C
= 10nF
CP
VVS =13.5V; I
V
= 20V; I
VS
V
CBX
I
GHX
V
CBX
I
GHX
GHX
I
GHX
C
CBX
= VSX = 13.5V; I
V
VS
C
CBX
= VSX = 20V; I
V
VS
C
CBX
GLX
I
GLX
GLX
I
GLX
V
= 13.5V; I
VS
= 20V; I
V
VS
CBX
CBX
CBX
= 8V; VSX = 0
= 50mA; T
= 8V; VSX = 0
= 50mA; T
= -50mA; TJ = 25°C
= -50mA; TJ = 125°C
= 0.1µF
= 0.1µF
= 0.1µF
= 50mA; TJ = 25°C
= 50mA; TJ = 125°C
= -50mA; TJ = 25°C
= -50mA; TJ = 125°C
= 0
GLX
GLX
GLX
= 0; VSX = 0
= 0; VSX = 0
= 0; VSX = 0
= 25°C
J
= 125°C
J
= 0;
GHX
= 0;
GHX
= 0;
GHX
= 0
= 0
7.5
10
10
V
VS
+6.5V
V
VS
10V
V
VS
+10V
7V
10V
10V
1.2 4 ms
+
14
14
14
10 Ω
20 Ω
10
20
V
VS
+14V
V
VS
+14V
V
VS
+14V
10
20
10
20
V
VS
V
VS
14V
500 ns
= 13.5V
V
VS
VS1 = VS2 =0
C
= 0.1µF
CBX
V
V
V
Ω
Ω
Ω
Ω
Ω
Ω
6/17
RPR= 10kW
L9904
Table 5.
(8V < V
Electrical Characteristcs
< 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
VS
(continued)
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
t
GH1LH
t
GH2LH
t
GH1HL
t
GH2HL
Propagation delay time including
cross conduction protection time
t
CCP
Propagation delay time 500 ns
Fig. 2
V
VS
V
S1
C
CBX
C
PR
= 13.5V
= VS2 =0
= 0.1µF
= 150pF;
RPR= 10kΩ;
5)
t
GL1LH
t
GL2LH
Propagation delay time Fig. 2
V
VS
= 13.5V
VS1 = VS2 =0
C
= 0.1µF
CBX
= 10kΩ
R
PR
t
GL1LH
t
GL2LH
t
GL1HL
t
GL2HL
Propagation delay time including
cross conduction protection time
t
CCP
Propagation delay time 500 ns
Fig. 2
V
VS
V
S1
C
CBX
C
PR
= 13.5V
= VS2 =0
= 0.1µF
= 150pF;
RPR= 10kΩ;
5)
t
GH1r
t
GH2r
t
GH1f
t
GH2f
t
GL1r
t
GL2r
t
GL1f
t
GL2f
Rise time Fig. 2
= 13.5V
V
VS
V
= VS2 =0
Fall time 1 µs
Rise time 1 µs
Fall time 1 µs
C
C
C
R
S1
CBX
GHX
GLX
PR
= 0.1µF
= 4.7nF
= 4.7nF
= 10kΩ;
Short Circuit Detection
V
S1TH
V
S2TH
t
SCd
Step up converter (ST) (5.2V ≤ V
V
V
R
DSON
f
Threshold voltage 4 V
Detection time 5 10 15 µs
< 10V)
VS
ST disable HIGH threshold 10 V
STH
ST disable threshold hysteresis
STh
voltage
Open drain ON resistance
Clock frequency 50 100 149 kHz
ST
2. not tested in production: guaranteed by design and verified in characterization
5. tested with differed values in production but guaranteed by design and verified in characterization
2)
= 5.2V;
V
VS
= 50mA
I
ST
0.711.3µs
500 ns
0.711.3µs
1 µs
12V
20 Ω
7/17
L9904
Figure 4. Timing of the ISO-interface
V
TX
0.3 • V
VCC
t
V
K
KL
t
Kf
0.7 • V
t
KH
t
Kr
VCC
0.3 • V
VCC
t
0.55 • V
0.45 • V
V
RX
open drain
transistor at
K-pin
ON
OFF
VS
VS
t
RXL
0.3 • V
VCC
20%
80%
t
RXH
0.7 • V
VCC
IK> I
t
SH
KSC
Figure 5. Timing of the drivers for the external MOS regarding the inputs DIR and PWM
PWM
or
DIR
50%
t
t
8/17
GHX
GLX
80%
20%
80%
20%
t
GHXLHtGHXr
t
GLXHLtGLXf
t
GHXHL
t
GLXLH
t
GHXf
t
GLXr
t
t
t
Figure 6. I(V) characteristics of the K-Line for TX = HIGH and VVS=13.5V
IK [mA]
0.2
L9904
Figure 7. Driving sequence
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-20 -10 0 10 20
Ω
~50k
VK [V]
EN
DIR
Ω
~50k
≈
≈
Note:
Before standby mode
(EN=low) a braking phase
is mandatory to discharge
the stored energy of the
motor.
PWM
GL2
GH2
GL1
GH1
braking
≈≈
≈
9/17
L9904
Figure 8. Charging time of an external capacitor of 10nF connected to CP pin at VVS=8V and
=13.5V
V
VS
voltage [V]
30
25
20
15
10
5
0
01234
Figure 9. Application Circuit Diagram
V
BAT
D1
VS
10
C
C
S2
Voltage
Regulator
µC
V
GND
CC
S1
ST
1
VCC
Overvoltage
Undervoltage
R
DG
DG
EN
DIR
PWM
PR
C
R
PR
PR
RX
TX
Thermal shut down
2
4
R
EN
5
R
DIR
VCC
R
PWM
3
6
Timer
7
R
RX
VCC
R
TX
8
Charging time of a 10nF load at CP
CP for VS=13.5V
CP for VS=8V
EN
time [ms]
R
Refer ence
+
V
=
STH
f
ST
VCC
BIAS
Charge
pump
V
=
S1TH
Control Logic
V
=
S2TH
ISO-Interface
0.5•V
=
VS
I
KH
CP
11
CP
13
CB1
12
GH1
14
S1
R
S1
GL1
19
R
GL1
GL2
18
R
GL2
S2
17
R
S2
GH2
15
CB2
16
K
9
GND
20
R
C
B1
C1
M
R
R
C
B2
R
K-Line
10/17
L9904
3 FUNCTIONAL DESCRIPTION
3.1 General
The L9904 integrated circuit (IC) is designed to control four external N-channel MOS transistors in H-Bridge configuration for DC-motor driving in automotive applications. It includes an ISO9141 compatible interface. A typical
application is shown in fig.9.
3.2 Voltage supply
The IC is supplied via an external reverse battery protection diode to the VVS pin. The typical operating voltage
range is down to 8V.
The supply current consumption of the IC composes of static and a dynamic part. The static current is typically
5.8mA. The dynamical current I
of the external power mos transistor. The current can be estimated by the expression:
An external power transistor with a gate charge of Q
quires a dynamical supply current of I
The total supply current consumption is I
3.3 Extended supply voltage range (ST)
The operating battery voltage range can be extended down to 6V using the additional components shown in
fig.7. A small inductor of L~150
with the switching open drain output ST. The switching frequency is typical 100kHz with a fixed duty cycle of
50%. The step up converter starts below V
at V
> 10V to avoid EME at nominal battery voltage. The diode D2 in series with the ST pin is necessary only
VS
for systems with negative battery voltage. No additional load can be driven by the step up converter.
is depending of the PWM frequency f
dyn
I
µ
H (I
= 2 · f
dyn
= 6.4mA.
dyn
= 5.8mA + 6.4mA = 12.2mA.
VS
~500mA) in series to the battery supply builts up a step up converter
peak
< 8V, increases the supply voltage at the VS pin and switches off
VS
· Q
PWM
Gate
Gate
= 160nC and a PWM frequency of f
and the required gate charge Q
PWM
PWM
Gate
= 20kHz re-
Figure 10.
V
BAT
L1 D1
D2
C1 C2
VS
ST
L9904
-
+
V
=
STH
f
ST
11/17
L9904
3.4 Control inputs (EN, DIR, PWM)
The cmos level inputs drive the device as shown in fig.7 and described in the truth table.
The device is activated with enable input HIGH signal. For enable input floating (not connected) or VEN=0V the
device is in standby mode. When activating the device a wake-up time of 50µs is recommended to stabilize the
internal supplies.
The DIR and PWM inputs control the driver of the external H-Bridge transistors. The motor direction can be
choosen with the DIR input, the duty cycle and frequency with the PWM input. Unconnected inputs are defined
by internal pull up resistors. During wake-up and braking and before disactivating the IC via enable both inputs
should be driven HIGH.
Table 6.
Status Control inputs Device status
Truth table:
Driver stage for external
power MOS
EN DIR
1 0xxxxxx
2 1xx1000LLLL L thermal
3 1xx0100LLLL L overvoltage
4 1xx0010LLLL L undervoltage
5 1xx0001
6 1000000LHHL H
7 1x10000LHLH H braking mode
8 1100000HLLH H
PWM
TS OV UV SC GH1 GL1 GH2 GL2 DG
7)
R
X
R
6)
X
7)
R
6)
6)
X
Diagnostic Comment
R T standby mode
shutdown
6
X
L
short circuit
Symbols: x Don't care R:Resistive output TS:Thermal shutdown
0: Logic LOW or not active L: Output in sink condition OV:Overvoltage
1: Logic HIGH or active H: Output in source condition UV:Undervoltage
T: Tristate SC:Short Circuit
6. Only those external MOS transistors of the H-Bridge which are in short circuit condition are switched off. All others remain driven
by DIR and PWM.
7. See Application Note AN2229
6)
3.5 Thermal shutdown
When the junction temperature exceeds T
the diagnostic DG is LOW until the junction temperature drops below T
all driver are switched in sink condition (L), the K- output is off and
JSD
JSD
- T
JHYST
.
3.6 Overvoltage Shutdown
When the supply voltage VVS exceeds the overvoltage threshold V
all driver are switched in sink condi-
VSOVH
tion (L), the K- output is off and the diagnostic DG is LOW.
3.7 Undervoltage Shutdown
For supply voltages below the undervoltage disable threshold the gate driver remains in sink condition (L) and
the diagnostic DG is low.
12/17
L9904
3.8 Short Circuit Detection
The output voltage at the S1 and S2 pin of the H-Bridge is monitored by comparators to detect shorts to ground
or battery. The activated external highside MOS transistor will be switched off if the voltage drop remains below
the comparator threshold voltage V
transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be
changed. The status doesn't change for the other MOS transistors. The external lowside MOS transistor will be
switched off if the voltage drop passes over the comparator threshold voltage V
the short current detection time t
SCd
until the DIR or PWM input status will be changed. The status doesn't change for the other MOS transistors.
3.9 Diagnostic Output (DG)
The diagnostic output provides a real time error detection, if monitors the following error stacks: Thermal shutdown, overvoltage shutdown , undervoltage shutdown and short circuit shutdown. The open drain output with
internal pull up resistor is LOW if an error is occuring.
3.10 Bootstrap capacitor (CB1,CB2)
To ensure, that the external power MOS transistors reach the required R
of 5V for logic level and 10V for standard power MOS transistors has to be guaranteed. The highside transistors
require a gate voltage higher than the supply voltage. This is achieved with the internal chargepump circuit in
combination with the bootstrap capacitor. The bootstrap capacitor is charged, when the highside MOS transistor
is OFF and the lowside is ON. When the lowside is switched OFF, the charged bootstrap capacitor is able to
supply the gate driver of the highside power MOS transistor. For effective charging the values of the bootstrap
capacitors should be larger than the gate-source capacitance of the power MOS and respect the required PWM
ratio.
S1TH
and V
for longer than the short current detection time t
S2TH
and V
S1TH
for longer than
S2TH
SCd
. The
. The transistor remains in off condition, the diagnostic output goes LOW
, a minimum gate source voltage
DSON
3.11 Chargepump circuit (CP)
The reverse battery protection can be obtained with an external N-channel MOS transistor as shown in fig.6. In
this case its drain-bulk diode provides the protection. The output CP is intended to drive the gate of this transistor above the battery voltage to switch on the MOS and to bypass the drain-bulk diode with the R
CP has a connection to VS through an internal diode and a 20k
Ω
resistor.
DSON
. The
3.12 Gate drivers for the external N-channel power MOS transistors (GH1, GH2, GL1, GL2)
High level at EN activates the driver of the external MOS under control of the DIR and PWM inputs (see truth
table and driving sequence fig.4). The external power MOS gates are connected via series resistors to the device to reduce electro magnetic emission (EME) of the system. The resistors influence the switching behaviour.
They have to be choosen carefully. Too large resistors enlarge the charging and discharging time of the power
MOS gate and can generate cross current in the halfbridges. The driver assures a longer switching delay time
from source to sink stage in order to prevent the cross conduction.
The gate source voltage is limited to 14V. The charge/discharge current is limited by the R
of the driver.
DSON
The drivers are not protected against shorts.
3.13 Programmable cross conduction protection
The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an additional delay time t
t
is determined by the external capacitor CPR and resistor RPR at the PR pin. The capacitor CPR is charged
CCP
up to the voltage limit V
ternal MOS transistor and the charging source at the PR pin. The resistor R
to prevent cross conduction in the halfbridge. The cross conduction protection time
CCP
. A level change on the control inputs DIR and PWM switches off the concerned ex-
PRH
discharges the capacitor CPR.
PR
The concerned external power MOS transistor will be switched on again when the voltage at PR reaches the
value of V
and 1nF. The resistor R
. After that the CPR will be charged again. The capacitor CPR should be choosen between 100pF
PRL
should be higher than 7kW. The delay time can be expressed as follows:
PR
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L9904
K
t
= RPR · CPR · ln NPR with NPR= V
CCP
t
= 0.69 · RPR · CPR
CCP
3.14 ISO-Interface
The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate
up to 60kbit/s via a single wire which is V
and GND compatible. The logic level transmission input TX drives
BAT
the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to V
pin is protected against overvoltage, short to GND and VS and can be driven beyond V
or GND the output shows high impedance characteristic. The open drain output RX with an internal pull
of V
VS
up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short
circuit condition at K-pin is recognized if the internal open drain transistor isn't able to pull the voltage potential
at K-pin below the threshold of 0.45·V
. Then the RX stays in high condition. A timer starts and switches the
VS
open drain transistor after typ. 20µs off. A next low at the TX input resets the timer and the open drain transistor
switches on again.
Figure 11. Functional schematic of the ISO-interface
RX
PRH
/ V
PRL
= 2
. The K-
and GND. During lack
VS
BAT
TX
R
RX
0.5 •V
R
=
delay
T
SH
V
CC
R
TX
R
Q
S
VS
I
KH
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Figure 12. SO20 Mechanical Data & Package Dimensions
L9904
DIM.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
(1)
D
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “D” dimension does not include mold flash, pro tusions or gate
burrs. Mold flash, protusions or g ate burrs shall not exceed
0.15mm per side.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
12.60 13.00 0.496 0.512
OUTLINE AND
MECHANICAL DATA
SO20
0016022 D
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Table 7. Revision History
Date Revision Description of Changes
October 2002 1 First Issue on ST-Press DMS
January 2004 2 Migration from ST-Press to EDOCS DMS
May 2004 3 Change Maturity from Product Preview to Final.
October 2005 4 Inserted on pag 12 AN2229 ref.
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L9904
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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