ST L9904 User Manual
L9904
MOTOR BRIDGE CONTROLLER
1 FEATURES |
Figure 1. Package |
■OPERATING SUPPLY VOLTAGE 8V TO 28V, OVERVOLTAGE MAX. 40V
■OPERATING SUPPLY VOLTAGE 6V WITH IMPLEMENTED STEPUP CONVERTER
■QUIESCENT CURRENT IN STANDBY MODE LESS THAN 50µA
■ISO 9141 COMPATIBLE INTERFACE
■CHARGE PUMP FOR DRIVING A POWER MOS AS REVERSE BATTERY PROTECTION
■PWM OPERATION FREQUENCY UP TO 30KHZ
■PROGRAMMABLE CROSS CONDUCTION PROTECTION TIME
■OVERVOLTAGE, UNDERVOLTAGE, SHORT CIRCUIT AND THERMAL PROTECTION
■REAL TIME DIAGNOSTIC
Figure 2. Block Diagram
SO20 |
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Table 1. Order Codes |
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Part Number |
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Package |
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L9904 |
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SO20 |
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L9904TR |
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Tape & Reel |
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2 DESCRIPTION
Control circuit for power MOS bridge driver in automotive applications with ISO 9141bus interface.
VS |
10 |
ST |
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1 |
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+ |
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= VSTH
fST
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VCC |
Overvoltage |
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DG |
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2 |
RDG |
Undervoltage |
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Thermal shutdown |
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EN |
4 |
REN
DIR 
5
RDIR
VCC
RPWM
PWM 
3 
PR |
6 |
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Timer |
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RX |
7 |
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RRX
VCC
RTX
TX |
8 |
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Reference
BIAS
Control Logic
ISO-Interface
= 0.5 • VVS
RCP
VCC
Charge 11 CP pump
13 |
CB1 |
12 |
GH1 |
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14 |
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S1 |
V |
S1TH |
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RS1 |
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19 GL1
RGL1
18
GL2
RGL2
17
S2
V S2TH = |
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RS2 |
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15 |
GH2 |
16 |
CB2 |
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9 |
K |
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I KH |
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20 |
GND |
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REV. 4 |
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October 2005 |
1/17 |
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L9904
Table 2. Pin Function
N° |
Pin |
Description |
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1 |
ST |
Open Drain Switch for Stepup converter |
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2 |
DG |
Open drain diagnostic output |
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3 |
PWM |
PWM input for H-bridge control |
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4 |
EN |
Enable input |
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5 |
DIR |
Direction select input for H-bridge control |
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6 |
PR |
Programmable cross conduction protection time |
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7 |
RX |
ISO 9141 interface, receiver output |
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8 |
TX |
ISO 9141 interface, transmitter input |
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9 |
K |
ISO 9141 Interface, bidirectional communication K-line |
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10 |
VS |
Supply voltage |
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11 |
CP |
Charge pump for driving a power MOS as reverse battery protection |
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12 |
GH1 |
Gate driver for power MOS highside switch in halfbridge 1 |
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13 |
CB1 |
External bootstrap capacitor |
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14 |
S1 |
Source/drain of halfbridge 1 |
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15 |
GH2 |
Gate driver for power MOS highside switch in halfbridge 2 |
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16 |
CB2 |
External bootstrap capacitor |
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17 |
S2 |
Source/drain of halfbridge 2 |
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18 |
GL2 |
Gate driver for power MOS lowside switch in halfbridge 2 |
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19 |
GL1 |
Gate driver for power MOS lowside switch in halfbridge 1 |
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20 |
GND |
Ground |
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Figure 3. Pin Connection (Top view)
ST |
1 |
20 |
GND |
DG |
2 |
19 |
GL1 |
PWM |
3 |
18 |
GL2 |
EN |
4 |
17 |
S2 |
DIR |
5 |
16 |
CB2 |
PR |
6 |
15 |
GH2 |
RX |
7 |
14 |
S1 |
TX |
8 |
13 |
CB1 |
K |
9 |
12 |
GH1 |
VS |
10 |
11 |
CP |
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SO20 |
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2/17
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L9904 |
Table 3. Absolute Maximum Ratings |
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Symbol |
Parameter |
Value |
Unit |
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VCB1 , VCB2 |
Bootstrap voltage |
-0.3 to 40 |
V |
ICB1 , ICB2 |
Bootstrap current |
-100 |
mA |
VCP |
Charge pump voltage |
-0.3 to 40 |
V |
ICP |
Charge pump current |
-1 |
mA |
VDIR ,VEN |
Logic input voltage |
-0.3 to 7 |
V |
,VPWM ,VTX |
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IDIR ,IEN |
Logic input current |
±1 |
mA |
,IPWM ,ITX |
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VDG ,VRX |
Logic output voltage |
-0.3 to 7 |
V |
IDG ,IRX |
Logic output current |
-1 |
mA |
VGH1, VGH2 |
Gate driver voltage |
-0.3 to VSX + 10 |
V |
IGH1 , IGH2 |
Gate driver current |
-1 |
mA |
VGL1 , VGL2 |
Gate driver voltage |
-0.3 to 10 |
V |
IGL1 , IGL2 |
Gate driver current |
-10 |
mA |
VK |
K-line voltage |
-20 to VS |
V |
VPR |
Programming input voltage |
-0.3 to 7 |
V |
IPR |
Programming input current |
-1 |
mA |
VS1 , VS2 |
Source/drain voltage |
-2 to VVS + 2 |
V |
IS1 , IS2 |
Source/drain current |
-10 |
mA |
VST |
Output voltage |
-0.3 to 40 |
V |
IST |
Step up output current |
-1 |
mA |
VVSDC |
DC supply voltage |
-0.3 to 28 |
V |
VVSP |
Pulse supply voltage (T < 500ms) |
40 |
V |
IVS |
DC supply current |
-100 |
mA |
For externally applied voltages or currents exceeding these limits damage of the device may occur!
All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body model with R=1.5kΩ, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of 0.2mJ.
Table 4. Thermal Data
Symbol |
Parameter |
Value |
Unit |
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TJ |
Operating junction temperature |
-40 to 150 |
°C |
TJSD |
Junction temperature thermal shutdown threshold |
min 150 |
°C |
TJSDH |
Junction thermal shutdown hysteresis |
typ 15 |
°C |
Rth j-amb |
Thermal resistance junction to ambient 1) |
85 |
°C/W |
1. see application note 110 for SO packages.
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3/17
L9904
Table 5. Electrical Characteristcs |
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(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ |
≤ 150°C, unless otherwise specified. The voltages are refered to |
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GND and currents are assumed positive, when current flows into the pin |
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Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Unit |
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Supply (VS) |
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VVS OVH |
Overvoltage disable HIGH |
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28 |
33 |
36 |
V |
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threshold |
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VVS OVh |
Overvoltage threshold hysteresis 2) |
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1.6 |
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VVS UVH |
Undervoltage disable HIGH |
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6 |
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7 |
V |
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threshold |
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VVS UVh |
Undervoltage threshold |
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0.66 |
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V |
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hysteresis 2) |
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IVSL |
Supply current |
VEN = 0 ; VVS = 13.5V; TJ< 85°C |
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50 |
µA |
IVSH |
Supply current, pwm-mode |
VVS= 13.5V; VEN= HIGH; |
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8.1 |
13 |
mA |
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VDIR= LOW; S1 = S2 = GND |
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fPWM = 20kHz; CCBX = 0.1µF; |
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CGLX = 4.7nF; CGHX = 4.7nF; |
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RPR = 10kΩ; CPR = 150pF |
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IVSD |
Supply current, dc-mode |
VVS= 13.5V; VEN= HIGH; |
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5.8 |
10 |
mA |
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VDIR= LOW; S1 = S2 = GND |
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VPWM = LOW; CGHX = 4.7nF |
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RPR = 10kΩ; CPR = 150pF |
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Enable input (EN) |
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VENL |
Low level |
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1.5 |
V |
VENH |
High level |
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3.5 |
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V |
VENh |
Hysteresis threshold 2) |
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1 |
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V |
REN |
Input pull down resistance |
VEN = 5V |
16 |
50 |
100 |
kΩ |
H-bridge control inputs (DIR, PWM) |
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VDIRL |
Input low level |
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1.5 |
V |
VPWML |
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VDIRH |
Input high level |
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3.5 |
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V |
VPWMH |
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VDIRh |
Input threshold hysteresis 2) |
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1 |
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V |
VPWMh |
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RDIR |
Internal pull up resistance |
VDIR = 0; VPWM = 0 |
16 |
50 |
100 |
kΩ |
RPWM |
to internal VCC 3) |
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DIAGNOSTIC output (DG) |
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VDG |
Output drop |
IDG = 1mA |
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0.6 |
V |
RDG |
Internal pull up resistance |
VDG = 0V |
10 |
20 |
40 |
kΩ |
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to internal VCC 3) |
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Programmable cross conduction protection 4) |
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NPR |
Threshold voltage ratio VPRH/ |
RPR = 10kΩ |
1.8 |
2 |
2.2 |
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VPRL |
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IPR |
Current capability |
VPR = 2V |
-0.5 |
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mA |
ISO interface, transmission input (TX) |
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VTXL |
Input low level |
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1.5 |
V |
4/17 |
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L9904 |
Table 5. Electrical Characteristcs (continued) |
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(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ |
≤ 150°C, unless otherwise specified. The voltages are refered to |
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GND and currents are assumed positive, when current flows into the pin |
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Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Unit |
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VTXH |
Input high level |
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3.5 |
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V |
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VTXh |
Input hysteresis voltage 2) |
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1 |
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V |
RTX |
Internal pull up resistance to |
VTX = 0 |
10 |
20 |
40 |
kΩ |
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internal VCC 3) |
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ISO interface, receiver output (RX) |
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VRXL |
Output voltage high stage |
TX = HIGH; IRX = 0; VK = VVS |
4.5 |
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5.5 |
V |
RRX |
Internal pull up resistance |
TX = HIGH; |
5 |
10 |
20 |
kΩ |
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to internal VCC 3) |
VRX = 0V |
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RRXON |
ON resistance to ground |
TX = LOW; |
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40 |
90 |
Ω |
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IRX = 1mA |
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tRXH |
Output high delay time |
Fig. 1 |
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0.5 |
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µs |
tRXL |
Output low delay time |
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0.5 |
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µs |
ISO interface, K-line (K) |
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VKL |
Input low level |
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-20V |
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0.45 · |
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VVS |
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VKH |
Input high level |
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0.55 · |
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VVS |
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VVS |
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VKh |
Input hysteresis voltage 2) |
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0.025· |
0.8V |
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VVS |
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IKH |
Input current |
VTX = HIGH |
-5 |
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25 |
µA |
RKON |
ON resistance to ground |
VTX = LOW; IK=10mA |
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10 |
30 |
Ω |
IKSC |
Short circuit current |
VTX = LOW |
40 |
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130 |
mA |
fK |
Transmission frequency |
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60 |
100 |
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kHz |
2.not tested in production: guaranteed by design and verified in characterization
3.Internal VVCC is 4.5V ... 5.5V
4.see page 18 for calculation of programmable cross conduction protection time
tKr |
Rise time |
VVS = 13.5V; Fig. 1 |
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2 |
6 |
µs |
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External loads at K-line: |
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RK = 510Ω pull up |
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to VVS |
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CK = 2.2nF to GND |
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tKf |
Fall time |
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2 |
6 |
µs |
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tKH |
Switch high delay time |
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4 |
17 |
µs |
tKL |
Switch low delay time |
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4 |
17 |
µs |
tSH |
Short circuit detection time |
VVS = 13.5V; |
10 |
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40 |
µs |
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TX = LOW |
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VK > 0.55 · VVS |
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Charge pump |
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VCP |
Charge pump voltage |
VVS = 8V |
VVS+ |
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VVS+ |
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7V |
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14V |
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VVS = 13.5V |
VVS+ |
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VVS+ |
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10V |
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14V |
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VVS = 20V |
VVS+ |
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VVS |
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10V |
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+14V |
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5/17
L9904
Table 5. Electrical Characteristcs (continued) |
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(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ |
≤ 150°C, unless otherwise specified. The voltages are refered to |
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GND and currents are assumed positive, when current flows into the pin |
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Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Unit |
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ICP |
Charging current |
VVS = 13.5V |
-50 |
-75 |
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µA |
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VCP= VVS + 8V |
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tCP |
Charging time 2) |
VVS = 13.5V |
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1.2 |
4 |
ms |
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VCP= VVS + 8V |
CCP = 10nF |
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fCP |
Charge pump frequency |
VVS = 13.5V |
250 |
500 |
750 |
kHz |
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Drivers for external highside power MOS |
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VCB1 |
Bootstrap voltage |
VVS = 8V; ICBX = 0; VSX = 0 |
7.5 |
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14 |
V |
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VCB2 |
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VVS =13.5V; ICBX = 0; VSX = 0 |
10 |
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14 |
V |
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VVS = 20V; ICBX = 0; VSX = 0 |
10 |
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14 |
V |
RGH1L |
ON-resistance of SINK stage |
VCBX = 8V; VSX = 0 |
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10 |
Ω |
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RGH2L |
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IGHX = 50mA; TJ = 25°C |
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VCBX = 8V; VSX = 0 |
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20 |
Ω |
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IGHX = 50mA; TJ = 125°C |
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RGH1H |
ON-resistance of SOURCE stage |
IGHX = -50mA; TJ = 25°C |
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10 |
Ω |
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RGH2H |
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IGHX = -50mA; TJ = 125°C |
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20 |
Ω |
VGH1H |
Gate ON voltage (SOURCE) |
VVS= VSX = 8V; IGHX = 0; |
VVS |
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VVS |
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VGH2H |
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CCBX = 0.1µF |
+6.5V |
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+14V |
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VVS = VSX = 13.5V; IGHX = 0; |
VVS+ |
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VVS |
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CCBX = 0.1µF |
10V |
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+14V |
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VVS = VSX = 20V; IGHX = 0; |
VVS |
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VVS |
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CCBX = 0.1µF |
+10V |
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+14V |
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RGH1 |
Gate discharge resistance |
EN = LOW |
10 |
100 |
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kΩ |
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RGH2 |
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RS1 |
Sink resistance |
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10 |
100 |
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kΩ |
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RS2 |
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Drivers for external lowside power MOS |
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RGL1L |
ON-resistance of SINK stage |
IGLX = 50mA; TJ = 25°C |
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10 |
Ω |
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RGL2L |
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IGLX = 50mA; TJ = 125°C |
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20 |
Ω |
RGL1H, |
ON-resistance of SOURCE stage |
IGLX = -50mA; TJ = 25°C |
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10 |
Ω |
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RGL2H |
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IGLX = -50mA; TJ = 125°C |
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20 |
Ω |
VGL1H, |
Gate ON voltage (SOURCE) |
VVS = 8V; IGLX = 0 |
7V |
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VVS |
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VGL2H |
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VVS = 13.5V; IGLX = 0 |
10V |
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VVS |
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VVS = 20V; IGLX = 0 |
10V |
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14V |
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RGL1 |
Gate discharge resistance |
EN = LOW |
10 |
100 |
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kΩ |
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RGL2 |
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2. not tested in production: guaranteed by design and verified in characterization |
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Timing of the drivers |
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tGH1LH |
Propagation delay time |
Fig. 2 |
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500 |
ns |
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tGH2LH |
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VVS = 13.5V |
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VS1 = VS2 =0 |
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CCBX = 0.1µF |
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RPR= 10kW |
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6/17
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