ST L9904 User Manual

L9904

Fi

MOTOR BRIDGE CONTROLLER

1 FEATURES

■ OPERATING SUPPLY VOLTAGE 8V TO 28V,

OVERVOLTAGE MAX. 40V

■ OPERATING SUPPLY VOLTAGE 6V WITH

IMPLEMENTED STEPUP CONVERTER

■ QUIESCENT CURRENT IN STANDBY MODE

LESS THAN 50µA

■ ISO 9141 COMPATIBLE INTERFACE

■ CHARGE PUMP FOR DRIVING A POWER

MOS AS REVERSE BATTERY PROTECTION

■ PWM OPERATION FREQUENCY UP TO

30KHZ

■ PROGRAMMABLE CROSS CONDUCTION

PROTECTION TIME

■ OVERVOLTAGE, UNDERVOLTAGE, SHORT

CIRCUIT AND THERMAL PROTECTION

■ REAL TIME DIAGNOSTIC

Figure 2. Block Diagram

10

VS

VCC

-

+

f

Overvolt age

Undervoltage

Thermal shutdown

Timer

=

V

STH

ST

PWM

1

ST

R

DG

2

DG

4

EN

R

EN

5

DIR

R

DIR

R

PWM

3

6

PR

gure 1. Package

SO20

Table 1. Order Codes

Part Number Package

L9904 SO20

L9904TR Tape & Reel

2 DESCRIPTION

Control circuit for power MOS bridge driver in automotive applications with ISO 9141bus interface.

R

Reference

BIAS

VCC

Charge pump

=

V

S1TH

Control Logic

=

V

S2TH

CP

11

CP

13

CB1

12

GH1

14

S1

R

S1

19

GL1

R

GL1

18

GL2

R

GL2

17

S2

R

S2

15

GH2

16

CB2

October 2005

7

RX

R

RX

VCC

R

TX

8

TX

ISO-Interface

=

0.5 • V VS

I

KH

9

K

20

GND

REV. 4

1/17

L9904

Table 2. Pin Function

N° Pin Description

1 ST Open Drain Switch for Stepup converter

2 DG Open drain diagnostic output

3 PWM PWM input for H-bridge control

4 EN Enable input

5 DIR Direction select input for H-bridge control

6 PR Programmable cross conduction protection time

7 RX ISO 9141 interface, receiver output

8 TX ISO 9141 interface, transmitter input

9 K ISO 9141 Interface, bidirectional communication K-line

10 VS Supply voltage

11 CP Charge pump for driving a power MOS as reverse battery protection

12 GH1 Gate driver for power MOS highside switch in halfbridge 1

13 CB1 External bootstrap capacitor

14 S1 Source/drain of halfbridge 1

15 GH2 Gate driver for power MOS highside switch in halfbridge 2

16 CB2 External bootstrap capacitor

17 S2 Source/drain of halfbridge 2

18 GL2 Gate driver for power MOS lowside switch in halfbridge 2

19 GL1 Gate driver for power MOS lowside switch in halfbridge 1

20 GND Ground

Figure 3. Pin Connection (Top view)

ST

DG

PWM

EN

DIR

PR

RX

TX

K GH1

VS CP

2

3

4

5

6

7

8

9

10

SO20

20

19

18

17

16

15

14

13

12

11

GND1

GL1

GL2

S2

CB2

GH2

S1

CB1

2/17

L9904

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit

V

, V

CB1

, I

I

CB1

V

CP

I

CP

,V

V

DIR

,V

PWM ,VTX

,I

I

DIR

,I

PWM ,ITX

,V

V

DG

,IRX Logic output current -1 mA

I

DG

, V

V

GH1

, I

I

GH1

, V

V

GL1

, I

I

GL1

V

PR

I

PR

, V

V

S1

, I

I

S1

V

ST

I

ST

V

VSDC

V

VSP

I

VS

For externally applied voltages or currents exceeding these limits damage of the device may occur! All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body

model with R=1.5k

0.2mJ.

Bootstrap voltage -0.3 to 40 V

CB2

Bootstrap current -100 mA

CB2

Charge pump voltage -0.3 to 40 V

Charge pump current -1 mA

Logic input voltage -0.3 to 7 V

EN

Logic input current ±1 mA

EN

Logic output voltage -0.3 to 7 V

RX

Gate driver voltage -0.3 to VSX + 10 V

GH2

Gate driver current -1 mA

GH2

Gate driver voltage -0.3 to 10 V

GL2

Gate driver current -10 mA

GL2

K-line voltage -20 to V

K

S

Programming input voltage -0.3 to 7 V

Programming input current -1 mA

Source/drain voltage -2 to VVS + 2 V

S2

Source/drain current -10 mA

S2

Output voltage -0.3 to 40 V

Step up output current -1 mA

DC supply voltage -0.3 to 28 V

Pulse supply voltage (T < 500ms) 40 V

DC supply current -100 mA

Ω

, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of

V

Table 4. Thermal Data

Symbol Parameter Value Unit

T

JSD

T

JSDH

R

th j-amb

1. see application note 110 for SO packages.

Operating junction temperature -40 to 150 °C

J

Junction temperature thermal shutdown threshold min 150 °C

Junction thermal shutdown hysteresis typ 15 °C

Thermal resistance junction to ambient

1)

85 °C/W

.

3/17

L9904

Table 5.

Electrical Characteristcs

(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin

Symbol Parameter Test Condition Min. Typ. Max. Unit

Supply (VS)

V

VS OVH

V

VS OVh

V

VS UVH

V

VS UVh

I

VSL

I

VSH

I

VSD

Enable input (EN)

V

R

H-bridge control inputs (DIR, PWM)

V

DIRL

V

PWML

V

DIRH

V

PWMH

V

DIRh

V

PWMh

R

PWM

DIAGNOSTIC output (DG)

V

R

Programmable cross conduction protection

N

I

ISO interface, transmission input (TX)

V

Overvoltage disable HIGH

28 33 36 V

threshold

Overvoltage threshold hysteresis

Undervoltage disable HIGH

2)

67V

1.6 V

threshold

Undervoltage threshold hysteresis

2)

0.66 V

Supply current VEN = 0 ; VVS = 13.5V; TJ< 85°C 50 µA

Supply current, pwm-mode VVS= 13.5V; VEN= HIGH;

= LOW; S1 = S2 = GND

V

DIR

f

PWM

C

GLX

R

PR

= 20kHz; C

= 4.7nF; C

= 10kΩ; C

CBX

GHX

= 150pF

PR

= 0.1µF;

= 4.7nF;

Supply current, dc-mode VVS= 13.5V; VEN= HIGH;

V

= LOW; S1 = S2 = GND

DIR

= LOW; C

V

PWM

= 10kΩ; C

R

PR

Low level 1.5 V

ENL

High level 3.5 V

ENH

ENh

Hysteresis threshold

Input pull down resistance VEN = 5V 16 50 100 kΩ

EN

2)

GHX

= 150pF

PR

= 4.7nF

8.1 13 mA

5.8 10 mA

1V

Input low level 1.5 V

Input high level 3.5 V

Input threshold hysteresis

Internal pull up resistance

DIR

to internal VCC

Output drop IDG = 1mA 0.6 V

DG

Internal pull up resistance

DG

to internal VCC

Threshold voltage ratio V

PR

V

PRL

Current capability

PR

Input low level 1.5 V

TXL

3)

2)

PRH

1V

V

DIR

= 0; V

= 0 16 50 100 kΩ

PWM

VDG = 0V 10 20 40 kΩ

4)

R

V

PR

= 10kΩ

= 2V

/

1.822.2

-0.5 mA

4/17

L9904

Table 5.

(8V < V

Electrical Characteristcs

< 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to

VS

(continued)

GND and currents are assumed positive, when current flows into the pin

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

R

ISO interface, receiver output (RX)

V

R

RXON

t

RXH

t

RXL

ISO interface, K-line (K)

V

I

R

I

KSC

t

Charge pump

V

Input high level 3.5 V

TXH

Input hysteresis voltage 2) 1 V

TXh

Internal pull up resistance to

TX

VTX = 0 102040kΩ

internal VCC 3)

Output voltage high stage

RXL

Internal pull up resistance

RX

to internal VCC

3)

ON resistance to ground TX = LOW;

TX = HIGH; I

TX = HIGH;

= 0V

V

RX

= 1mA

I

RX

= 0; V

= V

K

VS

4.5 5.5 V

51020kΩ

40 90 Ω

Output high delay time Fig. 1 0.5 µs

Output low delay time 0.5 µs

Input low level -20V 0.45 ·

KL

Input high level

KH

Input hysteresis voltage 2) 0.025·

Kh

Input current VTX = HIGH -5 25 µA

KH

ON resistance to ground VTX = LOW; IK=10mA 10 30 Ω

KON

0.55 · V

VS

V

VS

Short circuit current VTX = LOW 40 130 mA

Transmission frequency 60 100 kHz

f

K

2. not tested in production: guaranteed by design and verified in characterization

3. Internal V

4. see page 18 for calculation of programmable cross conduction protection time

Rise time VVS = 13.5V; Fig. 1

Kr

is 4.5V ... 5.5V

VCC

26µs

External loads at K-line:

= 510Ω pull up

R

K

to V

VS

C

= 2.2nF to GND

K

Fall time 26µs

Kf

Switch high delay time 4 17 µs

KH

Switch low delay time 4 17 µs

KL

Short circuit detection time VVS = 13.5V;

SH

10 40 µs

TX = LOW

> 0.55 · V

V

Charge pump voltage VVS = 8V

CP

K

VS

V

+

VS

7V

V

VS

= 13.5V

+

V

VS

10V

V

= 20V

VS

+

V

VS

10V

V

VS

V

VS

0.8V

VVS+

14V

V

VS

14V V

VS

+14V

+

5/17

L9904

Table 5.

(8V < V

Electrical Characteristcs

< 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to

VS

(continued)

GND and currents are assumed positive, when current flows into the pin

Symbol Parameter Test Condition Min. Typ. Max. Unit

I

t

CP

Charging current

= VVS + 8V

V

CP

Charging time

2)

VCP= VVS + 8V

f

Charge pump frequency VVS = 13.5V 250 500 750 kHz

CP

Drivers for external highside power MOS

V V

R R

V V

R R

GH1L

GH2L

GH1H

GH2H

GH1H

GH2H

Bootstrap voltage VVS = 8V; I

CB1

CB2

ON-resistance of SINK stage

ON-resistance of SOURCE stage I

Gate ON voltage (SOURCE) VVS= VSX = 8V; I

Gate discharge resistance EN = LOW 10 100 kΩ

GH1

GH2

Sink resistance 10 100 kΩ

S1

S2

Drivers for external lowside power MOS

R

GL1L

R

GL2L

R

GL1H,

R

GL2H

V

GL1H,

V

GL2H

R R

2. not tested in production: guaranteed by design and verified in characterization

ON-resistance of SINK stage I

ON-resistance of SOURCE stage I

Gate ON voltage (SOURCE) VVS = 8V; I

Gate discharge resistance EN = LOW 10 100 kΩ

GL1

GL2

Timing of the drivers

t

GH1LH

t

GH2LH

Propagation delay time Fig. 2

V

= 13.5V -50 -75 µA

VS

V

= 13.5V

VS

C

= 10nF

CP

VVS =13.5V; I V

= 20V; I

VS

V

CBX

I

GHX

V

CBX

I

GHX

I

GHX

C

CBX

= VSX = 13.5V; I

V

VS

C

CBX

= VSX = 20V; I

V

VS

C

CBX

GLX

I

GLX

I

GLX

V

= 13.5V; I

VS

= 20V; I

V

VS

CBX

= 8V; VSX = 0

= 50mA; T

= 8V; VSX = 0

= 50mA; T

= -50mA; TJ = 25°C = -50mA; TJ = 125°C

= 0.1µF

= 50mA; TJ = 25°C = 50mA; TJ = 125°C

= -50mA; TJ = 25°C = -50mA; TJ = 125°C

= 0

GLX

= 0; VSX = 0

= 25°C

J

= 125°C

J

= 0;

GHX

= 0;

GHX

= 0;

GHX

= 0

7.5

10 10

V

VS

+6.5V

V

VS

10V

V

VS

+10V

7V 10V 10V

1.2 4 ms

+

14 14 14

10 Ω

20 Ω

10 20

V

VS

+14V

V

VS

+14V

V

VS

+14V

10 20

V

VS

V

VS

14V

500 ns

= 13.5V

V

VS

VS1 = VS2 =0 C

= 0.1µF

CBX

V V V

Ω Ω

6/17

RPR= 10kW