ST L9823 User Manual

L9823

Octal low-side driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic

Features

■Outputs current capability up to 0.5 A

■Cascadable SPI control for outputs

■Reset function with reset signal or undervoltage at VDD

■Programmable intrinsic output voltage clamping at typ. 50 V for inductive switching

■Overcurrent shutdown with latch-off for every write cycle (SFPD = low)

■Independent thermal shutdown of outputs (SOA Protection)

■Output status data available on the SPI using 8-bit I/O protocol up to 3.0 MHz

■Low standby current with reset = low (typ. 35 µA @ VDD)

■Open load detection (outputs off)

■Single VDD logic supply

■High EMS immunity and low EME (controlled output slopes)

■Full functionality of the remaining device at negative voltage drop on outputs (-1.5 V or -3.0 A)

'!0'03

SO24

■Output mode programmable for sustained current limit or shutdown

Description

L9823 is a octal low-side driver circuit, dedicated for automotive applications.

Output voltage clamping is provided for flyback current recirculation, when inductive loads are driven.

Chip select and cascadable serial 8-bit Interface for outputs control and diagnostic data transfer.

Table 1.	Device summary
	Order code	Package	Packing
	L9823	SO24	Tube
	E-L9823	SO24	Tube

April 2011

Doc ID 7791 Rev 5

1/19

www.st.com

Contents	L9823

Contents

1	Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
	1.1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.2	Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
2	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9

2.4Power outputs characteristics for flyback current, outputs short circuit protection and diagnostics 12

3	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.1	General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.2	Output stages control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.3	Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
4	Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
5	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18

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L9823	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Outputs Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Diagnostic for outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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List of figures	L9823

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Output control register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. Timing of the serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Pulse diagram to read the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Structure of the outputs status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Typical application circuit diagram for the L9823 circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. SO24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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L9823	Block diagram and pins description

1 Block diagram and pins description

1.1Block diagram

Figure 1. Block diagram

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1.2Pins description

Figure 2. Pins connection (top view)

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	Block diagram and pins description			L9823
	Table 2.	Pins description
	N#	Pin	Description
	1	OUT7	Output 7
	2	OUT6	Output 6
			The system clock pin (SCLK) clocks the internal shift registers of the L9823. The serial input
			pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while
			the serial output pin (SO) shifts data information out of the shift register on the rising edge of
			the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of
	3	SCLK	data. It is essential that the SCLK pin be in a logic low state whenever chip select bar pin
			(CSB) makes any transition. For this reason, it is recommended though not necessary, that
			the SCLK pin be kept in a low logic state as long as the device is not accessed (CSB in logic
			high state). When CSB is in a logic high state, any signal at the SCLK and SI pin is ignored
			and SO is tri-stated (high-impedance).
			This pin is for the input of serial instruction data. SI information is read in on the falling edge of
			SCLK. A logic high state present on this pin when the SCLK signal rises will program a
			specific output OFF, and in turn, turns OFF the specific output on the rising edge of the CSB
			signal. Conversely, a logic low state present on the SI pin will program the output ON, and in
			turn, turns ON the specific output on the rising edge of the CSB signal. To program the eight
	4	SI	outputs of the L9823 ON or OFF, an eight bit serial stream of data is required to be entered
			into the SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For
			each rise of the SCLK signal, with CSB held in a logic low state, a databyte instruction (ON or
			OFF) is loaded into the shift register per the databyte SI state. The shift register is full after
			eight bits of information have been entered. To preserve data integrity, care should be taken to
			not transition SI as SCLK transitions from a low-to-high logic state.
	5	GND	GND
	6	GND	GND
	7	GND	GND
	8	GND	GND
			The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin
			remains in a high impedance state until the CSB pin goes to a logic low state. The SO data
			reports the drain status, either high or low. The SO pin changes state on the rising edge of
	9	SO	SCLK and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the
			corresponding SO databyte is a high state. When SO an output is ON, and there is no fault,
			the corresponding databyte on the SO pin will be a low logic state. The SI / SO shifting of data
			follows a first-in-first-out protocol with both input and output words transferring the Most
			Significant Bit (MSB) first. The SO pin is not affected by the status of the Reset pin.
			The system MCU selects the L9823 to be communicated with through the use of the CSB pin.
			Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823
			and vise versa. Clocked-in data from the MCU is transferred from the L9823 shift register and
			latched into the power outputs on the rising edge of the CSB signal. On the falling edge of the
	10	CSB	CSB signal, drain status information is transferred from the power outputs and loaded into the
			device's shift register. The CSB pin also controls the output driver of the serial output pin.
			Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowing
			information to be transferred from the L9823 to the MCU. To avoid any spurious data, it is
			essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic
			low state.
	11	OUT5	Output 5
	12	OUT4	Output 4
	13	OUT3	Output 3

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