ST L9659 User Manual

L9659

Octal squib driver ASIC for safety application

Features

■8 deployment drivers with SPI selectable firing current and times

■Capability to deploy the squib with 1.2 A (min)/2 ms, 1.75 A (min)/1.0 ms and 1.75 A (min)/0.65 ms between VRES of 7 V to 37 V

■Capability to deploy the squib with 1.5 A (min)/2 ms between VRES of 7 V to 25 V

■Firing capability to deploy all channels simultaneously

'!0'03

LQFP64 (10x10x1.4mm)

■Independently controlled high-side and lowside MOS for diagnosis

■Analog output available for resistance measurement

■Squib short to ground, short to battery and MOS diagnostic available on SPI register

■Capability to deploy the squib the low side MOS is shorted to ground

■4 fire enable inputs

■5.5 MHz SPI interface

■Low voltage internal reset

■2 kV ESD capability on all pins

■Package: LQFP64

Table 1. Device summary

■Technology: ST proprietary BCD5 (0.65 µm)

■RoHS compliant

Description

The L9659 is intended to deploy up to 8 squibs. Squib drivers are sized to deploy 1.2 A minimum for 2 ms, 1.75 A minimum for 1 ms and 1.75 A minimum for 0.65 ms during load dump along with 1.5 A minimum for 2 ms for VRES voltages less than 25 V.

Full diagnostic capabilities of the squib interface are provided.

Order code	Amb. temp range, °C	Package	Packing
L9659	-40 to +95	LQFP64	Tray
L9659TR	-40 to +95	LQFP64	Tape and reel

July 2011

Doc ID 022048 Rev 1

1/51

www.st.com

Contents	L9659

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
	1.1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.3	Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8

2	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.2	Absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . .	10
	2.3	Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11

2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.2 Electrical characteristics - Squib deployment drivers and diagnostics . . 12 2.4.3 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	3.1	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.2	General functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19

3.2.1 Power on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 RESETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 Reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.4 Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.5 VRESx capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.6 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.7 Ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1 SPI pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

	3.4	Squib drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
		3.4.1	Firing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
		3.4.2	Firing current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
		3.4.3	Fire enable (FEN) function description . . . . . . . . . . . . . . . . . . . . . . . . .	26
		3.4.4	Squib diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
		3.4.5	SPI register definition for squib functions . . . . . . . . . . . . . . . . . . . . . . . .	31
4	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			49
5	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			50

2/51	Doc ID 022048 Rev 1

L9659	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. General - DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics . . . . . . . . . . . . . 12 Table 8. SPI timing - DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Features that are accessed/controlled for the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. SPI MOSI/MISO response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. How faults shall be interpreted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. Diagnostic Mode HSS selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. Diagnostic mode 3 VRESx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14. MISO responses to various events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 15. Command description summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 16. Configuration mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 17. Configuration mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 18. Deployment mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 19. Deployment mode 2 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 20. Diagnostic selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 21. Diagnostic mode LS FET selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 22. Diagnostic mode HS FET selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 23. Diagnostic mode HSS selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 24. Diagnostic mode VRESx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 25. Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 26. MOSI diagnostic mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 27. DEPLOY_STATUSx flag and the DEPLOY_SUCCESSx flag conditions. . . . . . . . . . . . . . 44 Table 28. MOSI monitor mode 2 Bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 29. Current measurement channel selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 30. MOSI monitor mode 3 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 31. MOSI monitor mode 4 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 32. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Doc ID 022048 Rev 1

3/51

List of figures	L9659

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. MOS settling time and turn-on time 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. MISO loading for disable time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. POR timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Deployment drivers diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Driver activation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. Squib diagnostics block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10. LQFP64 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4/51	Doc ID 022048 Rev 1

L9659	Block diagram and pin description

1 Block diagram and pin description

1.1Block diagram

Figure 1. Block diagram

#3?$ 3#,+ -/3) -)3/

&%. &%. &%. &%.

!/54 !'.$ 6$$ '.$

2%3%4

4%34

30) 3QUIBU$EPLOYMENT$IAGNOSTICS

		$EPLOYMENT
		$RIVER
	0IN
		$IAGNOSTICS

62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$

)2%&

'!0'03

1.2Pin description

Table 2.	Pin description
Pin #		Pin name	Description	I/O type	Reset state
1		MISO	SPI data out	Output	Hi-Z
2		NC	No connect	-	-
3		FEN1	Fire enable for channels 0 and 1	Input	Pulldown
4		FEN2	Fire enable for channels 2 and 3	Input	Pulldown
5		RESETB	Reset pin	Input	Pullup
6		GND	Ground (analog & digital)	-	-
7		VDD	VDD supply voltage	Input	-

Doc ID 022048 Rev 1

5/51

Block diagram and pin description					L9659
Table 2.	Pin description (continued)
Pin #		Pin name	Description	I/O type	Reset state
8		FEN3	Fire enable for channels 4 and 5	Input	Pulldown
9		FEN4	Fire enable for channels 6 and 7	Input	Pulldown
10		NC	No connect	-	-
11		NC	No connect	-	-
12		CS_D	SPI chip select for deployment driver	Input	Pullup
13		MOSI	SPI data in	Input	Hi-Z
14		NC	No connect	-	-
15		NC	No connect	-	-
16		SCLK	SPI clock	Input	Hi-Z
17		GND4	Power ground for loop channel 4	-	-
18		SQL4	Low side driver output for channel 4	Output	Pulldown
19		SQH4	High side driver output for channel 4	Output	Hi-Z
20		VRES4	Reserve voltage for loop channel 4	Input	-
21		VRES5	Reserve voltage for loop channel 5	Input	-
22		SQH5	High side driver output for channel 5	Output	Hi-Z
23		SQL5	Low side driver output for channel 5	Output	Pulldown
24		GND5	Power ground for loop channel 5	-	-
25		GND6	Power ground for loop channel 6	-	-
26		SQL6	Low side driver output for channel 6	Output	Pulldown
27		SQH6	High side driver output for channel 6	Output	Hi-Z
28		VRES6	Reserve voltage for loop channel 6	Input	-
29		VRES7	Reserve voltage for loop channel 7	Input	-
30		SQH7	High side driver output for channel 7	Output	Hi-Z
31		SQL7	Low side driver output for channel 7	Output	Pulldown
32		GND7	Power ground for loop channel 7	-	-
33		TEST	Test pin	Input	Pulldown
34		VSDIAG	Supply for deployment driver diagnostics	Input	-
35		NC	No connect	-	-
36		Reserved	Factory testmode output	-	-
37		Reserved	Factory testmode output	-	-
38		NC	No connect	-	-
39		NC	No connect	-	-
40		NC	No connect	-	-
41		NC	No connect	-	-
42		NC	No connect	-	-

6/51	Doc ID 022048 Rev 1

L9659				Block diagram and pin description
Table 2.	Pin description (continued)
Pin #		Pin name	Description		I/O type	Reset state
43		NC	No connect		-	-
44		NC	No connect		-	-
45		NC	No connect		-	-
46		IREF	External current reference resistor		Output	-
47		AGND	Ground reference for AOUT		-	-
48		AOUT	Analog output for loop diagnostics		Output	Hi-Z
49		GND3	Power ground for loop channel 3		-	-
50		SQL3	Low side driver output for channel 3		Output	Pulldown
51		SQH3	High side driver output for channel 3		Output	Hi-Z
52		VRES3	Reserve voltage for loop channel 3		Input	-
53		VRES2	Reserve voltage for loop channel 2		Input	-
54		SQH2	High side driver output for channel 2		Output	Hi-Z
55		SQL2	Low side driver output for channel 2		Output	Pulldown
56		GND2	Power ground for loop channel 2		-	-
57		GND1	Power ground for loop channel 1		-	-
58		SQL1	Low side driver output for channel 1		Output	Pulldown
59		SQH1	High side driver output for channel 1		Output	Hi-Z
60		VRES1	Reserve voltage for loop channel 1		Input	-
61		VRES0	Reserve voltage for loop channel 0		Input	-
62		SQH0	High side driver output for channel 0		Output	Hi-Z
63		SQL0	Low side driver output for channel 0		Output	Pulldown
64		GND0	Power ground for loop channel 0		-	-

Doc ID 022048 Rev 1

7/51

Block diagram and pin description	L9659

1.3Application schematic

Figure 2. Application schematic

				62%3
		#3?$		62%3	#VRES ?
				62%3
		3#,+
			30)	62%3
		-/3)
		-)3/	3QUIBB$EPLOYMENT	62%3
		&%.	$IAGNOSTICS	62%3
				62%3	#VRES ?
		&%.
				62%3
		&%.
		&%.		31(
		63$)!'		31,
		&		'.$
	+7			31(
4O !$#		!/54
				31,
		!'.$
	&			'.$
		6$$		31(
	&	'.$	0IN	31,
			$EPLOYMENT	'.$
				31(
			$RIVERS
		2%3%4	$IAGNOSTICS	31,
		4%34		'.$
				31(
				31,
				'.$
				31(
				31,
				'.$
				31(
				31,
				'.$
				31(
				31,
				'.$
					6$$
					2)2%&
				)2%&
					'!0'03

8/51	Doc ID 022048 Rev 1

L9659	Electrical specifications

2 Electrical specifications

2.1Absolute maximum ratings

The following maximum ratings are continuous absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit.

Table 3.	Absolute maximum ratings
Symbol		Parameter	Value	Unit
(1)		Supply voltage	- 0.3 to 5.5	V
VDD
VSDIAG		Supply voltage for squib diagnostics	- 0.3 to 40	V
VRESx		VRES voltage (VRES0, VRES1, VRES2, VRES3, VRES4,	- 0.3 to 40	V
		VRES5, VRES6, VRES7)
SQHx		Squib high side drivers (SQH0, SQH1, SQH2, SQH3, SQH4,	- 0.6 to 40	V
		SQH5, SQH6, SQH7)
SQLx		Squib low side drivers (SQL0, SQL1, SQL2, SQL3, SQL4,	- 0.3 to 40	V
		SQL5, SQL6, SQL7)
TEST		Test pin	-0.3 to 40	V
VI		Discrete input voltage (RESETB, CS_D, SCLK, MOSI,	- 0.3 to 5.5	V
		FEN1, FEN2, FEN3, FEN4, IREF)
VO		Discrete output voltage (MISO, AOUT)	- 0.3 to 5.5	V
AGND		Analog output reference	-0.3 to 5.5	V
GNDx		Ground (GND0, GND1, GND2, GND3, GND4, GND5,	-0.3 to 5.5	V
		GND6, GND7)
Tj (2)		Maximum steady-state junction temperature	150	°C
Tamb		Ambient temperature	-40 to 95	°C
Tstg		Storage temperature	-65 to 150	°C
Rth j amb		Thermal resistance junction to ambient (on FR-4 board)	46	°C/W

The following maximum ratings are up to 48 hours; exceeding any one of these values for longer than a total time of 48 hours may cause permanent damage to the integrated circuit.

	VDD	Supply voltage	- 0.3 to 6.0	V
	VI	Discrete input voltage (RESETB, CS_D, SCLK, MOSI,	- 0.3 to 6.0	V
		FEN1, FEN2, FEN3, FEN4, IREF)
	VO	Discrete output voltage (MISO, AOUT)	- 0.3 to 6.0	V
	AGND	Analog output reference	-0.3 to 6.0	V
	GNDx	Ground (GND0, GND1, GND2, GND3, GND4, GND5,	-0.3 to 6.0	V
		GND6, GND7)
	Tj (2)	Maximum steady-state junction temperature	150	°C
	Tamb	Ambient temperature	-40 to 95	°C
	Tstg	Storage temperature	-65 to 150	°C
	Rth j amb	Thermal resistance junction to ambient (on FR-4 board)	46	°C/W

1.Exceeding a VDD of 5.1V during a deployment may cause damage

2.To allow for deployment the maximum steady state junction temperature cannot exceed 130°C. Under the operating ratings defined in section 2.3 the steady state junction temperature will not exceed 130°C.

Doc ID 022048 Rev 1

9/51

Electrical specifications	L9659

2.2Absolute maximum degraded operating ratings

Under the following deviations to the ratings indicated in Section 2.3 the L9659 performance will be degraded and not meet the electrical characteristics outlined in Section 2.4. At minimum the SPI and diagnostics will function but not meet specified electrical parameters.

Table 4.		Absolute maximum degraded operating ratings
Symbol		Parameter		Value	Unit
VDD	Supply voltage			4.5 to 5.5	V
VSDIAG	Supply voltage for squib diagnostics			7 to 40	V
VRES	VRES voltage (VRES0, VRES1, VRES2, VRES3, VRES4,			7 to 40	V
	VRES5, VRES6, VRES7)
VI	Discrete input voltage (RESETB, DEPEN, CS_D, SCLK,			- 0.3 to (VDD +0.3)	V
	MOSI, FEN1, FEN2, FEN3, FEN4, IREF)
VO	Discrete output voltage (MISO, AOUT)			-0.3 to (VDD + 0.3)	V
Tj	Junction temperature			-40 to 150	°C

Note:	The above is provided for informational purposes only and will result in degraded operation.
	Under the above conditions the SPI will be functional as well as diagnostics, though the
	electrical performance may not conform to the parameters outlined in Section 2.4. Firing
	requirements as indicated in Section 2.4 may not be met with the conditions above.

2.3Operating ratings

Table 5.	Operating ratings
Symbol		Parameter	Value	Unit
VDD		Supply voltage	4.9 to 5.1	V
VSDIAG		Supply voltage for squib diagnostics	7 to 37	V
VRESx		VRES voltage (VRES0, VRES1, VRES2, VRES3, VRES4,	7 to 37	V
		VRES5, VRES6, VRES7)
VI		Discrete input voltage (RESETB, CS_D, SCLK, MOSI,	- 0.3 to (VDD +0.3)	V
		FEN1, FEN2, FEN3, FEN4, IREF)
VO		Discrete output voltage (MISO, AOUT)	-0.3 to (VDD + 0.3)	V
Tamb		Ambient temperature	-40 to 95	°C
RTh j-amb		Thermal resistance junction to ambient (on FR-4 board)	46	°C/W

Comments:

VSDIAG supply will provide power for squib resistance and HSS diagnostics

VDD will be used for all internal functions as well as short to battery/ground and high squib resistance diagnostics.

10/51

Doc ID 022048 Rev 1

L9659	Electrical specifications

2.4Electrical characteristics

2.4.1General

4.9 V ≤ VDD ≤ 5.1 V; 7 V ≤ VRESX ≤ 37 V; 7 V ≤ VSDIAG ≤ 37 V; FEN1 = FEN2 = FEN3 = FEN4 = VDD; R_REF = 10 kΩ, ±1 %, 100 PPM; -40 °C ≤ TA ≤ +95 °C; unless other specified.

	Table 6.	General - DC electrical characteristics
	Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
	Osc	Internal oscillator	Tested with 10K , 1%, 100ppm Iref	4.75	-	5.25	MHz
		frequency	resistor
		Internal voltage reset VDD	VDD level for L9659 to report reset
	VRST1	after de-glitch time (tpor)	condition -deployment drivers are	4.0	-	4.5	V
		See Figure 7	disabled
	VRST2	Internal voltage reset VDD	Guaranteed by design	2.1	-	3.0
		with no de-glitch time See
	tPOR	POR De-glitch timer	Timer for VRST1	5	-	25	µs
			No squib diagnostics. No deployment.	-	-	15
			Resistance measurement diagnostics	-	-	17
	IDD	Input current VDD	with no fault condition present.				mA
			Short to –0.3V on SQL; VRCM active	-	-	35
			During deployment	-	-	15
	RIREF_H	Resistance threshold IREF	-	-	-	60.0	kΩ
	RIREF_L		-	2.0	-	-	kΩ
	VIH_RESETB	Input voltage threshold	-	-	-	2.0	V
	VIL_RESETB		-	0.8	-	-	V
		RESETB
	VHYS_RST		-	100	-	300	mV
	VIH_TEST	Input voltage threshold	Guaranteed by design	-	3.2	-	V
		TEST
	ITESTPD	Input pull-down current TEST		1.0	-	2.5	mA
	IAOUT_SHRT	AOUT pin current limit	AOUT short to ground during squib	-	-	20	mA
			resistance diagnostics
	IRESETPU	Input pull-up current	RESETB = VIH to GND	-10	-	-50	µA
		RESETB
	IRESx	Quiescent current for	Current per pin during HSS test	-	-	10	µA
		VRESx during HSS test	excluding selected channel
	VIH	Input voltage threshold	Input Logic = 1	-	-	2.0	V
	VIL	(MOSI, SCLK, CS_D)	Input Logic = 0	0.8	-	-	V
	VHYST	Input hysteresis		100	-	300	mV
		(MOSI, SCLK, CS_D)
	ILKGD	Input leakage current	VIN = VDD	-	-	1	µA
		MOSI, SCLK	VIN = 0 to VIH	-1	-	-	µA

Doc ID 022048 Rev 1

11/51

	Electrical specifications						L9659
	Table 6.	General - DC electrical characteristics (continued)
	Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
	IPU_CS	Input pull-up current CS_D	VIN = VIH to GND	-10	-	-50	µA
	VOH		IOH = -800µA	VDD–	-	-	V
		Output voltage MISO		0.8
	VOL		IOL = 1.6mA	-	-	0.4	V
	IHI_Z	Tri-state current MISO	MISO = VDD	-	-	1	µA
			MISO = 0V	-1	-	-	µA

2.4.2Electrical characteristics - Squib deployment drivers and diagnostics

4.9 V ≤ VDD ≤ 5. 1V; 7 V ≤ VRESX ≤ 37 V; 7 V ≤ VSDIAG ≤ 37 V; FEN1 = FEN2 = FEN3 = FEN4 = VDD; R_REF = 10 kΩ, ±1%, 100 PPM; -40 °C ≤ TA ≤ +95 °C; C_VRES0_1 ≥ 68nF; C_VRES2_3 ≥ 68nFC_VRES4_5 ≥ 68nF; C_VRES6_7 ≥ 68nF; unless other specified.

Table 7.	Squib deployment drivers and diagnostics - DC electrical characteristics
Symbol		Parameter	Test condition	Min.	Typ.	Max.	Unit
General
ILKGSQH		Leakage current SQH	VSDIAG = VDD = 0,	-	-	50	µA
			VRES = 37V, VSQH = 0V
			VSDIAG = 18V; VDD = 5V;
ILKGVRES		Bias current VRESX	VRES = 37V; SQH shorted	-	-	10	µA
			to SQL
ILKGSQL		Leakage current SQL	VSDIAG = VDD = 0,	-10	-	10	µA
			VSQL = 18V
IPD		Pulldown current SQL	VSQL = 1.5V to 20V	3.3	-	4.1	mA
VBIAS		Diagnostics Bias voltage	Nominal 3.6V	-5%	VDD*	+5%	V
					0.72
Short to battery/ground diagnostics - Rsqb from 0Ω to Open
ISVRCM		Maximum diagnostics bias	Short to battery or ground	5	-	20	mA
		current limit	test active VSQH = 0V
			Vbatt = 6.5V	1.92	-	3.42	KΩ
		Short to battery resistance
RSTB			Vbatt = 16V	8.61	-	13.98	KΩ
		threshold
			Vbatt = 20V	11.42	-	18.42	KΩ
ISTB		Short to battery current	-	0.9	-	1.42	mA
		threshold
RSTG		Short to ground threshold	-	1.07	-	2.1	KΩ
ISTG		Short to ground current	-	1.8	-	3.2	mA
		threshold

12/51

Doc ID 022048 Rev 1

	L9659					Electrical specifications
	Table 7.	Squib deployment drivers and diagnostics - DC electrical characteristics (continued)
	Symbol		Parameter	Test condition	Min.	Typ.	Max.	Unit
				From/CS ↑ until Test Results
				are Valid,
	tDIAGTIMEOUT		Diagnostic delay time	Output voltage change 0V to	-	-	300	µs
				VDD * 0.72
				CSQHx= 0.12µF
				CSQLx= 0.12µF
	High side safing diagnostics
			Diagnostic current into
	ISRC_HSS		selected VRESx pin during	Normal conditions	710	-	950	µA
			test
	IHSS_8		Current during diagnostic	All 8 VRESx pins tied	710	-	1020	µA
				together
			Normal resistance range	All 8 VRESx pins tied				KΩ
	RHSSNORM_th		when running high side		1.4	-	2.5
				together
			safing diagnostics
			Normal voltage range
	VHSSNORM_r		between VSDIAG and	All 8 VRESx pins tied	1.0	-	2.5	V
	ange		VRESx pin) when running	together
			high side safing diagnostics
			Short voltage threshold	All 8 VRESx pins tied
	VHSSSHORT_th		between VSDIAG and		0.5	-	1.0	V
				together
			VRESx pin)
			Open voltage threshold	All 8 VRESx pins tied
	VHSSOPEN_th		between VSDIAG and		2.5	-	4.0	V
				together
			VRESx pin)
				From/CS ↑ until test results
	tDIAGTIMEOUT		Diagnostic delay time	are valid,	-	-	500	µs
				CSQHx= 0.12µF
				CSQLx= 0.12µF
	Voltage measurement diagnostics (VRESx)
	IRESx		Max diagnostic current into	Normal Conditions	-	-	50	µA
			VRESx pin
	VVRESXLO_th		Low voltage threshold for	-	5.0	-	7	V
			VRESx pin
	VVRESXHI_th		High voltage threshold for	-	13.7	-	18.0	V
			VRESx pin
	tDIAGTIMEOUT		Diagnostic delay time	From/CS ↑ until test results	-	-	100	µs
				are valid.

Doc ID 022048 Rev 1

13/51

Electrical specifications	L9659

Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

MOS diagnostics

I_MOS

MOS test max current

Normal conditions

-

-

ISVRCM

mA

LS/HS MOS turn off under

Time is measured from the

tSHUTOFF

valid LS/ HS MOS current >

-

-

4

µs

fault condition

100mA to the LS/HS turn off

tFETtimeout

FET timeout

Normal Conditions

-

-

100

µs

High squib resistance diagnostics

RSQHIZ

High load resistance

-

1.07

-

2.1

kΩ

threshold

IHR

High resistance current

-

ISTG

mA

threshold

From/CS ↑ until test results

tDIAGTIMEOUT

MOS diagnostic delay time

are valid, CSQHx= 0.12µF

-

-

300

µs

CSQLx= 0.12µF

Squib resistance diagnostics

VOH

High saturation voltage;

VDD-

-

-

V

IAOUT = -500µA

0.2

Output voltage AOUT

VOL

Low Saturation Voltage;

-

-

0.2

V

IAOUT = +500µA

IZ

Tri-State Current AOUT

AOUT = VDD

-

-

1

µA

AOUT = 0V

-1

-

µA

RSQB RANGE

Load resistance range

-

0

-

10.0

Ω

Resistance measurement

0Ω ≤ RSQB < 3.5Ω

VAOUT-

-

VAOUT+

V

analog output tolerance

0.095V

0.095V

VAOUT

VAOUT =

R

VAOUT·

VAOUT·

VDD

1

0.08

SQB

3.5Ω ≤ RSQB ≤ 10Ω

-

V

----------- +

---------------

0.95V

1.05V

9.75

Ω

ISRC

Resistance measurement

VDD = 5.0V; VSDIAG = 7.0V

38

-

42

mA

current source

to 37V

ISINK

Resistance measurement

IPD OFF, VSQLx = 4 V

45

-

57

mA

current sink

ISLEW

Rmeas current di/dt

30% - 70% of ISRC

2

-

11

mA/µs

Vcmpr

Voltage threshold on squib

-

2.65

-

3.25

V

pin to shutdown ISRC

tisrcshtdwn

Shutdown time

Guaranteed by design

-

-

30

µs

VLSDrsqb

LSD (V_SQL) voltage during

-

0.8

-

2.2

V

resistance measure

14/51

Doc ID 022048 Rev 1

L9659					Electrical specifications
Table 7.	Squib deployment drivers and diagnostics - DC electrical characteristics (continued)
Symbol		Parameter	Test condition	Min.	Typ.	Max.	Unit
			Wait time before AOUT
tR_WAIT		Rmeas wait time	voltage is stable for ADC	-	-	300	µs
			reading R AOUT= 5.1kΩ;
			CAOUT=10nF
FENx input pins
tFENfilter		Minimum pulse width	-	12	-	16	µs
IFENPD		Internal pull-down current	VIN = VIL to VDD	20	-	50	µA
VFENLO		Input low voltage threshold	-	0.8	-	-	V
VFENHI		Input high voltage threshold	-	-	-	2.0	V
TFENLATCH		FEN Latch timer	-	0	-	512	ms
tFLACC		FEN latch timer	-	- 20%	-	20	%
		accuracy
Deployment drivers
TRESOLUTION		Diagnostic timing / resolution	IHS ≥ IMEAS,	22.5	25	27.5	µs
			0s ≤ TMEASURE_TIME ≤ 3.7ms
		Diagnostic time
T			CSQUIB _HI = 0.12µF	-	-	2	LSB
ACCURACY		acurracy	CSQUIB _LO = 0.12µF
IMEAS		High side driver current limit	Guaranteed by design	IHSX x	-	IHSX x	A
		detect threshold		0.90		0.99
		Total high and low side MOS	High side MOS +				Ω
R			low side MOS D9:D8=”11”;	-	-	2.0
DSonTOTAL		on resistance	VRES = 7V; I = 1.6A @95°C
RDSonHS		High side MOS on resistance	D9:D8=”11”; VRES = 7V;	-	0.3	0.8	Ω
			Tamb = 95°C; IVRES =
RDSonLS		Low side MOS on resistance		-	0.6	1.2	Ω
			1.6A;
			Configuration mode 1 bits
IHS_12A			D9:D8=”00” SQHx shorted	1.21	-	1.47	A
			to ground;
			VRES = 7 to 37V
			Configuration Mode 1 bits
IHS_15A		High side deployment current	D9:D8=”01” SQHx shorted	1.51	-	1.85	A
		limit	to ground;
			VRES = 7 to 25V
			Configuration Mode 1 bits
IHS_175A			D9:D8=”11” SQHx shorted	1.76	-	2.14	A
			to ground;
			VRES = 7 to 37V
tILIM		Low side MOS shutdown	Vsqblo=18V	90	-	110	µs
		under short to battery
ILS		Low side MOS current limit		2.2	-	4.0	A

Doc ID 022048 Rev 1

15/51

Electrical specifications									L9659
Table 7.	Squib deployment drivers and diagnostics - DC electrical characteristics (continued)
Symbol		Parameter		Test condition		Min.	Typ.	Max.	Unit
			Time from fire command
			CS_D rising edge to where
tsettle		Firing current settling time	firing current remains within			-	-	150	µs
			specified limits
			CSQUIB _HI = 0 to 0.12µF
			CSQUIB _LO = 0 to 0.12µF
			VRES = 7Vto 37@ IHS_12A
tDEPLOY-2ms			VRES = 7Vto 25@ IHS_15A			2.15	-	2.5	ms
			For I	HS_12A	and I
					HS_15A
			Firing current measured
			from CS_D rising edge
		Deployment time	VRES = 7Vto 37V
tDEPLOY-1ms			For IHS_175A Firing current			1.15	-	1.40	ms
			measured from CS_D rising
			edge
			VRES = 7Vto 37V
tDEPLOY-0.65ms			For IHS_175A Firing current			0.65	-	0.85	ms
			measured from CS_D rising
			edge

Figure 3. MOS settling time and turn-on time 2

)0%!+

)(3?XX! -AXIMUM

)(3?XX! -INIMUM

TSETTLE

#3?$ 2ISING2%DGE

'!0'03

16/51

Doc ID 022048 Rev 1