ST L9352B User Manual
Intelligent quad (2 x 5A / 2 x 2.5A) low-side switch
Features
■ Quad low-side switch
■ 2 x 5 A designed as conventional switch
■ 2 x 2.5 A designed as switched current-
regulator
■ Low ON-resistance 4 x 0.2 Ω (typ.)
■ PowerSO-36 - package with integrated cooling
area
■ Integrated free-wheeling and clamping Z-
diodes
■ Output slope control
■ Short circuit protection
■ Selective overtemperature shutdown
■ Open load detection
■ Ground and supply loss detection
■ External clock control
■ Recirculation control
■ Regulator drift detection
■ Regulator error control
■ Status monitoring
Table 1. Device summary
Order code Package
L9352B
PowerSO-36
■ status push-pull stages
■ Electrostatic discharge (ESD) protection
Description
The L9352B is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are
current regulators with current range from 0 mA to
2.25 A.
All channels are protected against fail functions.
They are monitored by a status output.
(1)
Packing
L9352B-LF PowerSO-36 Tray
L9352B-TR-LF PowerSO-36 Tape and reel
1. ECOPACK® package (see Section 6: Package information).
September 2008 Rev 6 1/27
www.st.com
1
Contents L9352B
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Input circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Output stages (not regulated) channel 1 and 2 . . . . . . . . . . . . . . . . . . . . 13
4.4 Current-regulator-stages channel 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Protective circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 Drift detection (regulated channels only) . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Other test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Non regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Regulated channels (timing diagrams of diagnostic with 2kHz
PWM input signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
L9352B List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Special test mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
List of figures L9352B
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Input PWM to output current range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Current accuracy according to the input and clock frequency ratio . . . . . . . . . . . . . . . . . . 14
Figure 5. Output slope, resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Overload switch-off delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Normal condition, resistive load, pulsed input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Diagnostic status output at different open load current conditions . . . . . . . . . . . . . . . . . . . 21
Figure 10. Pulsed open load conditions (regulated and non-regulated channels). . . . . . . . . . . . . . . . 22
Figure 11. Normal condition, inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Recirculation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Current regulation error (e.g. as a result of voltage reduction) . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Test mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. PowerSO-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4/27
L9352B Block diagram
1 Block diagram
Figure 1. Block diagram
VS VCC VDD
Internal Supply
EN
CLK
IN1
ST1
IN4
ST4
IN2
Overtemperature
Channel 4
Overtemperature
Channel 3
LOGIC
LOGIC
&
DA
LOGIC
Overtemperature
Channel 1
Open Load
Overload
GND-det.
Open Load
Overload
GND-det.
Overtemperature
Channel 2
Open Load
Overload
Q1
IPD
D4
Q4
IPD
Q2
ST2
IN3
ST3
TEST
99AT0059
GND-det.
Open Load
Overload
GND-det.
GND
drift-det.
LOGIC
&
DA
5/27
IPD
D3
Q3
IPD
Pins description L9352B
2 Pins description
Figure 2. Pins connection (top view)
CLK
GND 1
PGND3
PGND3
Q3
Q3
Q1
Q1
Q2
Q2
D4
D4
Q4
Q4
PGND4
PGND4
N.C.
D3
D3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
ST3
IN1
IN3
ST1
PGND1
PGND1
VS
PGND2
PGND2
TEST
EN
ST2
IN4
IN2
ST4
VDD
VCC
99AT0060
Table 2. Pins description
N° Pin Description
1 GND Logic ground
2, 3 PGND3 Power ground - Channel 3
4, 5 Q3 Power output - Channel 3
6, 7 D3 Free-wheeling diode - Channel 3
8, 9 Q1 Power output - Channel 1
10, 11 Q2 Power output - Channel 2
12, 13 D4 Free-wheeling diode - Channel 4
14, 15 Q4 Power output - Channel 4
16, 17 PGND4 Power ground - Channel 4
18 NC Not Connected
19 VCC 5 V supply
20 VDD 5 V supply
21 ST4 Status output - Channel 4
22 IN2 Control input - Channel 2
23 IN4 Control input - Channel 4
24 ST2 Status output - Channel 2
25 EN Enable input for all four channels
6/27
L9352B Pins description
Table 2. Pins description (continued)
N° Pin Description
26 TEST Enable input for drift detection
27, 28 PGND2 Power ground - Channel 2
29 VS Supply voltage
30, 31 PGND1 Power ground - Channel 1
32 ST1 Status output - Channel 1
33 IN3 Control input - Channel 3
34 IN1 Control input - Channel 1
35 ST3 Status output - Channel 3
36 CLK Clock input
7/27
Electrical specifications L9352B
3 Electrical specifications
3.1 Absolute maximum ratings
The absolute maximum ratings are the limiting values for this device.
Warning: Damage may occur if this device is subjected to conditions
which are beyond these values.
Table 3. Absolute maximum ratings
Symbol Parameter Test conditions Min Typ Max Unit
E
Q
Switch off energy for inductive loads 50 mJ
Volt ag es
V
CC
V
V
V
S
, V
V
Q
V
Q
, V
IN
V
CLK
V
ST
V
D
DRmax
Supply voltage -0.3 40 V
Supply voltage -0.3 6 V
DD
Output voltage static 40 V
Output voltage during clamping t < 1ms 60 V
Input voltage IN1 to IN4, EN II < |10|mA -1.5 6 V
EN
Input voltage CLK -1.5 6 V
Output voltage status -0.3 6 V
Recirculation circuits D3, D4 40 V
Max. reverse breakdown voltage of free
wheeling diodes D3, D4
55 V
Currents
I
Q1/2
I
Q3/4
I
Q1/2
I
PGND1/2
I
Q3/4
I
PGND3/4
I
ST
Output current for Q1 and Q2 >5
Output current for Q3 and Q4 >3
,
Output current at reversal supply for Q1
and Q2
,
Output current at reversal supply for
Q3 and Q4
-4 A
-2 A
Output current status pin -5 5 mA
internal
limited
internal
limited
ESD protection
A
A
Electrostatical discharging
ESD
GND, PGND, Qx, Dx, CLK, ST, IN,
MIL883C ±2 kV
TEST, EN
8/27
L9352B Electrical specifications
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Test conditions Min Typ Max Unit
VS,
VCC,VDD
ESD Output pins (Qx, Dx)
Supply pins vs. GND and PGND ±1 kV
vs. Common GND
(PGND1-4 + GND)
±4 kV
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Test conditions Min Typ Max Unit
T
T
T
stg
T
T
R
th j-case
1. This parameter will not be tested but assured by design.
Junction temperature T
j
jc
Junction temperature during clamping
(life time)
Storage temperature T
th
hy
Over temperature shutdown threshold
Over temperature shutdown hysteresis
j
Σt = 30min
Σt = 15min
stg
(1)
(1)
-40 150 °C
175
190
-55 150 °C
175 200 °C
10 °C
Thermal resistance junction to case 2 K/W
3.3 Operating range
°C
Table 5. Operating range
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
, V
V
CC
dV
S
V
V
V
ST
I
ST
T
T
Supply voltage 4.8 18 V
S
Supply voltage 4.5 5.5 V
DD
/dt Supply voltage transient time -1 1 V/μs
Output voltage static -0.3 40 V
Q
Output voltage induced by inductive
Q
switching
Voltage will be
limited by internal
Z-diode clamping
60 V
Output voltage status -0.3 6 V
Output current status -1 1 mA
Junction temperature -40 150 °C
j
Junction temperature during clamping
jc
Σ = 30min
Σ = 15min
175
190
°C
9/27
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