ST L9352B User Manual

L9352B

Intelligent quad (2 x 5A / 2 x 2.5A) low-side switch

Features

■Quad low-side switch

■2 x 5 A designed as conventional switch

■2 x 2.5 A designed as switched currentregulator

■Low ON-resistance 4 x 0.2 Ω (typ.)

■PowerSO-36 - package with integrated cooling area

■Integrated free-wheeling and clamping Z- diodes

■Output slope control

■Short circuit protection

■Selective overtemperature shutdown

■Open load detection

■Ground and supply loss detection

■External clock control

■Recirculation control

■Regulator drift detection

■Regulator error control

■Status monitoring

PowerSO-36

■status push-pull stages

■Electrostatic discharge (ESD) protection

Description

The L9352B is an integrated quad low-side power switch to drive inductive loads like valves used in ABS systems. Two of the four channels are current regulators with current range from 0 mA to 2.25 A.

All channels are protected against fail functions. They are monitored by a status output.

Table 1.	Device summary
	Order code	Package(1)	Packing
	L9352B-LF	PowerSO-36	Tray
	L9352B-TR-LF	PowerSO-36	Tape and reel

1. ECOPACK® package (see Section 6: Package information).

September 2008

Rev 6

1/27

www.st.com

Contents	L9352B

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
3	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	3.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	3.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	3.3	Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	3.4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
4	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	4.1	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.2	Input circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.3	Output stages (not regulated) channel 1 and 2 . . . . . . . . . . . . . . . . . . . .	13
	4.4	Current-regulator-stages channel 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.5	Protective circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	4.6	Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	4.7	Drift detection (regulated channels only) . . . . . . . . . . . . . . . . . . . . . . . . .	17
	4.8	Other test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	4.9	Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
5	Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	5.1	Non regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	5.2	Regulated channels (timing diagrams of diagnostic with 2kHz
		PWM input signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
6	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
7	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26

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L9352B	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. Special test mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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List of figures	L9352B

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Input PWM to output current range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. Current accuracy according to the input and clock frequency ratio . . . . . . . . . . . . . . . . . . 14 Figure 5. Output slope, resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. Overload switch-off delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Normal condition, resistive load, pulsed input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Diagnostic status output at different open load current conditions . . . . . . . . . . . . . . . . . . . 21 Figure 10. Pulsed open load conditions (regulated and non-regulated channels) . . . . . . . . . . . . . . . . 22 Figure 11. Normal condition, inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13. Recirculation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14. Current regulation error (e.g. as a result of voltage reduction) . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15. Over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 16. Test mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17. PowerSO-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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L9352B	Block diagram

1 Block diagram

Figure 1. Block diagram

VS	VCC	VDD
	Internal Supply
EN
Overtemperature		Overtemperature
Channel 4		Channel 1
CLK
		Open Load
IN1		Overload
	LOGIC		Q1
ST1			IPD
		GND-det.
		Open Load
			D4
IN4	LOGIC	Overload	Q4
	&
	DA
ST4		GND-det.	IPD
Overtemperature		Overtemperature
Channel 3		Channel 2
		Open Load
IN2		Overload
	LOGIC		Q2
ST2			IPD
		GND-det.
		Open Load
			D3
IN3	LOGIC	Overload
			Q3
	&
	DA
ST3			IPD
		GND-det.
drift-det.
TEST
99AT0059			GND
			5/27

Pins description	L9352B

2 Pins description

Figure 2. Pins connection (top view)

											CLK
GND	1					36
PGND3	2			35							ST3
PGND3	3			34							IN1
Q3	4			33							IN3
Q3	5			32							ST1
D3	6			31							PGND1
D3	7			30							PGND1
Q1	8			29							VS
Q1	9			28							PGND2
Q2	10			27							PGND2
Q2	11			26							TEST
D4	12			25							EN
D4	13			24							ST2
Q4	14			23							IN4
Q4	15			22							IN2
PGND4	16			21							ST4
PGND4	17			20							VDD
N.C.	18			19							VCC
				99AT0060

Table 2.		Pins description
N°			Pin	Description
1			GND	Logic ground
2,	3		PGND3	Power ground - Channel 3
4,	5		Q3	Power output - Channel 3
6,	7		D3	Free-wheeling diode - Channel 3
8,	9		Q1	Power output - Channel 1
10,	11		Q2	Power output - Channel 2
12, 13			D4	Free-wheeling diode - Channel 4
14,	15		Q4	Power output - Channel 4
16, 17			PGND4	Power ground - Channel 4
18			NC	Not Connected
19			VCC	5 V supply
20			VDD	5 V supply
21			ST4	Status output - Channel 4
22			IN2	Control input - Channel 2
23			IN4	Control input - Channel 4
24			ST2	Status output - Channel 2
25			EN	Enable input for all four channels

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L9352B				Pins description
	Table 2.	Pins description (continued)
	N°		Pin	Description
	26		TEST	Enable input for drift detection
	27, 28		PGND2	Power ground - Channel 2
	29		VS	Supply voltage
	30, 31		PGND1	Power ground - Channel 1
	32		ST1	Status output - Channel 1
	33		IN3	Control input - Channel 3
	34		IN1	Control input - Channel 1
	35		ST3	Status output - Channel 3
	36		CLK	Clock input

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Electrical specifications	L9352B

3 Electrical specifications

3.1Absolute maximum ratings

The absolute maximum ratings are the limiting values for this device.

Warning: Damage may occur if this device is subjected to conditions

	which are beyond these values.
Table 3.	Absolute maximum ratings
Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
EQ	Switch off energy for inductive loads				50	mJ
Voltages
VS	Supply voltage		-0.3		40	V
VCC, VDD	Supply voltage		-0.3		6	V
VQ	Output voltage static				40	V
VQ	Output voltage during clamping	t < 1ms			60	V
VIN, VEN	Input voltage IN1 to IN4, EN	II < |10|mA	-1.5		6	V
VCLK	Input voltage CLK		-1.5		6	V
VST	Output voltage status		-0.3		6	V
VD	Recirculation circuits D3, D4				40	V
VDRmax	Max. reverse breakdown voltage of free				55	V
	wheeling diodes D3, D4
Currents
IQ1/2	Output current for Q1 and Q2		>5		internal	A
					limited
IQ3/4	Output current for Q3 and Q4		>3		internal	A
					limited
IQ1/2,	Output current at reversal supply for Q1		-4			A
IPGND1/2	and Q2
IQ3/4,	Output current at reversal supply for		-2			A
IPGND3/4	Q3 and Q4
IST	Output current status pin		-5		5	mA
ESD protection
	Electrostatical discharging
ESD	GND, PGND, Qx, Dx, CLK, ST, IN,	MIL883C	±2			kV
	TEST, EN

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L9352B				Electrical specifications
Table 3.	Absolute maximum ratings (continued)
Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
VS,	Supply pins	vs. GND and PGND	±1			kV
VCC,VDD
ESD	Output pins (Qx, Dx)	vs. Common GND	±4			kV
		(PGND1-4 + GND)

3.2Thermal data

Table 4.	Thermal data
Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
Tj	Junction temperature	Tj	-40		150	°C
Tjc	Junction temperature during clamping	Σt = 30min			175	°C
	(life time)	Σt = 15min			190
Tstg	Storage temperature	Tstg	-55		150	°C
Tth	Over temperature shutdown threshold	(1)	175		200	°C
Thy	Over temperature shutdown hysteresis	(1)		10		°C
Rth j-case	Thermal resistance junction to case				2	K/W

1. This parameter will not be tested but assured by design.

3.3Operating range

Table 5.	Operating range
Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
VS	Supply voltage		4.8		18	V
VCC, VDD	Supply voltage		4.5		5.5	V
dVS/dt	Supply voltage transient time		-1		1	V/μs
VQ	Output voltage static		-0.3		40	V
	Output voltage induced by inductive	Voltage will be
VQ		limited by internal			60	V
	switching
		Z-diode clamping
VST	Output voltage status		-0.3		6	V
IST	Output current status		-1		1	mA
Tj	Junction temperature		-40		150	°C
Tjc	Junction temperature during clamping	Σ = 30min			175	°C
		Σ = 15min			190

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