Intelligent quad (2 x 5A / 2 x 2.5A) low-side switch
Features
■ Quad low-side switch
■ 2 x 5 A designed as conventional switch
■ 2 x 2.5 A designed as switched current-
regulator
■ Low ON-resistance 4 x 0.2 Ω (typ.)
■ PowerSO-36 - package with integrated cooling
area
■ Integrated free-wheeling and clamping Z-
diodes
■ Output slope control
■ Short circuit protection
■ Selective overtemperature shutdown
■ Open load detection
■ Ground and supply loss detection
■ External clock control
■ Recirculation control
■ Regulator drift detection
■ Regulator error control
■ Status monitoring
Table 1. Device summary
Order code Package
L9352B
PowerSO-36
■ status push-pull stages
■ Electrostatic discharge (ESD) protection
Description
The L9352B is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are
current regulators with current range from 0 mA to
2.25 A.
All channels are protected against fail functions.
They are monitored by a status output.
(1)
Packing
L9352B-LF PowerSO-36 Tray
L9352B-TR-LF PowerSO-36 Tape and reel
1. ECOPACK® package (see Section 6: Package information).
September 2008 Rev 6 1/27
www.st.com
1
Contents L9352B
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Input circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Output stages (not regulated) channel 1 and 2 . . . . . . . . . . . . . . . . . . . . 13
4.4 Current-regulator-stages channel 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Protective circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 Drift detection (regulated channels only) . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Other test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Non regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Regulated channels (timing diagrams of diagnostic with 2kHz
PWM input signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
L9352B List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Special test mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
List of figures L9352B
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Input PWM to output current range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Current accuracy according to the input and clock frequency ratio . . . . . . . . . . . . . . . . . . 14
Figure 5. Output slope, resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Overload switch-off delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Normal condition, resistive load, pulsed input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Diagnostic status output at different open load current conditions . . . . . . . . . . . . . . . . . . . 21
Figure 10. Pulsed open load conditions (regulated and non-regulated channels). . . . . . . . . . . . . . . . 22
Figure 11. Normal condition, inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Recirculation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Current regulation error (e.g. as a result of voltage reduction) . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Test mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. PowerSO-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4/27
L9352B Block diagram
1 Block diagram
Figure 1. Block diagram
VS VCC VDD
Internal Supply
EN
CLK
IN1
ST1
IN4
ST4
IN2
Overtemperature
Channel 4
Overtemperature
Channel 3
LOGIC
LOGIC
&
DA
LOGIC
Overtemperature
Channel 1
Open Load
Overload
GND-det.
Open Load
Overload
GND-det.
Overtemperature
Channel 2
Open Load
Overload
Q1
IPD
D4
Q4
IPD
Q2
ST2
IN3
ST3
TEST
99AT0059
GND-det.
Open Load
Overload
GND-det.
GND
drift-det.
LOGIC
&
DA
5/27
IPD
D3
Q3
IPD
Pins description L9352B
2 Pins description
Figure 2. Pins connection (top view)
CLK
GND 1
PGND3
PGND3
Q3
Q3
Q1
Q1
Q2
Q2
D4
D4
Q4
Q4
PGND4
PGND4
N.C.
D3
D3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
ST3
IN1
IN3
ST1
PGND1
PGND1
VS
PGND2
PGND2
TEST
EN
ST2
IN4
IN2
ST4
VDD
VCC
99AT0060
Table 2. Pins description
N° Pin Description
1 GND Logic ground
2, 3 PGND3 Power ground - Channel 3
4, 5 Q3 Power output - Channel 3
6, 7 D3 Free-wheeling diode - Channel 3
8, 9 Q1 Power output - Channel 1
10, 11 Q2 Power output - Channel 2
12, 13 D4 Free-wheeling diode - Channel 4
14, 15 Q4 Power output - Channel 4
16, 17 PGND4 Power ground - Channel 4
18 NC Not Connected
19 VCC 5 V supply
20 VDD 5 V supply
21 ST4 Status output - Channel 4
22 IN2 Control input - Channel 2
23 IN4 Control input - Channel 4
24 ST2 Status output - Channel 2
25 EN Enable input for all four channels
6/27
L9352B Pins description
Table 2. Pins description (continued)
N° Pin Description
26 TEST Enable input for drift detection
27, 28 PGND2 Power ground - Channel 2
29 VS Supply voltage
30, 31 PGND1 Power ground - Channel 1
32 ST1 Status output - Channel 1
33 IN3 Control input - Channel 3
34 IN1 Control input - Channel 1
35 ST3 Status output - Channel 3
36 CLK Clock input
7/27
Electrical specifications L9352B
3 Electrical specifications
3.1 Absolute maximum ratings
The absolute maximum ratings are the limiting values for this device.
Warning: Damage may occur if this device is subjected to conditions
which are beyond these values.
Table 3. Absolute maximum ratings
Symbol Parameter Test conditions Min Typ Max Unit
E
Q
Switch off energy for inductive loads 50 mJ
Volt ag es
V
CC
V
V
V
S
, V
V
Q
V
Q
, V
IN
V
CLK
V
ST
V
D
DRmax
Supply voltage -0.3 40 V
Supply voltage -0.3 6 V
DD
Output voltage static 40 V
Output voltage during clamping t < 1ms 60 V
Input voltage IN1 to IN4, EN II < |10|mA -1.5 6 V
EN
Input voltage CLK -1.5 6 V
Output voltage status -0.3 6 V
Recirculation circuits D3, D4 40 V
Max. reverse breakdown voltage of free
wheeling diodes D3, D4
55 V
Currents
I
Q1/2
I
Q3/4
I
Q1/2
I
PGND1/2
I
Q3/4
I
PGND3/4
I
ST
Output current for Q1 and Q2 >5
Output current for Q3 and Q4 >3
,
Output current at reversal supply for Q1
and Q2
,
Output current at reversal supply for
Q3 and Q4
-4 A
-2 A
Output current status pin -5 5 mA
internal
limited
internal
limited
ESD protection
A
A
Electrostatical discharging
ESD
GND, PGND, Qx, Dx, CLK, ST, IN,
MIL883C ±2 kV
TEST, EN
8/27
L9352B Electrical specifications
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Test conditions Min Typ Max Unit
VS,
VCC,VDD
ESD Output pins (Qx, Dx)
Supply pins vs. GND and PGND ±1 kV
vs. Common GND
(PGND1-4 + GND)
±4 kV
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Test conditions Min Typ Max Unit
T
T
T
stg
T
T
R
th j-case
1. This parameter will not be tested but assured by design.
Junction temperature T
j
jc
Junction temperature during clamping
(life time)
Storage temperature T
th
hy
Over temperature shutdown threshold
Over temperature shutdown hysteresis
j
Σt = 30min
Σt = 15min
stg
(1)
(1)
-40 150 °C
175
190
-55 150 °C
175 200 °C
10 °C
Thermal resistance junction to case 2 K/W
3.3 Operating range
°C
Table 5. Operating range
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
, V
V
CC
dV
S
V
V
V
ST
I
ST
T
T
Supply voltage 4.8 18 V
S
Supply voltage 4.5 5.5 V
DD
/dt Supply voltage transient time -1 1 V/μs
Output voltage static -0.3 40 V
Q
Output voltage induced by inductive
Q
switching
Voltage will be
limited by internal
Z-diode clamping
60 V
Output voltage status -0.3 6 V
Output current status -1 1 mA
Junction temperature -40 150 °C
j
Junction temperature during clamping
jc
Σ = 30min
Σ = 15min
175
190
°C
9/27
Electrical specifications L9352B
3.4 Electrical characteristics
Table 6.
Electrical characteristics
(VS = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol Parameter Test condition Min. Typ. Max. Unit
Power supply
V
≤ 18V
I
SON
I
SOFF
I
cc
I
dd
I
dd
Supply current
Quiescent current
Supply current VCC (analog supply) V
Supply current VDD (digital supply) VDD = 5V f
Supply current VDD (digital supply) VDD = 5V f
General diagnostic functions
V
V
f
CLK,min
DC
CLKe_low
DC
CLKe_high
VS
V
QU
thGND
thPGL
loss
Open load voltage
Signal-GND-loss threshold VCC = 5V 0.1 1 V
Power-GND-loss threshold VCC = 5V 1.5 2.5 3.5 V
Clock frequency error 10 100 kHz
Clock duty cycle error detection low f
Clock duty cycle error detection high f
Supply detection VCC = VDD = 5V 2 4.5 V
Additional diagnostic functions channel 1 and channel 2 (non regulated channels)
S
(outputs ON)
V
≤ 18V
S
(outputs OFF)
= 5V 5 mA
CC
=0Hz 5 μA
CLK
=250kHz 5 mA
CLK
VS ≥ 6.5V
(outputs OFF)
= 250 kHz 33,3 45 %
CLK
= 250 kHz 55 66,6 %
CLK
0.3 0.33 0.36 x V
5mA
5mA
Q
I
QU1,2
I
QO1,2
Open-load current channel 1, 2 VS ≥ 6.5V 50 300 mA
Over-load current channel 1, 2 VS ≥ 6.5V 5 7.5 9 A
Additional diagnostic functions channel 3 and channel 4 (regulated channels)
DC
I
QO3,4
V
PWM
OUT
rerr
Output duty cycle error filtered with 10ms 90 100 %
Overload current
channel 3,4
Recirculation error shutdown
threshold (open D3/D4)
Output PWM ratio during drift
dOUT
comparison
VS ≥ 6.5V 2.5 5 8 A
Iout > 50mA 45 50 60 V
= V
V
V
IN3
TEST
IN4
= H
= PWM
IN
-14.3 +14.3 %
Digital inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
V
IL
V
IH
V
IHy
Input low voltage -0.3 1 V
Input high voltage 2 6 V
Input voltage hysteresis
(1)
20 500 mV
10/27
L9352B Electrical specifications
Table 6.
Electrical characteristics
(V
= 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
S
(continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
I
I
Input pull down current VIN = 5V, VS ≥ 6.5V 8 20 40 μA
Digital outputs (ST1 to ST4)
V
V
R
DIAGL
R
DIAGH
STL
STH
Status output voltage in low state
Status output voltage in high state
R
R
OUT
OUT
+ R
+ R
in low state 0.3 0.64 1.5 kΩ
DSON
in high state 1.5 3.2 7.0 kΩ
DSON
(2))
IST ≤ 40μA00.4V
IST ≥ - 40μA2.53.45V
(2))
I
≥ -120μA23.45V
ST
Power outputs (Q1 to Q4)
R
DSON
V
F_250mA
V
F_2.25A
R
sens
V
I
PD
I
Qlk
Static drain-source ON-resistance IQ = 1A; VS ≥ 9.5V 0.2 0.4 W
Forward voltage of free wheeling path
D3, D4 @250mA
Forward voltage of free wheeling path
D3, D4 @2.25A
Sense resistor = (V
V
F_250mA
Z-diode clamping voltage IQ ≥ 100mA 45 60 V
Z
)/2A
F_2.25A-
= -250mA 0.5 1.5 V
I
D3/4
I
= -2.25A 2.0 4.5 V
D3/4
1W
Output pull down current VEN = H, VIN = L 10 150 μA
Output leakage current VEN = L; VQ = 20V 5 μA
Timing
t
ON
t
OFF
t
IN3/4min
t
OFFREG
t
r
t
f
t
sf
t
lf
t
SCP
t
D
t
RE
t
Dreg
Output ON delay time IQ = 1A 0 5 20 μs
Output OFF delay time channel IQ = 1A 0 10 30 μs
Minimum Input Register ON time
Output OFF delay time regulator 528 μs
Output rise time IQ = 1A
Output fall time IQ = 1A
Short error detection filter time f
Long error detection filter time f
Short circuit switch-OFF delay time
Status delay time
Regulation error status delay time
Output off status delay time
Reg. current accuracy (reg. channels only)
I
Q3/Q4
Maximum current DC = 90% 2 2.25 2.5 A
(3)
= 250kHz DC = 50%
CLK
= 250kHz DC = 50%
CLK
(3)
(3)
(3)
(reg. channels only) 10 ms
(3)
(reg. channels only 528 μs
0.5 1.5 8 μs
0.5 1.5 8 μs
(3)
48μs
(3)
16 32 μs
430μs
896 1024 μs
2 μs
11/27
Electrical specifications L9352B
Table 6.
Electrical characteristics
(V
= 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
S
(continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
25
10
6
6
I
Q3/Q4
ΔI
Q3/Q4
Current Resolution Input Duty Cycle
0.4% - 99% f
= 2KHz@
clk
0.00A ≤ I
0.25A ≤ I
0.40A ≤ I
0.80A ≤ I
Q3/Q4
Q3/Q4
Q3/Q4
Q3/Q4
≤ 0.25A
≤ 0.40A
≤ 0.80A
≤ 2.25A
-8
Min. quant. step 5 mA
Frequencies
CLK frequency crystal-controlled 250 kHz
Input PWM frequency (reg. channels only) 2 kHz
1. This parameter will not be tested but assured by design.
2. Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW".
3. Digital filtered with external clock, only functional test.
mA
%
%
%
12/27
L9352B Functional description
4 Functional description
4.1 Overview
The L9352B is designed to drive inductive loads (relays, electromagnetic valves) in low side
configuration. Integrated active Zener-clamp (for channel1 and 2) or free wheeling diodes
(for channel 3 and 4) allow the recirculation of the inductive loads. All four channels are
monitored with a status output. All wiring to the loads and supply pins of the device are
controlled. The device is self-protected against short circuit at the outputs and over
temperature. For each channel one independent push-pull status output is used for a
parallel diagnostic function.
Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target
output current. The output current is controlled through the output PWM of the power stage.
The regulator limit of 90% is detected and monitored with the status signal. The current is
measured during recirculation phase of the load.
A test mode compares the differences between the two regulators. This “drift” test compares
the output PWM of the regulators. By this feature a drift of the load during lifetime can be
detected.
4.2 Input circuits
The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with
hysteresis. All inputs are connected to pull-down current sources.
4.3 Output stages (not regulated) channel 1 and 2
The two power outputs (5A) consist of DMOS-power transistors with open drain output. The
output stages are protected against short circuit. Via integrated Zener-clamp-diodes the
overvoltage of the inductive loads due to recirculation are clamped to typ. 52V for fast shut
off of the valves. Parallel to the DMOS transistors there are internal pull-down current
sources. They are provided to assure an open load condition in the OFF-state. With EN=low
this current source is switched off, but the open load comparator is still active.
4.4 Current-regulator-stages channel 3 and 4
The current-regulator channels are designed to drive inductive loads. The target value of the
current is given by the duty cycle (DC) of the 2 kHz PWM input signal. The following figure
shows the relation between the input PWM and the output current and the specified
accuracy
.
13/27
Functional description L9352B
A
Figure 3. Input PWM to output current range
2250
IO
(mA)
800
400
250
±
±25
±6% -8% to +6%
10%
mA
10 16 32 90
INPUT PWM(%)
D03AT513
The ON period of the input signal is measured with a 1MHz clock, synchronized with the
external 250kHz clock. For requested precision of the output current the ratio between the
frequencies of the input signal and the external 250kHz clock has to be fixed according to
the graph shown in Figure 4.
Figure 4.
The theoretical error is zero for f
Current accuracy according to the input and clock frequency ratio
current accuracy
5.6%
112.5
/ fIN = 125.
CLK
125
0%
-10%
132
Regulator
switched off
f
/ f
CLK
IN
If the period of the input signal is longer than 132 times the period of the clock the regulator
is switched off. For a clock frequency lower than 100kHz the clock control will also disable
the regulator. For high precision applications the clock frequency and the input frequency
have to be correlated.
The output current is measured during the recirculation of the load. The current sense
resistor is in series to the free wheeling diode. If this recirculation path is interrupted the
regulator stops immediately and the status output remains low for the rest of the input cycle.
The output period is 64 times the clock period. With a clock frequency of 250kHz the output
PWM frequency is 3.9kHz. The output PWM is synchronized with the first negative edge of
the input signal. After that the output and the input are asynchronous. The first period is
14/27
L9352B Functional description
used to measure the current. This means the first turn-on of the power is 256μs after the first
negative edge of the input signal.
As regulator a digital PI-regulator with the Transfer function for:
0.126
-------------- -
KI: and KP: 0.96
z1–
for a sampling time of 256µs is realized.
To speed up the current settling time the regulator output is locked to 90% output PWM until
the target current value is reached. This happens also when the target current value
changes and the output PWM reaches 90% during the regulation. The status output gets
low if the target current value is not reached within the regulation error delay time of
t
=10ms.
RE
4.5 Protective circuits
The outputs are protected against current overload, over temperature, and power-GND-loss.
The external clock is monitored by a clock watchdog. This clock watchdog detects a minimal
frequency f
55%. The current-regulator stages are protected against recirculation errors, when D3 or D4
is not connected. All these error conditions shut off the power stage and invert the status
output information.
and wrong clock duty cycles. The allowed clock duty cycle range is 45% to
CLK,min
4.6 Error detection
The status outputs indicate the switching state under normal conditions (status LOW = OFF;
status HIGH = ON). If an error occurs, the logic level of the status output is inverted, as listed
in the diagnostic table below. All external errors, for example open load, are filtered
internally. The following table shows the detected errors, the filter times and the detection
mode (on/off).
Table 7. Error detection
Short circuit of the load X t
Open load
(under voltage detection)
Open load
(under current detection)
Overtemperature X t
Power-GND-loss X X t
Signal-GND-loss X X t
ON State
EN &IN = HIGH
OFF State
EN &IN = LOW
Filter time Reset done by
Xt
Xt
EN & IN = “LOW”
sf
lf
sf
for T
D
timer T
timer T
or T
EN & IN = “LOW”
sf
for TD or T
in on: EN & IN = “LOW”
for TD or T
lf
in off: timer TD
timer T
lf
Dreg
D
D
Dreg
Dreg
D
15/27
Functional description L9352B
Table 7. Error detection (continued)
ON State
EN &IN = HIGH
Supply-VS-loss X X t
Clock control X X no
X
Output voltage clamp active
(regulated
channels)
OFF State
EN &IN = LOW
Filter time Reset done by
no
EN&IN = low means that at least one between enable and input is low. For the inputs IN=low
means also no input PWM. For the regulator input period longer than T
standard channel input period longer than T
.
D
A detected error is stored in an error register. The reset of this register is made with a timer
T
. With this approach all errors are present at the status output at least for the time TD.
D
All protection functions like short circuit of the output, over temperature, clock failure or
power-GND-loss in ON condition are stored into an internal “fail” register. The output is then
shut off. The register must be reset with a low signal at the input. A “low signal” means that
the input is low for a time longer than T
or T
D
for the related channel, otherwise it is
DReg
interpreted as a PWM input signal and the register is left in set mode.
Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail
register. This type of error is only delayed with the standard timer t
Open load is detected for all four channels in on- and off-state.
timer T
lf
in on: EN & IN = “LOW”
for TD or T
in off: timer TD
in on: EN & IN = “LOW”
or T
for T
D
in off: timer TD
Dreg
function.
lf
D
Dreg
Dreg
and for the
Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33
* VS the error register is set and delayed with T
. A sink current stage pull the output down
D
to ground, with EN high. With EN low the output is floating in case of openload and the
detection is not assured. In the ON state the load current is monitored by the non-regulated
channels. If it drops below the specified threshold value I
the error register is set and delayed with T
. A regulated channel detects the open load in
D
an open load is detected and
QU
the on state with the current regulator error detection. If the output PWM reaches 90% for a
time longer than t
than an error occurs. This could happen when no load is connected, the
RE
resistivity of the load is too high or the supply voltage too low.
A clock failure (clock loss) is detected when the frequency becomes lower than f
CLK,min
. All
status outputs are set on error and all power outputs are shut off. The status signals remain
in their state until the clock signal is present again. A clock failure during power on of V
CC
is
detected only on the regulated channels. The status outputs of the channel 1 and 2 are low
in this case.
16/27
L9352B Functional description
4.7 Drift detection (regulated channels only)
The drift detection is used to compare the two regulated channels during regulation. This
“Drift” test compares the output PWM of the regulators. The resistivity of the load influences
the output PWM. The approximated formula for the output current below shows the
dependency of the load resistor to the output PWM. In this formula the energy reduction
during the recirculation is not taken into account. The real output PWM is higher. The
testmode is enabled with IN, EN and TEST high. With an identical 2kHz PWM-Signal
connected to the IN-inputs the output PWM must be in a range of ±14.3%. If the difference
between the two on-times is more than ±14.3% of the expected value an error is detected
and monitored by the status outputs, in the same way as described above, but a drift error
will not be registered and also not delayed with T
IOUT
--------------------------- -
RL RON+
Drift Definition:
Drift = PWM(1+E) - PWM (1-E) = 2PWM E
Drift * 4 < PWM (1+E)
with E >14.3% a drift is detected
E.. not correlated Error of the channels
%PWM ... Corresponding ideal output PWM to a given input PWM
as other errors.
D
VBAT
PWM⋅=
A 7bit output-PWM-register is used for the comparison. The register with the lower value is
subtracted from the higher one. This result is multiplied by four and compared with the
higher value.
4.8 Other test modes
The test pin is also used to test the regulated channels in the production. With a special
sequence on this pin the power stages of the regulated channels can be controlled direct
from the input. No status feedback of the regulated channels is given. The status output is
clocked by the regulator logic. The output sequence is a indication of a proper logic
functionality. The following table shows the functionality of this special test mode.
Table 8. Special test mode functionality
EN IN TEST OUT STATUS Note
1 X X X X disable test mode
1 1 1 on 1 Drift mode
0 X off test pattern test condition one
0 X off test pattern test condition two
0 X off test pattern test condition three
0 0 off test pattern test condition four
0 1 on test pattern test condition four
For more details about the test condition four see timing diagram.
17/27
Functional description L9352B
4.9 Diagnostic
The status follows the input signal in normal operating conditions.
If any error is detected the status is inverted.
Table 9. Diagnostic
Tes t
Operating condition
input
TEST
L
Normal function
L
L
L
L
Open load or short to ground
L
L
L
Overload or short to supply
Latched overload
Reset latch
Reset latch
Overtemperature
Latched overtemperature
Reset latch
Reset latch
Recirculation error (reg.chn.)
Latched error
Reset latch
Reset latch
L
L
L
L
L
L
L
L
L
L
L
L
L
Clock failure (clock loss)
(1)
L
L
L
Drift
(2)
H
H
Failure
No failure
1. during power on sequence only detected on channel 3 and 4 (see description).
2. This input combination is also used for an internal chip-test and must not be used.
H
H
Enable
input
ENA
L
L
H
H
L
L
H
H
H
H
H –> L
H
H
H
H –> L
H
H
H
H –> L
H
L
L
H
H
L
L
H
H
Control input
non-reg./reg. IN
L
H/PWM
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
X
H/PWM –> L
H/PWM
H/PWM
X
H/PWM –> L
PWM
PWM
X
PWM –> L
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
Power
output/
reg. Q
current
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
Status
output
ST
L
L
L
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
X
X
L
H
18/27
L9352B Timing diagrams
5 Timing diagrams
5.1 Non regulated channels
Figure 5. Output slope, resistive load
V
I
V
IH
V
IL
t
t
OFFtr
85% V
15% V
t
V
Q
V
S
S
S
ONtf
99AT0061
Figure 6. Overload switch-off delay
I
Q
I
QO
I
QU
t
D
V
ST
00RS0001
t
t
SCP
t
sf
t
t
19/27
Timing diagrams L9352B
Figure 7. Normal condition, resistive load, pulsed input signal
V
IN
V
Q
I
Q
t
D
V
ST
99AT0063
Figure 8. Current overload
V
IN
V
Q
I
Q
t
D
Set Fail
register
I
QU
t
D
t
D
Reset Fail
register
I
QO
V
ST
99AT0064
20/27
L9352B Timing diagrams
Figure 9. Diagnostic status output at different open load current conditions
Under current condition followed by normal operation
t
D
V
IN
V
Q
I
Q
t
D
V
ST
99AT0065
Open load condition in the case of pulsed input signal followed by normal operation
V
IN
V
Q
I
Q
t
D
V
ST
I
QU
t
D
I
QU
99AT0066
21/27
Timing diagrams L9352B
Figure 10. Pulsed open load conditions (regulated and non-regulated channels)
V
IN
V
Q
I
Q
V
ST
99AT0067
t
lf
t
D
0.33 x V
S
t
lf
5.2 Regulated channels (timing diagrams of diagnostic with 2kHz PWM input signal)
Figure 11. Normal condition, inductive load
500μs
V
IN
t
DREG
V
Q
I
Q
V
ST
99AT0068
256μs
256μs
22/27
Target Current
L9352B Timing diagrams
Figure 12. Current overload
500μs
V
IN
V
Q
I
QO
I
Q
V
ST
99AT0069
Figure 13. Recirculation error
500μs
t
DREG
Reset Fail
register
Set fail
registor
t
sf
t
DREG
Reset Fail
register
V
IN
V
Q
I
Q
V
ST
99AT0070
Set Fail
register
target current
23/27
Timing diagrams L9352B
Figure 14. Current regulation error (e.g. as a result of voltage reduction)
500μs
V
IN
V
Q
PWM
= 90%
I
Q
V
ST
99AT0071
target current
ratio
t
RE
Figure 15. Over temperature
Overtemperature
Condition
500μs
V
IN
V
Q
target current
I
Q
V
ST
99AT0072
Figure 16. Test mode 4
Test mode 4 VEN low
V
TEST
V
IN3/4
t
Set Fail
register
DREG
Reset Fail
register
V
Q3/4
99AT0073
24/27
L9352B Package information
6 Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK®
packages. ECOPACK
®
packages are lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 17. PowerSO-36 mechanical data and package dimensions
DIM.
A 3.60 0.1417
a1 0.10 0.30 0.0039 0.01 18
a2 3.30 0.1299
a3 0 0.10 0 .0039
b 0.22 0.38 0.0087 0.0150
c 0.23 0.32 0.0091 0.0126
D 15.80 16.00 0.6220 0.62 99
D1 9.40 9.80 0.3701 0.3858
E 13.90 14.5 0.5472 0.5709
E1 10.90 11.10 0.4291 0.43 70
E2 2.90 0.1142
E3 5.80 6.20 0.2283 0.2441
e 0.65 0.0256
e3 11.05 0.4350
G 0 0.10 0.0039
H 15.50 15.90 0.6102 0.62 60
h 1.10 0.0433
L 0.8 1.10 0.0315 0.0433
N 10˚ (max)
s 8˚ (max)
Note: “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions are "a3", "E" and "G".
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
PowerSO-36
0096119 C
25/27
Revision history L9352B
7 Revision history
Table 10. Document revision history
Date Revision Changes
20-Feb-2004 5 Initial release.
05-Sep-2008 6
Document reformatted.
Updated the order codes in Table 1: Device summary.
26/27
L9352B
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