ST L7986TA User Manual

Features

■ 3 A DC output current

■ 4.5 V to 38 V input voltage

■ Output voltage adjustable from 0.6 V

■ 250 kHz switching frequency, programmable

up to 1 MHz

■ Internal soft-start and enable

■ Low dropout operation: 100% duty cycle

■ Voltage feed-forward

■ Zero load current operation

■ Overcurrent and thermal protection

■ HSOP8 package

■ Guarantee overtemperature range (-40 °C to

125 °C)

Applications

■ Automotive:

– Car audio, car infotainment

■ Industrial:

– PLD, PLA, FPGA, chargers

■ Networking: XDSL, modems, DC-DC modules

■ Computer:

– Optical storage, hard disk drive, printers,

■ LED driving

L7986TA

3 A step-down switching regulator

HSOP8 exposed pad

Description

The L7986TA is a step-down switching regulator with 3.7 A (min.) current limited embedded power MOSFET, so it is able to deliver up to 3 A current to the load depending on the application conditions.

The input voltage can range from 4.5 V to 38 V, while the output voltage can be set starting from

0.6 V to V

Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz.

The HSOP package with exposed pad allows reducing the R

down to 40 °C/W.

thJA

March 2012 Doc ID 022098 Rev 2 1/43

www.st.com

Contents L7986TA

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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L7986TA Contents

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Doc ID 022098 Rev 2 3/43

Pin settings L7986TA

1 Pin settings

1.1 Pin connection

Figure 1. Pin connection (top view)

1.2 Pin description

Table 1. Pin description

N. Type Description

1 OUT Regulator output

Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period, with respect to the power turn-on, is present at the pin. When connected to an external signal at a frequency higher

2 SYNCH

3EN

4 COMP Error amplifier output to be used for loop frequency compensation.

5FB

7 GND Ground

than the internal one, the device is synchronized by the external signal, with zero phase shift.

Connecting together the SYNCH pin of two devices, the one with a higher frequency works as master and the other as slave; so the two powers turn-ons have a phase shift of half a period.

A logical signal (active high) enables the device. With EN higher than 1.2 V the device is ON and with EN lower than 0.3 V the device is OFF.

Feedback input. By connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from V

The switching frequency can be increased connecting an external resistor from the FSW pin and ground. If this pin is left floating, the device works at its free-running frequency of 250 kHz.

Unregulated DC input voltage.

to the FB pin.

OUT

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L7986TA Maximum ratings

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

Vcc Input voltage 45

OUT Output DC voltage -0.3 to V

FSW, COMP, SYNCH Analog pin -0.3 to 4

EN Enable pin -0.3 to V

FB Feedback voltage -0.3 to 1.5

TOT

stg

3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

thJA

1. Package mounted on demonstration board.

Maximum thermal resistance junction-ambient

Power dissipation

< 60 °C

at T

HSOP 2 W

Junction temperature range -40 to 150 °C

Storage temperature range -55 to 150 °C

(1)

HSOP8 40 °C/W

Doc ID 022098 Rev 2 5/43

Electrical characteristics L7986TA

4 Electrical characteristics

TJ=-40 °C to 125 °C, VCC=12 V, unless otherwise specified.

Table 4. Electrical characteristics

Val ues

Symbol Parameter Test condition

Min. Typ. Max.

Unit

CCON

CCHYS

DSON

LIM

Operating input voltage range

4.5 38

Tur n - on VCC threshold 4.5

VCC UVLO hysteresis 0.1 0.4

MOSFET on resistance 200 400 mΩ

=25 °C 3.7 4.2 4.7

Maximum limiting current

3.5 4.7

Oscillator

Switching frequency 210 250 275 KHz

FSW pin voltage 1.254 V

FSW

DDuty Cycle 0 100%

ADJ

Adjustable switching frequency

=33 kΩ 1000 KHz

FSW

Dynamic characteristics

Feedback voltage 4.5 V<VCC<38 V 0.582 0.6 0.618 V

DC characteristics

QST-BY

Quiescent current

Total standby quiescent current

Duty Cycle=0, V V

=0.8

2.4 mA

20 30 µA

Enable

Device OFF level 0.3

EN threshold voltage

Device ON level 1.2

EN current EN=V

Soft-start

FSW pin floating 7.4 8.2 9.7

Soft-start duration

F R

FSW

=1 MHz,

=33 kΩ

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7.5 10 µA

L7986TA Electrical characteristics

Table 4. Electrical characteristics (continued)

Val ues

Symbol Parameter Test condition

Min. Typ. Max.

Error amplifier

Unit

O SOURCE

O SINK

High level output voltage VFB<0.6 V 3

Low level output voltage VFB>0.6 V 0.1

Source COMP pin VFB=0.5 V, V

Sink COMP pin VFB=0.7 V, V

Open-loop voltage gain

Synchronization function

S_IN,HI

S_IN,LO

S_IN_PW

SYNCH,LO

S_OUT,HI

S_OUT_PW

High input voltage 2 3.3

Low input voltage 1

Input pulse width

Slave sink current V

Master output amplitude I

Output pulse width SYNCH floating 110 ns

Protection

Thermal shutdown 150

SHDN

Hysteresis 30

(1)

S_IN,HI

S_IN,LO

S_IN,HI

S_IN,LO

SYNCH

SOURCE

=1 V 19 mA

COMP

=1 V 30 mA

COMP

100 dB

=3 V,

=0 V

100

=2 V,

=1 V

300

=2.9 V 0.7 1 mA

=4.5 mA 2 V

°C

1. Guaranteed by design.

Doc ID 022098 Rev 2 7/43

Functional description L7986TA

5 Functional description

The L7986TA is based on a “voltage mode”, constant frequency control. The output voltage

is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing

OUT

an error signal that, compared to a fixed frequency sawtooth, controls the on- and off-time of the power switch.

The main internal blocks are shown in the block diagram in Figure 2. They are:

● A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the

synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feed-forward are implemented.

● The soft-start circuitry to limit inrush current during the startup phase.

● The voltage mode error amplifier.

● The pulse width modulator and the relative logic circuitry necessary to drive the internal

power switch.

● The high-side driver for embedded P-channel power MOSFET switch.

● The peak current limit sensing block, to handle overload and short-circuit conditions.

● A voltage regulator and internal reference. It supplies internal circuitry and provides a

fixed internal reference.

● A voltage monitor circuitry (UVLO) that checks the input and internal voltages.

● A thermal shutdown block, to prevent thermal runaway.

Figure 2. Block diagram

TRIMMING UVLO

TRIMMING UVLOUVLO

COMP

0.6V

SOFT-

START

REGULATOR

BANDGAP

1.254V 3.3V

THERMAL

SHUTDOWN

E/A

OSCILLATOR

FSW

PWM

GND

PEAK

CURRENT

LIMIT

SRQ

SYNCH

PHASE SHIFT

SYNCH

DRIVER

VCC

OUT

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L7986TA Functional description

5.1 Oscillator and synchronization

Figure 3 shows the block diagram of the oscillator circuit. The internal oscillator provides a

constant frequency clock. Its frequency depends on the resistor externally connect to the FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as shown in Figure 5 by an external resistor connected to ground.

To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 4.a).

The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feed-forward is implemented (Figure 4.b) in order to keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM gain expression).

On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pins together. When SYNCH pins are connected, the device with a higher oscillator frequency works as master, so the slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor (see the L5988D datasheet).

Figure 3. Oscillator circuit block diagram

Clock

ClockClock

FSW

The device can be synchronized to work at a higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain (Figure 4.c). This change must be taken into account when the loop stability is studied. To minimize the change of the PWM gain, the free-running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render the truncation of sawtooth negligible, due to the external synchronization.

Clock

Generator

Synchronization

Ramp

Generator

SYNCH

Sawtooth

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Functional description L7986TA

Figure 4. Sawtooth: voltage and frequency feed-forward; external synchronization

Figure 5. Oscillator frequency vs. FSW pin resistor

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L7986TA Functional description

5.2 Soft-start

The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monothonically.

The soft-start is performed by a staircase ramp on the non-inverting input (V

) of the error

REF

amplifier. So the output voltage slew rate is:

Equation 1

VREF

⎛⎞

------- -+

⋅=

⎝⎠

where SR

is the slew rate of the non-inverting input, while R1and R2 is the resistor

VREF

OUT

divider to regulate the output voltage (see Figure 6). The soft-start staircase consists of 64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency.

Figure 6. Soft-start scheme.

Soft-start time results:

Equation 2

32 64⋅

TIME

--------------------=

Fsw

For example, with a switching frequency of 250 kHz the SS

Doc ID 022098 Rev 2 11/43

TIME

is 8 ms.

Functional description L7986TA

5.3 Error amplifier and compensation

The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier, therefore, with high DC gain and low output impedance.

The uncompensated error amplifier characteristics are the following:

Table 5. Uncompensated error amplifier characteristics

Low frequency gain 100 dB

GBWP 4.5 MHz

Slew rate 7 V/µs

Output voltage swing 0 to 3.3 V

Maximum source/sink current 17 mA/25 mA

In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. If the zero introduced by the output capacitor helps to compensate the double pole of the LC filter, a type II compensation network can be used. Otherwise, a type III compensation network must be used (see Chapter 6.4 for details of the compensation network selection).

Anyway, the methodology to compensate the loop is to introduce zeroes to obtain a safe phase margin.

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L7986TA Functional description

5.4 Overcurrent protection

The L7986TA implements overcurrent protection by sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns.

If the overcurrent limit is reached, the power MOSFET is turned off implementing pulse-bypulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power MOSFET is turned off and one pulse is skipped. If, at the following switching on, when the “masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time”, the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit (see Figure 7).

So, the overcurrent/short-circuit protection acts by switching off the power MOSFET and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current around the current limit.

This kind of overcurrent protection is effective if the output current is limited. To prevent the current from diverging, the current ripple in the inductor during the on-time must not be higher than the current ripple during the off-time. That is:

Equation 3

VINV–

----------------------------------------------------------- --------------------------------------------------------------

If the output voltage is shorted, V

OUT

⋅ DCR I

DSONIOUT

⋅

⋅––

OUT

≅ 0, I

OUTVFRDSONIOUT

------------------------------------------------------------- ----------------------------------------------------------

D⋅

OUT=ILIM

, D/FSW=T

⋅ DCR I

⋅

ON_MIN

, (1-D)/FSW≅ 1/FSW. So,

⋅++ +

OUT

1D–()⋅=

from Equation 3, the maximum switching frequency that guarantees to limit the current results:

Equation 4

VFDCR I⋅+

With R

=300 mΩ, DRC=0.08 Ω, the worst condition is with VIN=38 V, I

DSon

()

--------------------------------------------------------------- ----------------------

INRDSON

LIM

DCR+()I

⋅–()

LIM

------------------------ -

⋅=

ON_MIN

=3.7 A; the

LIM

maximum frequency to keep the output current limited during the short-circuit results 88 kHz.

The pulse-by-pulse mechanism, which reduces the switching frequency down to one eighth the maximum F

, adjusted by the FSW pin, that assures a full effective output current

limitation, is 88 kHz*8 = 706 kHz.

If, with V

=38 V, the switching frequency is set higher than 706 kHz, during short-circuit

condition the system finds a different equilibrium with higher current. For example, with F

=800 kHz and the output shorted to ground, the output current is limited around:

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