ST L7985 User Manual
Features
■ 2 A DC output current
■ 4.5 V to 38 V input voltage
■ Output voltage adjustable from 0.6 V
■ 250 KHz switching frequency, programmable
up to 1 MHz
■ Internal soft-start and enable
■ Low dropout operation: 100% duty cycle
■ Voltage feed-forward
■ Zero load current operation
■ Overcurrent and thermal protection
■ VFQFPN3x3-10L and HSOP8 package
Applications
■ Consumer: STB, DVD, DVD recorder, car
audio, LCD TV and monitors
■ Industrial: PLD, PLA, FPGA, chargers
■ Networking: XDSL, modems, DC-DC modules
■ Computer: optical storage, hard disk drive,
printers, audio/graphic cards
■ LED driving
L7985
2 A step-down switching regulator
VFQFPN10 3 x 3 mm HSOP8 Exp. pad
Description
The L7985/A is a step-down switching regulator
with 2.5 A (minimum) current limited embedded
power MOSFET, so it is able to deliver up to 2 A
current to the load depending on the application
conditions.
The input voltage can range from 4.5 V to 38 V,
while the output voltage can be set starting from
0.6 V to V
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The QFN and the HSOP packages with exposed
pad allow reducing the R
and 40 °C/W respectively.
.
IN
down to 60 °C/W
thJA
Figure 1. Application circuit
Vin=4.5V - 38V
VCC
9-10
C1
EN
43
L7985
GND FB
8
R5
6
7
COMPFSW
OUT
1-2
SYNCH
5
R4 R1
C4
C5
D1
R2
L1
March 2012 Doc ID 022446 Rev 2 1/44
Vout f rom 0.6 to Vin
C2
www.st.com
44
Contents L7985
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/44 Doc ID 022446 Rev 2
L7985 Contents
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Doc ID 022446 Rev 2 3/44
Pin settings L7985
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYNCH
SYNCH
SYNCH
SYNCH
SYNCH
SYNCH
EN
EN
EN
COMP
COMP
COMP
COMP
COMP
COMP
VFQFPN10
VFQFPN10
1.2 Pin description
Table 1. Pin description
V
V
V
CCVCC
CCVCC
CCVCC
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
GND
GND
GND
GND
GND
GND
FSW
FSW
FSW
FSW
FSW
FSW
FB
FB
FB
FB
FB
FB
OUT
OUT
OUT
OUT
OUT
OUT
SYNCH
SYNCH
SYNCH
SYNCH
SYNCH
SYNCH
EN
EN
EN
COMP
COMP
COMP
COMP
COMP
COMP
HSOP8
HSOP8
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
GND
GND
GND
GND
GND
GND
FSW
FSW
FSW
FSW
FSW
FSW
FB
FB
FB
FB
FB
FB
N.
(VFQFPN)N.(HSOP)
Type Description
1-2 1 OUT Regulator output
Master/slave synchronization. When it is left floating, a
signal with a phase shift of half a period, with respect to the
power turn-on, is present at the pin. When connected to an
external signal at a frequency higher than the internal one,
3 2 SYNCH
the device is synchronized by the external signal, with zero
phase shift.
Connecting together the SYNCH pin of two devices, the one
with a higher frequency works as master and the other one
as slave; so the two power turn-ons have a phase shift of
half a period.
A logical signal (active high) enables the device. With EN
43EN
higher than 1.2 V the device is ON and with EN lower than
0.3 V the device is OFF.
54COMP
Error amplifier output to be used for loop frequency
compensation.
Feedback input. By connecting the output voltage directly to
65FB
this pin the output voltage is regulated at 0.6 V. To have
higher regulated voltages an external resistor divider is
required from V
The switching frequency can be increased connecting an
76F
SW
external resistor from the FSW pin and ground. If this pin is
left floating, the device works at its free-running frequency of
250 KHz.
8 7 GND Ground
to the FB pin.
OUT
9-10 8 V
CC
Unregulated DC input voltage.
4/44 Doc ID 022446 Rev 2
L7985 Maximum ratings
2 Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
Vcc Input voltage 45
OUT Output DC voltage -0.3 to V
FSW, COMP, SYNCH Analog pin -0.3 to 4
EN Enable pin -0.3 to V
FB Feedback voltage -0.3 to 1.5
P
TOT
T
J
T
stg
3 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
thJA
1. Package mounted on demonstration board.
Maximum thermal resistance
junction-ambient
CC
V
CC
Power dissipation
< 60 °C
at T
A
VFQFPN 1.5. W
HSOP 2
Junction temperature range -40 to 150 °C
Storage temperature range -55 to 150 °C
VFQFPN 60
(1)
HSOP 40
°C/W
Doc ID 022446 Rev 2 5/44
Electrical characteristics L7985
4 Electrical characteristics
TJ = 25 °C, V
Table 4. Electrical characteristics
= 12 V, unless otherwise specified.
CC
Val ues
Symbol Parameter Test conditions
Min. Typ. Max.
V
V
CCON
V
CCHYS
CC
Operating input voltage
range
Tur n o n VCC threshold
VCC UVLO hysteseris
(1)
(1)
(1)
4.5 38
0.1 0.4
200
R
DSON
I
LIM
MOSFET on resistance
(1)
Maximum limiting current 2.5 3.0 3.5 A
Oscillator
(1)
210 250 275 KHz
V
F
SW
FSW
Switching frequency
FSW pin voltage 1.254 V
D Duty cycle 0 100 %
F
ADJ
Adjustable switching
frequency
R
=33 kΩ 1000 KHz
FSW
4.5
400
Unit
V
mΩ
Dynamic characteristics
V
FB
Feedback voltage
DC characteristics
I
Q
I
QST-BY
Quiescent current
Total standby quiescent
current
Enable
V
EN
I
EN
EN threshold voltage
EN current EN=V
Soft-start
T
SS
Soft-start duration
4.5 V<V
4.5 V<V
Duty cycle=0, V
V
<38 V 0.593 0.6 0.607
CC
(1)
CC
<38 V
FB
=0.8
0.582 0.6 0.618
2.4 mA
20 30 µA
Device OFF level 0.3
Device ON level 1.2
CC
7.5 10 µA
FSW pin floating 7.4 8.2 9.1
=1 MHz,
F
R
SW
FSW
=33 kΩ
2
V
V
ms
6/44 Doc ID 022446 Rev 2
L7985 Electrical characteristics
Table 4. Electrical characteristics
Val ues
Symbol Parameter Test conditions
Min. Typ. Max.
Error amplifier
Unit
V
CH
V
CL
I
O SOURCE
I
O SINK
G
High level output voltage VFB<0.6 V 3
Low level output voltage VFB>0.6 V 0.1
Source COMP pin VFB=0.5 V, V
Sink COMP pin VFB=0.7 V, V
Open-loop voltage gain
V
Synchronization function
V
S_IN,HI
V
S_IN,LO
t
S_IN_PW
I
SYNCH,LO
V
S_OUT,HI
t
S_OUT_PW
High input voltage 2 3.3
Low input voltage 1
Input pulse width
Slave sink current V
Master output amplitude I
Output pulse width SYNCH floating 110 ns
Protection
Thermal shutdown 150
T
SHDN
Hystereris 30
(2)
V
S_IN,HI
V
S_IN,LO
V
S_IN,HI
V
S_IN,LO
SYNCH
SOURCE
V
=1 V 19 mA
COMP
=1 V 30 mA
COMP
100 dB
V
=3 V,
=0 V
100
ns
=2 V,
=1 V
300
=2.9 V 0.7 1 mA
=4.5 mA 2 V
°C
1. Specifications referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range
are assured by design, characterization and statistical correlation.
2. Guaranteed by design.
Doc ID 022446 Rev 2 7/44
Functional description L7985
5 Functional description
The L7985 is based on a “voltage mode” constant frequency control. The output voltage
is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing
V
OUT
an error signal that, compared to a fixed frequency sawtooth, controls the on- and off-time of
the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
● A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed-forward are implemented.
● The soft-start circuitry to limit inrush current during the startup phase.
● The voltage mode error amplifier.
● The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
● The high-side driver for embedded P-channel power MOSFET switch.
● The peak current limit sensing block, to handle overload and short-circuit conditions.
● A voltage regulator and internal reference. To supply the internal circuitry and provide a
fixed internal reference.
● A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
● A thermal shutdown block, to prevent thermal runaway.
Figure 3. Block diagram
TRIMMING UVLO
TRIMMING UVLOUVLO
EN
EN
COMP
COMP
0.6V
0.6V
SOFT-
SOFT-
START
START
EN
EN
FB
FB
REGULATOR
REGULATOR
REGULATOR
&
&
&
BANDGAP
BANDGAP
BANDGAP
1.254V 3.3V
1.254V 3.3V
THERMAL
THERMAL
SHUTDOWN
SHUTDOWN
E/A
E/A
OSCILLATOR
OSCILLATOR
FSW
FSW
PWM
PWM
GND
GND
PEAK
PEAK
CURRENT
CURRENT
LIMIT
LIMIT
SRQ
SRQ
SYNCH
SYNCH
&
&
PHASE SHIFT
PHASE SHIFT
SYNCH
SYNCH
DRIVER
DRIVER
VCC
VCC
OUT
OUT
8/44 Doc ID 022446 Rev 2
L7985 Functional description
5.1 Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a
constant frequency clock. Its frequency depends on the resistor externally connect to the
FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as
shown in Figure 6 by an external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed-forward is implemented (Figure 5.b) in order
to keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM
gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When the SYNCH pins are connected, the device with
a higher oscillator frequency works as master, so the slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor (see the L5988D datasheet).
Figure 4. Oscillator circuit block diagram
Clock
ClockClock
FSW
FSW
The device can be synchronized to work at higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This change has to be taken into account when the loop stability is studied. To
minimize the change of PWM gain, the free-running frequency should be set (with a resistor
on the FSW pin) only slightly lower than the external clock frequency. This pre-adjusting of
the frequency changes the sawtooth slope in order to render the truncation of sawtooth
negligible, due to the external synchronization.
Clock
Clock
Generator
Generator
Synchronization
Synchronization
Ramp
Ramp
Generator
Generator
SYNCH
SYNCH
Sawtooth
Sawtooth
Doc ID 022446 Rev 2 9/44
Functional description L7985
Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization
Figure 6. Oscillator frequency vs. FSW pin resistor
10/44 Doc ID 022446 Rev 2
L7985 Functional description
5.2 Soft-start
The soft-start is essential to assure correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monothonically.
The soft-start is performed by a staircase ramp on the non-inverting input (V
) of the error
REF
amplifier. So the output voltage slew rate is:
Equation 1
VREF
⎛⎞
1
------- -+
⋅=
⎝⎠
R2
where SR
SR
is the slew rate of the non-inverting input, while R1and R2 is the resistor
VREF
OUT
SR
R1
divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64
steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So
the soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 2
32 64⋅
SS
TIME
--------------------=
Fsw
For example, with a switching frequency of 250 kHz, the SS
Doc ID 022446 Rev 2 11/44
TIME
is 8 ms.
Functional description L7985
5.3 Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier, therefore, with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5. Uncompensated error amplifier characteristics
Low frequency gain 100 dB
GBWP 4.5 MHz
Slew rate 7 V/µs
Output voltage swing 0 to 3.3 V
Maximum source/sink current 17 mA/25 mA
In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. If the zero introduced by the output capacitor helps to compensate the double
pole of the LC filter, a type II compensation network can be used. Otherwise, a type III
compensation network must be used (see Chapter 6.4 for details of the compensation
network selection).
Anyway, the methodology to compensate the loop is to introduce zeroes to obtain a safe
phase margin.
12/44 Doc ID 022446 Rev 2
L7985 Functional description
5.4 Overcurrent protection
The L7985 implements overcurrent protection by sensing current flowing through the power
MOSFET. Due to the noise created by the switching activity of the power MOSFET, the
current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.
If the overcurrent limit is reached, the power MOSFET is turned off, implementing pulse-bypulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses
in order to keep the output current constant and equal to the current limit. If, at the end of the
“masking time”, the current is higher than the overcurrent threshold, the power MOSFET is
turned off and one pulse is skipped. If, at the following switching on, when the “masking
time” ends, the current is still higher than the overcurrent threshold, the device skips two
pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at
the end of the “masking time”, the current is lower than the overcurrent threshold, the
number of skipped cycles is decreased by one unit (see Figure 8).
So, the overcurrent/short-circuit protection acts by switching off the power MOSFET and
reducing the switching frequency down to one eighth of the default switching frequency, in
order to keep constant the output current around the current limit.
This kind of overcurrent protection is effective if the output current is limited. To prevent the
current from diverging, the current ripple in the inductor during the on-time must not be
higher than the current ripple during the off-time. That is:
Equation 3
VINV–
----------------------------------------------------------- --------------------------------------------------------------
If the output voltage is shorted, V
OUT
R
⋅ DCR I
DSONIOUT
LF
⋅
SW
⋅––
OUT
OUT
≅ 0, I
V
OUTVFRDSONIOUT
------------------------------------------------------------- ----------------------------------------------------------
D⋅
OUT=ILIM
, D/FSW=T
⋅ DCR I
⋅
LF
SW
ON_MIN
, (1-D)/FSW≅ 1/FSW. So,
⋅++ +
OUT
1D–()⋅=
from Equation 3, the maximum switching frequency that guarantees to limit the current
results:
Equation 4
VFDCR I⋅+
With R
*
F
SW
=300 mΩ, DRC=0.08 Ω, the worst condition is with VIN=38 V, I
DSON
()
--------------------------------------------------------------- ----------------------
V
INRDSON
LIM
DCR+()I
⋅–()
LIM
------------------------ -
⋅=
T
ON_MIN
1
=2.5A; the
LIM
maximum frequency to keep the output current limited during the short-circuit results 74
kHz.
The pulse-by-pulse mechanism, which reduces the switching frequency down to one eighth
of the maximum F
, adjusted by the FSW pin, assures that a full effective output current
SW
limitation is 74 kHz*8=592 kHz.
If, with V
=38 V, the switching frequency is set higher than 592 kHz, during short-circuit
IN
condition the system finds a different equilibrium with higher current. For example, with
F
=700 kHz and the output shorted to ground, the output current is limited around:
SW
Doc ID 022446 Rev 2 13/44
Functional description L7985
Equation 5
*
VINF
I
OUT
⋅ VFT
--------------------------------------------------------- ---------------------------------------------------------------- -- 3.68A==
DRC T
⁄()R
SW
ON_MIN
⁄–
DSON
ON_MIN
DCR+()F
*
⋅+
SW
where F
* is 700 kHz divided by eight.
SW
Figure 8. Overcurrent protection
5.5 Enable function
The enable feature allows to put the device into standby mode. With the EN pin lower than
0.3 V the device is disabled and the power consumption is reduced to less than 30 µA. With
the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal
pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is
disabled. The pin is also V
compatible.
CC
5.6 Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature returns to about 130 °C, the
device restarts in normal operation. The sensing element is very close to the PDMOS area,
so ensuring an accurate and fast temperature detection.
14/44 Doc ID 022446 Rev 2
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