ST L6919E User Manual

L6919E

L6919E

5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT

■2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL

■ULTRA FAST LOAD TRANSIENT RESPONSE

■INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT

■TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT FROM 0.800V TO 1.550V WITH 25mV STEPS

■DYNAMIC VID MANAGEMENT

■0.6% OUTPUT VOLTAGE ACCURACY

■10% ACTIVE CURRENT SHARING ACCURACY

■DIGITAL 2048 STEP SOFT-START

■OVERVOLTAGE PROTECTION

■OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S RdsON OR A SENSE RESISTOR

■OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 200kHz

■POWER GOOD OUTPUT AND INHIBIT FUNCTION

■REMOTE SENSE BUFFER

■PACKAGE: SO-28

APPLICATIONS

■POWER SUPPLY FOR SERVERS AND WORKSTATIONS

■POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS

■DISTRIBUTED POWER SUPPLY

SO-28

ORDERING NUMBERS:L6919E

L6919ETR

DESCRIPTION

The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. The device implements a dual-phase step-down controller with a 180° phase-shift between each phase. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 0.800V to 1.550V with 25mV binary steps managing On-The-Fly VID code changes.

The high precision internal reference assures the selected output voltage to be within ±0.6%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses.

The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Current mode.

BLOCK DIAGRAM

		O S C / I NH		S GN D					VC C D R
											BOO T 1
PGO O D		2 PHASE	IL LATOR							HS	U
									SS CO ND UCTION		GA T E1
					PW M1		L OG IC PW M	DA PTIV E A NT I
											PHAS E1
			P ROTE CTIONOSCS		AV G C URRENT	CORTIONREC	CH1	A	CRO	L S	L GAT E1
							OCP
	DIGIT AL	LOGIC AN D
				V CC
	SOFT-START										ISE N1
				V CC DR
				TO TAL			CUR REN T				PGN DS1
				C UR REN T			REA DIN G
VID 4				U R R EN T							PGN D
VID 3							CUR REN T				PGN DS2
VID 2	D AC
							REA DIN G
VID 1				C
			CH 2 OC P								ISE N2
VID 0
		C H1 OCP
						C OR R EC TION
					CU R R EN T		CH2		CON DU CT ION	LS	L GAT E2
								PT IV E A N T I
	32k						OCP
							GIC PW M
FB G	3 2k	I FB									PHAS E2
FB R	3 2k				PW M2		LO	A DA	CROSS
										HS
											U GA T E2
	R EMOTE
	32k
	BUFFER						Vcc
				ERR OR							BOO T 2
				A MPL IF IER
	V S EN		FB	COM P			V c c

September 2003

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L6919E

ABSOLUTE MAXIMUM RATINGS

	Symbol	Parameter	Value	Unit
	Vcc, VCCDR	to PGND	15	V
	VBOOT-VPHASE	Boot Voltage	15	V
	VUGATE1-VPHASE1		15	V
	VUGATE2-VPHASE2
		LGATE1, PHASE1, LGATE2, PHASE2 to PGND	-0.3 to Vcc+0.3	V
		VID0 to VID4	-0.3 to 5	V
		All other pins to PGND	-0.3 to 7	V
	Vphase	Sustainable Peak Voltage t < 20ns @ 600kHz	26	V
	UGATEx Pin	Maximum Withstanding Voltage Range	±1000	V
		Test Condition: CDF-AEC-Q100-002”Human Body Model”
	OTHER PINS		±2000	V
		Acceptance Criteria: “Normal Performance”

THERMAL DATA

Symbol	Parameter	Value	Unit
Rth j-amb	Thermal Resistance Junction to Ambient	60	°C/W
Tmax	Maximum junction temperature	150	°C
Tstorage	Storage temperature range	-40 to 150	°C
Tj	Junction Temperature Range	0 to 125	°C
PMAX	Max power dissipation at Tamb = 25°C	2	W

PIN CONNECTION

LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
SGND
COMP
FB
VSEN
FBR	11
FBG	12
ISEN1	13
PGNDS1	14

L6919E

28	PGND
27	LGATE2
26	PHASE2
25	UGATE2
24	BOOT2
23	PGOOD
22	VID4

21VID3

VID2

VID1

VID0

OSC / INH / FAULT ISEN2

PGNDS

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							L6919E
ELECTRICAL CHARACTERISTICS
VCC = 12V ±15%, TJ = 0 to 70°C unless otherwise specified
Symbol	Parameter		Test Condition	Min	Typ	Max		Unit
Vcc SUPPLY CURRENT
ICC	Vcc supply current		HGATEx and LGATEx open	7.5	10	12.5		mA
			VCCDR=VBOOT=12V
ICCDR	VCCDR supply current		LGATEx open; VCCDR=12V	2	3	4		mA
IBOOTx	Boot supply current		HGATEx open; PHASEx to PGND	0.5	1	1.5		mA
			VCC=VBOOT=12V
POWER-ON
	Turn-On VCC threshold		VCC Rising; VCCDR=5V	8.2	9.2	10.2		V
	Turn-Off VCC threshold		VCC Falling; VCCDR=5V	6.5	7.5	8.5		V
	Turn-On VCCDR		VCCDR Rising	4.2	4.4	4.6		V
	Threshold		VCC=12V
	Turn-Off VCCDR		VCCDR Falling	4.0	4.2	4.4		V
	Threshold		VCC=12V
OSCILLATOR/INHIBIT/FAULT
fOSC	Initial Accuracy		OSC = OPEN	135	150	165		kHz
			OSC = OPEN; Tj=0°C to 125°C	127		178		kHz
INH	Inhibit threshold		ISINK=5mA	0.5				V
dMAX	Maximum duty cycle		OSC = OPEN; IFB = 0	72	80			%
			OSC = OPEN; IFB = 70μA	30	40			%
Vosc	Ramp Amplitude				3			V
FAULT	Voltage at pin OSC		OVP or UVP Active	4.75	5.0	5.25		V
REFERENCE AND DAC
	Output Voltage		VID0, VID1, VID2, VID3, VID4	-0.6	-	0.6		%
	Accuracy		see Table1;
			FBR = VOUT; FBG = GND
IDAC	VID pull-up Current		VIDx = GND	4	5	6		μA
	VID pull-up Voltage		VIDx = OPEN	2.9	-	3.3		V
ERROR AMPLIFIER
	DC Gain				80			dB
SR	Slew-Rate		COMP=10pF		15			V/μs
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
	DC Gain				1			V/V
CMRR	Common Mode Rejection Ratio				40			dB
SR	Slew Rate		VSEN=10pF		15			V/μs
							3/33

L6919E

ELECTRICAL CHARACTERISTICS (continued)

VCC = 12V ±15%, TJ = 0 to 70°C unless otherwise specified

Symbol	Parameter	Test Condition	Min	Typ	Max	Unit
DIFFERENTIAL CURRENT SENSING
IISEN1,	Bias Current	ILOAD = 0	45	50	55	μA
IISEN2
IPGNDSx	Bias Current		45	50	55	μA
IISEN1,	Bias Current at		80	85	90	μA
IISEN2	Over Current Threshold
IFB	Active Droop Current	ILOAD ≤ 0%		0	1	μA
		ILOAD = 100%	47.5	50	52.5	μA
GATE DRIVERS
tRISE	High Side	VBOOTx-VPHASEx=10V;		15	30	ns
HGATE	Rise Time	CHGATEx to PHASEx=3.3nF
IHGATEx	High Side	VBOOTx-VPHASEx=10V		2		A
	Source Current
RHGATEx	High Side	VBOOTx-VPHASEx=12V;	1.5	2	2.5	Ω
	Sink Resistance
tRISE	Low Side	VCCDR=10V;		30	55	ns
LGATE	Rise Time	CLGATEx to PGNDx=5.6nF
ILGATEx	Low Side	VCCDR=10V		1.8		A
	Source Current
RLGATEx	Low Side	VCCDR=12V	0.7	1.1	1.5	Ω
	Sink Resistance
PROTECTIONS
PGOOD	Upper Threshold	VSEN Rising	108	112	116	%
	(VSEN/DAC Output)
PGOOD	Lower Threshold	VSEN Falling	84	88	92	%
	(VSEN/DAC Output)
OVP	Over Voltage Threshold	VSEN Rising	1.915		2.05	V
	(VSEN)
UVP	Under Voltage Trip	VSEN Falling	55	60	65	%
	(VSEN/DAC Output)
VPGOODL	PGOOD Voltage Low	IPGOOD = -4mA			0.4	V
IPGOODH	PGOOD Leakage	VPGOOD = 5V			1	μA

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												L6919E
	Table 1. Voltage Identification (VID) Codes
	VID4	VID3	VID2	VID1	VID0	Output	VID4	VID3	VID2	VID1	VID0	Output
						Voltage (V)						Voltage (V)
	0	0	0	0	0	1.575	1	0	0	0	0	1.175
	0	0	0	0	1	1.550	1	0	0	0	1	1.150
	0	0	0	1	0	1.525	1	0	0	1	0	1.125
	0	0	0	1	1	1.500	1	0	0	1	1	1.100
	0	0	1	0	0	1.475	1	0	1	0	0	1.075
	0	0	1	0	1	1.450	1	0	1	0	1	1.050
	0	0	1	1	0	1.425	1	0	1	1	0	1.025
	0	0	1	1	1	1.400	1	0	1	1	1	1.000
	0	1	0	0	0	1.375	1	1	0	0	0	0.975
	0	1	0	0	1	1.350	1	1	0	0	1	0.950
	0	1	0	1	0	1.325	1	1	0	1	0	0.925
	0	1	0	1	1	1.300	1	1	0	1	1	0.900
	0	1	1	0	0	1.275	1	1	1	0	0	0.875
	0	1	1	0	1	1.250	1	1	1	0	1	0.850
	0	1	1	1	0	1.225	1	1	1	1	0	0.825
	0	1	1	1	1	1.200	1	1	1	1	1	Shutdown

The device automatically regulates 25mV higher than the Hammer specs avoiding the use of any external offset resistor

Reference Schematic

Vin
GNDin					CIN
	VCCDR			VCC
	2			6
	BOOT1			BOOT2
	5			24
HS1	UGATE1			UGATE2	HS2
	4			25
L1	PHASE1			PHASE2	L2
	3			26
LS1	LGATE1			LGATE2	COUT	LOAD
	1			27	LS2
	ISEN1			ISEN2
	13			16
	Rg				Rg
	PGNDS1	L6919E		PGNDS2
	14			15
	Rg			PGND	Rg
				28
S4	VID4
S3	22			PGOOD		PGOOD
	VID3			23
S2	21			VSEN
	VID2			10
S1	20
	VID1
S0	19			FB	RFB
	VID0
	18			9
	OSC / INH
	17				RF
	SGND				CF
	7			COMP
		11	12	8
	FBR		FBG
						5/33

L6919E

PIN FUNCTION

N	Name	Description
1	LGATE1	Channel 1 LS driver output.
		A little series resistor helps in reducing device-dissipated power.
2	VCCDR	LS drivers supply: it can be varied from 5V to 12V buses.
		Filter locally with at least 1μF ceramic cap vs. PGND.
3	PHASE1	Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides
		the return path for the HS driver of channel 1.
4	UGATE1	Channel 1 HS driver output.
		A little series resistor helps in reducing device-dissipated power.
5	BOOT1	Channel 1 HS driver supply. This pin supplies the relative high side driver.
		Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode to VCC
		(cathode vs. boot).
6	VCC	Device supply voltage. The operative supply voltage is 12V ±10%.
		Filter with 1μF (Typ.) capacitor vs. GND.
7	GND	All the internal references are referred to this pin. Connect it to the PCB signal ground.
8	COMP	This pin is connected to the error amplifier output and is used to compensate the control
		feedback loop.
9	FB	This pin is connected to the error amplifier inverting input and is used to compensate the
		voltage control feedback loop.
		A current proportional to the sum of the current sensed in both channel is sourced from this pin
		(50μA at full load, 70μA at the Constant Current threshold). Connecting a resistor between this
		pin and VSEN pin allows programming the droop effect.
10	VSEN	Manages Over&Under-voltage conditions and the PGOOD signal. It is internally connected with
		the output of the Remote Sense Buffer for Remote Sense of the regulated voltage.
		If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
		manage OVP, UVP and PGOOD.
		Connecting 1nF capacitor max vs. SGND can help in reducing noise injection.
11	FBR	Remote sense buffer non-inverting input. It has to be connected to the positive side of the load
		to perform a remote sense.
		If no remote sense is implemented, connect directly to the output voltage (in this case connect
		also the VSEN pin directly to the output regulated voltage).
12	FBG	Remote sense buffer inverting input. It has to be connected to the negative side of the load to
		perform a remote sense.
		Pull-down to ground if no remote sense is implemented.
13	ISEN1	Channel 1 current sense pin. The output current may be sensed across a sense resistor or
		across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or
		to the sense resistor through a resistor Rg.
		The net connecting the pin to the sense point must be routed as close as possible to the
		PGNDS net in order to couple in common mode any picked-up noise.
14	PGNDS1	Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be
		routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up
		noise.
15	PGNDS2	Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be
		routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up
		noise.
16	ISEN2	Channel 2 current sense pin. The output current may be sensed across a sense resistor or
		across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or
		to the sense resistor through a resistor Rg.
		The net connecting the pin to the sense point must be routed as close as possible to the
		PGNDS net in order to couple in common mode any picked-up noise.
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		L6919E
PIN FUNCTION (continued)
N	Name	Description
17	OSC/INH	Oscillator pin.
	FAULT	It allows programming the switching frequency of each channel: the equivalent switching
		frequency at the load side results in being doubled.
		Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from
		(into) the pin with an internal gain of 6kHz/μA (See relevant section for details). If the pin is not
		connected, the switching frequency is 150kHz for each channel (300kHz on the load).
		The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this
		condition, cycle VCC.
		Forcing the pin to a voltage lower than 0.6V, the device stop operation and enter the inhibit
		state.
18-22	VID4-0	Voltage IDentification pins.
		Internally pulled-up, connect to GND to program a ‘0’ while leave floating to program a ‘1’.
		They are used to program the output voltage as specified in Table 1 and to set the PGOOD,
		OVP and UVP thresholds.
		The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of
		any external set-up resistor.
23	PGOOD	This pin is an open collector output and is pulled low if the output voltage is not within the above
		specified thresholds and during soft start. It cannot be pulled-up above 5V.
		If not used may be left floating.
24	BOOT2	Channel 2 HS driver supply. This pin supplies the relative high side driver.
		Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode to VCC
		(cathode vs. boot).
25	UGATE2	Channel 2 HS driver output.
		A little series resistor helps in reducing device-dissipated power.
26	PHASE2	Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides
		the return path for the HS driver of channel 2.
27	LGATE2	Channel 2 LS driver output.
		A little series resistor helps in reducing device-dissipated power.
28	PGND	LS drivers return path.
		This pin is common to both sections and it must be connected through the closest path to the
		LS mosfets source pins in order to reduce the noise injection into the device.

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L6919E

DEVICE DESCRIPTION

The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 0.825V to 1.575V with 25mV binary steps, with a maximum tolerance of ±0.6% over temperature and line voltage variations. The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor. The device manages On-The-Fly VID Code changes stepping to the new configuration following the VID table with no need for external components. The device provides an average current-mode control with fast transient response. It includes a 150kHz free-running oscillator. The error amplifier features a 15V/ms slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a sense resistor in fully differential mode. The current information corrects the PWM output in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions. The device protects against Over-Current, with an OC threshold for each phase, entering in constant current mode. Since the current is read across the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular waveform. When an under voltage is detected the device latches and the FAULT pin is driven high. The device performs also Over-Voltage protection that disables immediately the device turning ON the lower driver and driving high the FAULT pin.

OSCILLATOR

The switching frequency is internally fixed at 150kHz. Each phase works at the frequency fixed by the oscillator so that the resulting switching frequency at the load side results in being doubled.

The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 25 A (Fsw=150kHz) and may be varied using an external resistor (ROSC) connected between OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (Typ. 1.237V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6KHz/mA.

In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:

1.237

×

kHz

150kHz + 7.422 × 10

6

R

vs. GND: f

= 150kHz

+

6

=

OSC

S

R------O---S----C--

----------

--

mA

ROSC (KW)

12 –

1.237

×

kHz

= 150kHz – 6.457 × 10

7

R

vs. 12V: f

=

150kHz

–

OSC

S

---

---

R-------O--S----C------

--

6----------

--

mA

ROSC (KW)

Note that forcing a 25mA into this pin, the device stops switching because no current is delivered to the oscillator.

Figure 1. ROSC vs. Switching Frequency

	14000
	12000
vs. 12V	10000
	8000
)
Rosc(KΩ	6000
	4000
	2000
	0
	25	50	75	100	125	150

Frequency (KHz)

	800
GND	700
	600
) vs.	500
	400
Rosc(KΩ
	300
	200
	100
	0
	150	250	350	450	550	650

Frequency (KHz)

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L6919E

DIGITAL TO ANALOG CONVERTER

The built-in digital to analog converter allows the adjustment of the output voltage from 0.800V to 1.550V with 25mV as shown in the previous table 1. The internal reference is trimmed to ensure output voltage precision of ±0.6% and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5μA current generator up to 3.0V Typ); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. Programming the "11111" code, the device enters the NOCPU mode: all mosfets are turned OFF and protections are disabled. The condition is latched.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over / Under Voltage protection (OVP/UVP) thresholds.

DYNAMIC VID TRANSITION

The device is able to manage On-The-Fly VID Code changes that allow Output Voltage modification during normal device operation. The device checks every clock cycle (synchronously with the PWM ramp) for VID code modifications. Once the new code is stable for more than one clock cycle, the reference steps up or down in 25mV increments every clock cycle until the new VID code is reached. During the transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished. PGOOD, signal is masked during the transition and it is re-activated after the transition has finished while OVP / UVP are still active.

Figure 2. Dynamic VID transition

VID
Reference	t
	25mV steps transition
VOUT	t
	t

1 Clock Cycle Blanking Time

DRIVER SECTION

The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the RdsON), maintaining fast switching transition.

The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VCCDRV pin is required to start operations of the device.

The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will never drop.

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L6919E

Figure 3. Drivers peak current: High Side (left) and Low Side (right)

CH3 = HGATE1; CH4 = HGATE2

CH3 = LGATE1; CH4 = LGATE2

To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative.

The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion is also flexible; 5V or 12V bus can be chosen freely.

The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capacitive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with

VBOOT -VPHASE = 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with VCCDR = 12V.

CURRENT READING AND OVER CURRENT

The current flowing trough each phase is read using the voltage drop across the low side mosfets RdsON or across a sense resistor (RSENSE) and internally converted into a current. The Tran conductance ratio is issued

by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points. The full differential current reading rejects noise and allows to place sensing element in different locations without affecting the measurement's accuracy. The current reading circuitry reads the current during the time in which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two

pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet RdsON sense is implemented to avoid absolute maximum rating overcome on ISENx pin).

The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and negative current. This circuit reproduces the current flowing through the sensing element using a high speed Track & Hold Tran conductance amplifier. In particular, it reads the current during the second half of the OFF time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least 200ns to make proper reading of the delivered current

This circuit sources a constant 50mA current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following equation:

I 50mA RSENSE × IPHASE 50mA I

ISENx = + ---------------------------------------------- = + INFOx

Rg

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