ST L6917 User Manual

L6917DTR

L6917

5BIT PROGRAMMABLE DUAL-PHASE CONTROLLER

■2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL

■ULTRA FAST LOAD TRANSIENT RESPONSE

■INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT

■TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT COMPLIANT WITH VRM 9.0

■0.8% INTERNAL REFERENCE ACCURACY

■10% ACTIVE CURRENT SHARING ACCURACY

■DIGITAL 2048 STEP SOFT-START

■OVERVOLTAGE PROTECTION

■OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S RdsON OR A SENSE RESISTOR

■300 kHz INTERNAL OSCILLATOR

■OSCILLATOR EXTERNALLY ADJUSTABLE UP TO 1MHz

■POWER GOOD OUTPUT AND INHIBIT FUNCTION

■REMOTE SENSE BUFFER

■PACKAGE: SO-28

APPLICATIONS

■POWER SUPPLY FOR SERVER AND WORKSTATION

■POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS

■DISTRIBUTED POWER SUPPLY

BLOCK DIAGRAM

		ROSC / IN H
	PGO OD
		2 PH ASE
		OSCILLATOR
	DIGI TAL	VCC
	SO FT STA RT
		VCC DR

SO-28

ORDERING NUMBERS: L6917D

L6917DTR (Tape & Reel)

DESCRIPTION

The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors.

The device implements a dual-phase step-down controller with a 180° phase-shift between each phase. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 1.100V to 1.850V with 25mV binary steps.

The high precision internal reference assures the selected output voltage to be within ±0.8%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses.

The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current or under voltage, the system works in HICCUP mode.

SG ND			VCCDR
			BOOT 1
			UGATE1
CURRENT CORRECTION		LOGICPWM ADAPTIVEANTI CROSS-CONDUCTION	HS
	CU RR ENT		LG ATE1
PWM1			PH ASE1
-
+
	CH 1 OVER
			L S
			ISEN1

LO GIC

AND

PROTECTIONS

	VID4
	VID3
	VID2	DAC
	VID1
			CH 2 OVER
	VID0		CURR ENT
			CH1 OVER
			CU RR ENT
			1 0k
		1 0k	+
	FBG		IFB

-

FBR	1 0k	ERROR
		AMPLIFIER
		REMOT E
	10k	BUFFER

TOTAL	+
CURR ENT
AVG
CU RRENT	< >
CURRENT CORRECTION	CH 2 OVER
	CU RR ENT
PWM2

Vcc

CURRENT READ ING

CURRENT READ ING

CROSS-CONDUCTION

ADAPTIVE ANTI

LOGIC PWM

PGNDS 1

PGND

PGNDS 2

ISEN2

LG ATE2

L S

PH ASE2

UGATE2

HS

BOOT 2

VSEN	FB	COMP	Vc c
October 2001			1/27

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L6917

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value	Unit
Vcc, VCCDR	To PGND	15	V
VBOOT-VPHASE	Boot Voltage	15	V
VUGATE1-VPHASE1		15	V
VUGATE2-VPHASE2
	LGATE1, PHASE1, LGATE2, PHASE2 to PGND	-0.3 to Vcc+0.3	V
	All other pins to PGND	-0.3 to 7	V

THERMAL DATA

Symbol	Parameter	Value	Unit
Rth j-amb	Thermal Resistance Junction to Ambient	60	°C/W
Tmax	Maximum junction temperature	150	°C
Tstorage	Storage temperature range	-40 to 150	°C
Tj	Junction Temperature Range	-25 to 125	°C
PMAX	Max power dissipation at Tamb = 25°C	2	W

PIN CONNECTION

LGATE1	1	28	PGND
VCCDR	2	27	LGATE2
PHASE1	3	26	PHASE2
UGATE1	4	25	UGATE2
BOOT1	5	24	BOOT2
VCC	6	23	PGOOD
GND	7	22	VID4
COMP	8	21	VID3
FB	9	20	VID2
VSEN	10	19	VID1
FBR	11	18	VID0
FBG	12	17	OSC / INH/ FAULT
ISEN1	13	16	ISEN2
PGNDS1	14	15	PGNDS2
		SO28

2/27

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L6917

ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamb = 25°C unless otherwise specified)

Symbol	Parameter	Test Condition	Min	Typ	Max	Unit
Vcc SUPPLY CURRENT
ICC	Vcc supply current	HGATEx and LGATEx open	6	8	10	mA
		VCCDR=VBOOT=12V
ICCDR	VCCDR supply current	LGATEx open; VCCDR=12V	2	3	4	mA
IBOOTx	Boot supply current	HGATEx open; PHASEx to PGND	0.5	1	1.5	mA
		VCC=VBOOT=12V
POWER-ON
	Turn-On VCC threshold	VCC Rising; VCCDR=5V	7.8	9	10.2	V
	Turn-Off VCC threshold	VCC Falling; VCCDR=5V	6.5	7.5	8.5	V
	Turn-On VCCDR	VCCDR Rising	4.2	4.4	4.6	V
	Threshold	VCC=12V
	Turn-Off VCCDR	VCCDR Falling	4.0	4.2	4.4	V
	Threshold	VCC=12V
OSCILLATOR AND INHIBIT
fOSC	Initial Accuracy	OSC = OPEN	278	300	322	kHz
		OSC = OPEN; Tj=0°C to 125°C	270		330	kHz
fOSC,Ros	Total Accuracy	RT to GND=74kΩ	450	500	550	kHz
c
INH	Inhibit threshold	ISINK=5mA	0.8	0.85	0.9	V
dMAX	Maximum duty cycle	OSC = OPEN	80	85		%
Vosc	Ramp Amplitude		1.8	2	2.2	V
REFERENCE AND DAC
	Output Voltage	VID0, VID1, VID2, VID3, VID4	-0.8	-	0.8	%
	Accuracy	see Table1; Tamb=0° to 70°;
		FBR = VOUT; FBG = GND
IDAC	VID pull-up Current	VIDx = GND	4	5	6	μA
	VID pull-up Voltage	VIDx = OPEN	3.1	-	3.4	V
ERROR AMPLIFI ER
	DC Gain			80		dB
SR	Slew-Rate	COMP=10pF		15		V/μs
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
	DC Gain			1		V/V
CMRR	Common Mode Rejection Ratio			40		dB
	Input Offset	FBR=1.100V to1.850V;	-12		12	mV
		FBG=GND

3/27

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L6917

ELECTRICAL CHARACTERISTICS (continued)(VCC = 12V, Tamb = 25°C unless otherwise specified)

Symbol	Parameter	Test Condition	Min	Typ	Max	Unit
SR	Slew Rate	VSEN=10pF		15		V/μs
DIFFERENTIAL CURRENT SENSING
IISEN1,	Bias Current	Iload=0	45	50	55	μA
IISEN2
IPGNDSx	Bias Current		45	50	55	μA
IISEN1,	Bias Current at	Positive	80	85	90	μA
IISEN2	Over Current Threshold	Negative		37.5		μA
IFB	Active Droop Current	Iload<0%		0	1	μA
		Iload=100%	47.5	50	52.5	μA
GATE DRIVERS
tRISE	High Side	VBOOTx-VPHASEx=10V;		15	30	ns
HGATE	Rise Time	CHGATEx to PHASEx=3.3nF
IHGATEx	High Side	VBOOTx-VPHASEx=10V		2		A
	Source Current
RHGATEx	High Side	VBOOTx-VPHASEx=12V;	1.5	2	2.5	Ω
	Sink Resistance
tRISE	Low Side	VCCDR=10V;		30	55	ns
LGATE	Rise Time	CLGATEx to PGNDx=5.6nF
ILGATEx	Low Side	VCCDR=10V		1.8		A
	Source Current
RLGATEx	Low Side	VCCDR=12V	0.7	1.1	1.5	Ω
	Sink Resistance
PROTECTIONS
PGOOD	Upper Threshold	VSEN Rising	109	112	115	%
	(VSEN/DACOUT)
PGOOD	Lower Threshold	VSEN Falling	84	88	92	%
	(VSEN/DACOUT)
OVP	Over Voltage Threshold	VSEN Rising	2.0	2.1	2.2	V
	(VSEN)
UVP	Under Voltage Trip	VSEN Falling	76	80	84	%
	(VSEN/DACOUT)
VPGOOD	PGOOD Voltage Low	IPGOOD = -4mA	0.3	0.4	0.5	V
FAULT	Fault Condition	After OVP or 3 HICCUP cycles	4.75	5.0	5.25	V

4/27

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L6917

Table 1. VID Settings

VID4	VID3	VID2	VID1	VID0	Outpu t Voltage (V)
1	1	1	1	1	OUTPUT OFF
1	1	1	1	0	1.100
1	1	1	0	1	1.125
1	1	1	0	0	1.150
1	1	0	1	1	1.175
1	1	0	1	0	1.200
1	1	0	0	1	1.225
1	1	0	0	0	1.250
1	0	1	1	1	1.275
1	0	1	1	0	1.300
1	0	1	0	1	1.325
1	0	1	0	0	1.350
1	0	0	1	1	1.375
1	0	0	1	0	1.400
1	0	0	0	1	1.425
1	0	0	0	0	1.450
0	1	1	1	1	1.475
0	1	1	1	0	1.500
0	1	1	0	1	1.525
0	1	1	0	0	1.550
0	1	0	1	1	1.575
0	1	0	1	0	1.600
0	1	0	0	1	1.625
0	1	0	0	0	1.650
0	0	1	1	1	1.675
0	0	1	1	0	1.700
0	0	1	0	1	1.725
0	0	1	0	0	1.750
0	0	0	1	1	1.775
0	0	0	1	0	1.800
0	0	0	0	1	1.825
0	0	0	0	0	1.850

5/27

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L6917

PIN FUNCTION

N	Name	Description
1	LGATE1	Channel 1 low side gate driver output.
2	VCCDR	Mosfet driver supply. It can be varied from 5V to 12V Bus.
3	PHASE1	This pin is connected to the source of the upper mosfet and provides the return path for the high
		side driver of channel 1.
4	UGATE1	Channel 1 high side gate driver output.
5	BOOT1	Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
		mosfet. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs.
		boot).
6	VCC	Device supply voltage. The operative supply voltage is 12V.
7	GND	All the internal references are referred to this pin. Connect it to the PCB signal ground.
8	COMP	This pin is connected to the error amplifier output and is used to compensate the control
		feedback loop.
9	FB	This pin is connected to the error amplifier inverting input and is used to compensate the voltage
		control feedback loop.
		A current proportional to the sum of the current sensed in both channel is sourced from this pin
		(50μA at full load, 70μA at the Over Current threshold). Connecting a resistor between this pin
		and VSEN pin allows programming the droop effect.
10	VSEN	Connected to the output voltage it is able to manage Over & Under-voltage conditions and the
		PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote
		Sense of the regulated voltage.
		If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
		manage OVP, UVP and PGOOD.
11	FBR	Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to
		perform a remote sense.
		If no remote sense is implemented, connect directly to the output voltage (in this case connect
		also the VSEN pin directly to the output regulated voltage).
12	FBG	Remote sense buffer inverting input. It has to be connected to the negative side of the load to
		perform a remote sense.
		Pull-down to ground if no remote sense is implemented.
13	ISEN1	Channel 1 current sense pin. The output current may be sensed across a sense resistor or
		across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or
		to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
		as follow:
		35μ A Rg
		IMAX_POS1 = --------------------------
		Rsense
		Where 35μA is the current offset information relative to the Over Current condition (offset at OC
		threshold minus offset at zero load).
		In the same way the negative current limit threshold results to be set at ±50% as follow:
		±12.5 μA Rg
		IMAX_NEG1 = ----------------------------------
		Rse nse
		Where ±12.5μA is the current offset information relative to the Negative Over Current condition
		(offset at Negative OC threshold minus offset at zero load).
		The net connecting the pin to the sense point must be routed as close as possible to the
		PGNDS1 net in order to couple in common mode any picked-up noise.
14	PGNDS1	Channel 1 Power Ground sense pin. The net connecting the pin to the sense point (Through a
		resistor Rg) must be routed as close as possible to the ISEN1 net in order to couple in common

mode any picked-up noise.

6/27

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		L6917
PIN FUNCTION (continued)
N	Name	Description
15	PGNDS2	Channel 2 Power Ground sense pin. The net connecting the pin to the sense (Through a resistor
		Rg) point must be routed as close as possible to the ISEN2 net in order to couple in common
		mode any picked-up noise.
16	ISEN2	Channel 2 current sense pin. The output current may be sensed across a sense resistor or
		across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or
		to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
		as follow:
		35μ A Rg
		IMAX_POS2 = --------------------------
		Rsense
		Where 35μA is the current offset information relative to the Over Current condition (offset at OC
		threshold minus offset at zero load).
		In the same way the negative current limit threshold results to be set at ±50% as follow
		±12.5 μA Rg
		IMAX_NEG2 = ----------------------------------
		Rse nse
		Where ±12.5μA is the current offset information relative to the Negative Over Current condition
		(offset at Negative OC threshold minus offset at zero load).
		The net connecting the pin to the sense point must be routed as close as possible to the
		PGNDS2 net in order to couple in common mode any picked-up noise.
17	OSC/INH	Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
	FAULT	external frequency is increased according to the equation:
		14.82 106
		fS = 300KHz + -----------------------------
		ROSC (KΩ)
		Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
		the equation:
		12.91 107
		fS = 300KHz + -----------------------------
		ROSC (KΩ)
		If the pin is not connected, the switching frequency is 300KHz.
		Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state.
		The pin is forced high when an over voltage is detected and after three hiccup cycles. This
		condition is latched; to recover it is necessary turn off and on VCC.
18-22	VID4-0	Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are
		used to program the output voltage as specified in Table 1 and to set the power good thresholds.
		Connect to GND to program a `0' while leave floating to program a `1'.
23	PGOOD	This pin is an open collector output and is pulled low if the output voltage is not within the above
		specified thresholds.
		If not used may be left floating.
24	BOOT2	Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
		mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs.
		boot).
25	UGATE2	Channel 2 high side gate driver output.
26	PHASE2	This pin is connected to the source of the upper mosfet and provides the return path for the high
		side driver of channel 2.
27	LGATE2	Channel 2 low side gate driver output.
28	PGND	Power ground pin. This pin is common to both sections and it must be connected through the
		closest path to the low side mosfets source pins in order to reduce the noise injection into the
		device.
		7/27

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L6917

Device Description

The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance multiphase step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 1.100V to 1.850V with 25mV binary steps, with a maximum tolerance of ±0.8% over temperature and line voltage variations. The device provides an average current-mode control with fast transient response.

It includes a 300kHz free-running oscillato r externally adjustable up to 1MHz. The error amplifier features a 15V/μs slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets rDSON or across a sense resistor in fully differential mode. The current information corrects the PWM output in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions. The device protects against over-current, with an OC threshold for each phase, entering in HICCUP mode. After three hiccup cycles, the condition is latched and the FAULT pin is driven high. The device performs also an under voltage protection that causes a hiccup cycle when detected, and an over voltage protection that disable immediately the device turning ON the lower driver and driving high the FAULT pin.

The device is available in SO28 package.

Oscillator

The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 25μA (FSW = 300KHz) and may be varied using an external resistor (ROSC) connected between OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ). 1.235V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/μA.

In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:

R

v s. GND: f

=

300kHz +

1.237

12

kHz

= 300kHz +

14.82

106

R-----OS--------C----(--K-----Ω------)

--μ----A----

R-----OS--------C-----(-K-----Ω------)

OS C

S

R

v s. 12V: f

=

300kHz +

12 ± 1.237

12

kHz

= 300k Hz ±

12.918

107

R-----OS--------C----(--K-----Ω------)

--μ----A----

--

R----O----S----C----(---K----Ω-----)--

OS C

S

Note that forcing a 25μA current into this pin, the device stops switching because no current is delivered to the oscillator.

Figure 1. ROSC vs. Switching Frequency

Rosc(KΩ) vs. 12V

7000

6000

5000

4000

3000

2000

1000

0

0

100

200

300

Rosc(KΩ) vs. GND

1000

900

800

700

600

500

400

300

200

100

0

300 400 500 600 700 800 900 1000

Frequency (KHz)

Frequency (KHz)

8/27

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L6917

Digital to Analog Converter

The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with 25mV steps as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 0.8% and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5μA current generator up to 3.3V max); in this way, to program a logic º1º it is enough to leave the pin floating, while to program a logic º0º it is enough to short the pin to GND.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the overvoltage protection (OVP) thresholds.

Soft Start and INHIBIT

At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in 2048 clock periods as shown in figure 2.

Before soft start, the lower power MOS are turned ON after that VCCDRreaches 2V (independently by Vcc value) to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start begins, the reference is increased; when it reaches the bottom of the oscillator triangular waveform (1V typ) also the upper MOS begins to switch and the output voltage starts to increase with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig. 2). The Negative Current Limit comparators and Under Voltage comparator are enabled when the reference voltage reaches 0.8V.

The Soft-Start will not take place, if both Vcc and VCCDR pins are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.

Forcing the OSC/INH/FAULT pin to a voltage lower than 0.8V the device enter in INHIBIT mode: all the power mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT pin reaches the band-gap voltage and the soft start begins.

Figure 2. Soft Start

VIN=VCCDR

Turn ON threshold

2V

VLGATEx

VOUT

PGOOD

2048 Clock Cycles

t

t

t

t

Timing Diagram	Acquisiti on:
	CH1 = PGOOD; CH2 = VOUT; CH4 = LGATEx

9/27

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