ST L6917 User Manual
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5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
■
2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL
■ ULTRA FAST LOAD TRANSIENT RESPONSE
■
INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
■
TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 9.0
■
0.8% INTERNAL REFERENCE ACCURACY
■
10% ACTIVE CURRENT SHARING
ACCURACY
■ DIGITAL 2048 STEP SOFT-START
■
OVERVOLTAGE PROTECTION
■
OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET’S R
SENSE RESISTOR
■
300 kHz INTERNAL OSCILLATOR
■
OSCILLATOR EXTERNALLY ADJUSTABLE
UP TO 1MHz
■ POWER GOOD OUTPUT AND INHIBIT
FUNCTION
■
REMOTE SENSE BUFFER
■ PACKAGE: SO-28
APPLICATIONS
■ POWER SUPPLY FOR SERVER AND
WORKSTATION
■
POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS
■
DISTRIBUTED POWER SUPPLY
dsON
ORA
L6917
SO-28
ORDERING NUMBERS: L6917D
L6917DTR (Tape & Reel)
DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC conversion for high current microprocessors.
The device implementsa dual-phase step-down controller with a 180° phase-shift between each phase.
A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 1.100V to
1.850V with 25mV binary steps.
The high precision internal reference assures the se-
lected output voltage to be within ±0.8%. The high
peak current gate drive affords to have fast switching
to the external power mos providing low switching
losses.
The device assures a fast protection against load
over current and load over/under voltage. An internal
crowbar is provided turning on the low side mosfet if
an over-voltage is detected. In case of over-current
or under voltage, the system worksin HICCUP mode.
BLOCK DIAGRAM
October 2001
PGOOD
VID4
VID3
VID2
VID1
VID0
FBG
FBR
DIGITAL
SOFT START
DAC
10k
10k
10k
10k
REMOTE
BUFFER
ROSC /INH SGND VCCDR
2 PHASE
OSCILLATOR
LOGIC
AND
PROTECTIONS
CH1OV ER
CURR ENT
IFB
CH2 OVER
CURRENT
VCC
VCCDR
ERROR
AMPLIFIER
PWM1
-
+
CH 1 OVER
CURRENT
CURR ENT
CORRECTION
TOTAL
+
CURRENT
AVG
CURRENT
<>
CH 2 OVER
CURR ENT
CURRENT
CORRECTION
+
-
PWM2
VccCOMPFBVSEN
Vcc
LOGIC PWM
ADAPTIVE ANTI
CROSS-CONDUCTION
CURRENT
READING
CURRENT
READING
LOGIC PWM
ADAPTIVE ANTI
CROSS-CONDUCTION
BOOT1
HS
LS
LS
HS
UGATE1
PHASE1
LGATE1
ISEN1
PGNDS1
PGND
PGNDS2
ISEN2
LGATE2
PHASE2
UGATE2
BOOT2
1/27
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L6917
ABSOLUTEMAXIMUM RATINGS
Symbol Parameter Value Unit
Vcc, V
CCDR
V
BOOT-VPHASE
V
UGATE1-VPHASE1
V
UGATE2-VPHASE2
ToPGND 15 V
Boot Voltage 15 V
15 V
LGATE1, PHASE1, LGATE2,PHASE2 to PGND -0.3 to Vcc+0.3 V
All other pins to PGND -0.3 to 7 V
THERMAL DATA
Symbol Parameter Value Unit
R
th j-amb
T
T
storage
P
Thermal Resistance Junction to Ambient 60
Maximum junction temperature 150
max
Storage temperature range -40 to 150
T
Junction Temperature Range -25 to 125 °C
j
Max power dissipation at T
MAX
=25°C2W
amb
°
PIN CONNECTION
C/W
C
°
C
°
LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
GND
COMP
FB
FBR
FBG
ISEN1
PGNDS1
2
3
4
5
6
7
8
9
10VSEN
11
12
13
14
SO28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGND1
LGATE2
PHASE2
UGATE2
BOOT2
PGOOD
VID4
VID3
VID2
VID1
VID0
OSC/INH/FAULT
ISEN2
PGNDS2
2/27
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L6917
ELECTRICAL CHARACTERISTICS
(VCC= 12V, T
=25°C unless otherwise specified)
amb
Symbol Parameter Test Condition Min Typ Max Unit
Vcc SUPPLYCURRENT
I
CC
I
CCDR
I
BOOTx
Vcc supply current HGATEx and LGATExopen
V
supply current LGATEx open; V
CCDR
V
CCDR=VBOOT
=12V
=12V 2 3 4 mA
CCDR
Boot supply current HGATExopen; PHASEx to PGND
V
CC=VBOOT
=12V
6810mA
0.5 1 1.5 mA
POWER-ON
Turn-On V
Turn-Off V
Turn-On V
Threshold
Turn-Off V
Threshold
threshold VCCRising; V
CC
threshold VCCFalling; V
CC
CCDR
CCDR
V
CCDR
V
CC
V
CCDR
V
CC
=12V
=12V
Rising
Falling
=5V 7.8 9 10.2 V
CCDR
=5V 6.5 7.5 8.5 V
CCDR
4.2 4.4 4.6 V
4.0 4.2 4.4 V
OSCILLATORAND INHIBIT
f
OSC
Initial Accuracy OSC = OPEN
OSC = OPEN; Tj=0°Cto125°C
278
270
300 322
330
kHz
kHz
f
OSC,Ros
INH Inhibit threshold I
d
MAX
TotalAccuracy RTto GND=74kΩ 450 500 550 kHz
c
=5mA 0.8 0.85 0.9 V
SINK
Maximum duty cycle OSC = OPEN 80 85 %
∆Vosc Ramp Amplitude 1.8 2 2.2 V
REFERENCE AND DAC
I
DAC
Output Voltage
Accuracy
VID pull-up Current VIDx = GND 4 5 6
VID0, VID1, VID2, VID3, VID4
see Table1; Tamb=0°to 70°;
FBR= V
; FBG = GND
OUT
-0.8 - 0.8 %
VID pull-up Voltage VIDx = OPEN 3.1 - 3.4 V
ERROR AMPLIFIER
DC Gain 80 dB
SR Slew-Rate COMP=10pF 15 V/µs
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
DC Gain 1 V/V
CMRR Common Mode Rejection Ratio 40 dB
A
µ
Input Offset FBR=1.100V to1.850V;
FBG=GND
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-12 12 mV
3/27
L6917
ELECTRICAL CHARACTERISTICS
(continued)(VCC= 12V, T
=25°C unless otherwise specified)
amb
Symbol Parameter Test Condition Min Typ Max Unit
SR Slew Rate VSEN=10pF 15 V/µs
DIFFERENTIAL CURRENT SENSING
,
I
ISEN1
I
ISEN2
I
PGNDSx
I
ISEN1
I
ISEN2
I
Bias Current Iload=0 45 50 55 µA
Bias Current 45 50 55 µA
,
Bias Current at
Over Current Threshold
Active Droop Current Iload<0%
FB
Positive
80 85
Negative
Iload=100% 47.5
37.5
0
50
90 µA
1
52.5
GATE DRIVERS
t
RISE
HGATE
I
HGATEx
High Side
Rise Time
High Side
V
BOOTx-VPHASEx
C
V
to PHASEx=3.3nF
HGATEx
BOOTx-VPHASEx
=10V;
=10V 2 A
15 30 ns
Source Current
R
HGATEx
High Side
V
BOOTx-VPHASEx
=12V; 1.5 2 2.5 Ω
Sink Resistance
t
RISE
LGATE
Low Side
Rise Time
V
CCDR
C
LGATEx
=10V;
to PGNDx=5.6nF
30 55 ns
µA
µA
µA
I
LGATEx
Low Side
V
=10V 1.8 A
CCDR
Source Current
R
LGATEx
Low Side
V
=12V 0.7 1.1 1.5 Ω
CCDR
Sink Resistance
PROTECTIONS
Rising 109 112 115 %
PGOOD Upper Threshold
/DACOUT)
(V
SEN
PGOOD Lower Threshold
/DACOUT)
(V
SEN
OVP Over Voltage Threshold
)
(V
SEN
UVP Under VoltageTrip
/DACOUT)
(V
SEN
V
PGOOD
PGOOD Voltage Low I
V
SEN
Falling 84 88 92 %
V
SEN
Rising 2.0 2.1 2.2 V
V
SEN
Falling 76 80 84 %
V
SEN
= -4mA 0.3 0.4 0.5 V
PGOOD
FAULT FaultCondition After OVP or 3 HICCUP cycles 4.75 5.0 5.25 V
4/27
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Table 1. VID Settings
VID4 VID3 VID2 VID1 VID0 Output Voltage (V)
11111OUTPUT OFF
11110 1.100
11101 1.125
11100 1.150
11011 1.175
11010 1.200
11001 1.225
11000 1.250
10111 1.275
10110 1.300
10101 1.325
10100 1.350
10011 1.375
L6917
10010 1.400
10001 1.425
10000 1.450
01111 1.475
01110 1.500
01101 1.525
01100 1.550
01011 1.575
01010 1.600
01001 1.625
01000 1.650
00111 1.675
00110 1.700
00101 1.725
00100 1.750
00011 1.775
00010 1.800
00001 1.825
00000 1.850
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5/27
L6917
PIN FUNCTION
N Name Description
1 LGATE1 Channel 1 low side gate driver output.
2 VCCDR Mosfet driver supply.It can be varied from 5V to 12V Bus.
3 PHASE1 This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 1.
4 UGATE1 Channel 1 high side gate driver output.
5 BOOT1 Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE1 pin and througha diode to Vcc (cathode vs.
boot).
6 VCC Device supply voltage. The operative supply voltage is 12V.
7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
8 COMP This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
9 FB This pin is connected to theerror amplifier inverting input and is used to compensate the voltage
control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50µA at full load, 70µA at the Over Current threshold). Connecting a resistor between this pin
and VSEN pin allows programming the droop effect.
10 VSEN Connected to the output voltage it is able to manage Over & Under-voltage conditions and the
11 FBR Remote sense buffernon-inverting input. It has to be connected to the positive side of the load to
12 FBG Remote sense buffer inverting input. It has to be connected to the negative side of the load to
13 ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or
PGOOD signal. It is internally connected with the output of the Remote Sense Buffer forRemote
Sense of the regulated voltage.
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
manage OVP,UVP and PGOOD.
perform a remote sense.
If no remote sense is implemented, connect directly to the output voltage (in this case connect
also the VSEN pin directly to the output regulated voltage).
perform a remote sense.
Pull-down to ground if no remote sense is implemented.
across the low-side mosfet Rds
This pin has to be connected to the low-side mosfet drain or
ON.
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
I
MAX_POS1
35µARg⋅
--------------------------=
R
sense
6/27
14
Where 35µA is the current offset information relative to the Over Current condition (offset at OC
threshold minus offset at zero load).
In the same way the negative current limit threshold results to be set at –50% as follow:
I
MAX_NEG1
12.5– µARg⋅
---------------------------------- -=
R
se ns e
Where –12.5µA is the current offset information relative to the Negative Over Current condition
(offset at Negative OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS1 net in order to couple in common mode any picked-up noise.
PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point (Through a
resistor R
) must be routed as close as possible to the ISEN1 net in order to couple in common
g
mode any picked-up noise.
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L6917
PIN FUNCTION
(continued)
N Name Description
15 PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense (Through a resistor
R
) point must be routed as close as possible to the ISEN2 net in order to couple in common
g
mode any picked-up noise.
16 ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds
This pin has to be connected to the low-side mosfet drain or
ON.
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
I
MAX_POS2
35µARg⋅
--------------------------=
R
sense
Where 35µA is the current offset information relative to the Over Current condition (offset at OC
threshold minus offset at zero load).
In the same way the negative current limit threshold results to be set at –50% as follow
I
MAX_NEG2
12.5µ– ARg⋅
---------------------------------- -=
R
se ns e
Where –12.5µA is the current offset information relative to the Negative Over Current condition
(offset at Negative OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
17
OSC/INH
FAULT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND,the
external frequency is increased according to the equation:
6
⋅
14.82 10
f
S
300KH z
-----------------------------+=
R
OSC
KΩ()
Connecting a resistor from this pin to Vcc (12V),the switching frequency is reduced according to
the equation:
7
⋅
12.91 10
f
S
300KH z
-----------------------------+=
R
OSC
KΩ()
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state.
The pin is forced high when an over voltage is detected and after three hiccup cycles. This
condition is latched; to recover it is necessary turn off and on VCC.
18-22 VID4-0 Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
23 PGOOD This pin is an open collector output and is pulled low if theoutput voltage is not within the above
specified thresholds.
If not used may be left floating.
24 BOOT2 Channel 2 bootstrap capacitor pin. Through this pin is supplied thehigh side driver and the upper
mosfet. Connect through a capacitor to the PHASE2 pin and througha diode to Vcc (cathode vs.
boot).
25 UGATE2 Channel 2 high side gate driver output.
26 PHASE2 This pin is connected to the source of the upper mosfet and provides the return path forthe high
side driver of channel 2.
27 LGATE2 Channel 2 low side gate driver output.
28 PGND Power ground pin. This pin is common to both sections and it must be connected through the
closest path to the low side mosfets source pins in order to reduce the noise injection into the
device.
7/27
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L6917
DeviceDescription
The device is an integrated circuitrealized in BCD technology. It provides complete control logic and protections
for a high performance multiphase step-down DC-DC converter optimized for microprocessor power supply. It
is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg
phase shift is provided between the two phases allowing reduction inthe input capacitor current ripple, reducing
also the size and the losses. The output voltage of the converter can be precisely regulated, programming the
VID pins, from 1.100V to1.850V with 25mV binary steps, with amaximum tolerance of ±0.8% over temperature
and line voltage variations. The device provides an average current-mode control with fast transient response.
It includes a 300kHz free-running oscillator externally adjustable up to 1MHz. The error amplifier features a 15V/µs
slew rate that permits high converter bandwidth for fast transient performances. Current information is read
across the lower mosfets rDSON or across a sense resistor in fully differential mode. The current information
corrects the PWM output in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions. The device protects against
over-current, with an OC threshold for each phase, entering in HICCUP mode. After three hiccup cycles, the
condition is latched and the FAULT pin is driven high. Thedevice performs also an under voltage protection that
causes a hiccupcycle when detected, and anover voltage protectionthat disable immediately the device turning
ON the lower driver and driving high the FAULT pin.
The device is available in SO28 package.
Oscillator
The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internalcapacitor. The current delivered to the
oscillator is typically 25
tween OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ). 1.235V, the frequency
is varied proportionally tothe current sunk (forced) from (into) thepin considering the internal gainof 12KHz/
In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting
ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:
µA(F
= 300KHz) and maybe varied using an external resistor (R
SW
) connected be-
OSC
µ
A.
R
vs. GND: fS300kHz
OSC
R
OSC
Note that forcing a 25
oscillator.
Figure 1. R
Rosc(KΩ) vs. 12V
vs. Switching Frequency
OSC
7000
6000
5000
4000
3000
2000
1000
0
0 100 200 300
vs. 12V: f
S
300kHz
1.237
----------------------- -------
R
OSC
12 1.237–
------------------------ ------ 12
+
R
OSC
Ω()
K
KΩ()
kHz
-----------⋅+
12
µ
kHz
-----------
⋅
µA
A
300kHz
300kHz
14.82 106⋅
------------------------------+==
R
12.918 107⋅
----------------------- ---------–==
R
OSC
OSC
KΩ()
KΩ()
µA current into this pin, the device stops switching because no current is delivered to the
1000
900
800
700
600
500
400
300
200
Rosc(KΩ) vs. GND
100
0
300 400 500 600 700 800 900 1000
Frequency (KHz)
Frequency(KHz)
8/27
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L6917
Digitalto AnalogConverter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with
25mV steps as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 0.8%
and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is
realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code
drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an
amplifier obtaining the V
provided (realized with a 5
to leave the pin floating, while to program a logic ”0” it is enough to short the pin to GND.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the overvoltage protection (OVP) thresholds.
SoftStart and INHIBIT
At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in
2048 clock periods as shown in figure 2.
Before soft start,the lower power MOS are turned ONafter that V
to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start begins,
the reference is increased; when it reaches the bottom of the oscillator triangular waveform (1V typ) also the
upper MOS begins to switch and the output voltage starts to increase with closed loop regulation. At the end of
the digital soft start, thePower Good comparator is enabled and the PGOOD signal is then driven high (See fig.
2). The Negative Current Limit comparators and Under Voltage comparator are enabled when the reference
voltage reaches 0.8V.
The Soft-Start will not take place, if both Vcc and VCCDR pins are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.
Forcing the OSC/INH/FAULT pin to a voltage lower than 0.8V the device enter in INHIBIT mode: all the power
mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT pin reaches
the band-gap voltage and the soft start begins.
voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are
PROG
µA current generator up to 3.3V max); in this way, to program a logic ”1” it is enough
reaches 2V (independently by Vcc value)
CCDR
Figure 2. Soft Start
VIN=V
CCDR
V
LGATEx
V
OUT
PGOOD
Turn ON threshold
2V
t
t
t
2048 ClockCycles
Timing Diagram Acquisition:
t
CH1 = PGOOD; CH2 = V
; CH4 = LGATEx
OUT
9/27
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