L6910
L6910
L6910A
ADJUSTABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
FEATURE
■OPERATING SUPPLY VOLTAGE FROM 5V TO 12V BUSES
■UP TO 1.3A GATE CURRENT CAPABILITY
■ADJUSTABLE OUTPUT VOLTAGE
■N-INVERTING E/A INPUT AVAILABLE
■0.9V ±1.5% VOLTAGE REFERENCE
■VOLTAGE MODE PWM CONTROL
■VERY FAST LOAD TRANSIENT RESPONSE
■0% TO 100% DUTY CYCLE
■POWER GOOD OUTPUT
■OVERVOLTAGE PROTECTION
■HICCUP OVERCURRENT PROTECTION
■200kHz INTERNAL OSCILLATOR
■OSCILLATOR EXTERNALLY ADJUSTABLE FROM 50kHz TO 1MHz
■SOFT START AND INHIBIT
■PACKAGES: SO-16 & HTSSOP16
APPLICATIONS
■SUPPLY FOR MEMORIES AND TERMINATIONS
■COMPUTER ADD-ON CARDS
■LOW VOLTAGE DISTRIBUTED DC-DC
■MAG-AMP REPLACEMENT
BLOCK DIAGRAM
SO-16 (Narrow) |
HTSSOP16 (Exposed Pad) |
ORDERING NUMBERS: |
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L6910 (SO-16) |
L6910A (HTSSOP16) |
L6910TR (Tape & Reel) L6910ATR (Tape & Reel)
DESCRIPTION
The device is a pwm controller for high performance dc-dc conversion from 3.3V, 5V and 12V buses.
The output voltage is adjustable down to 0.9V; higher voltages can be obtained with an external voltage divider.
High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A.
The device assures protections against load overcurrent and overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in HICCUP mode.
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Vin 5V to12V |
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PGOOD |
VCC |
OCSET |
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BOOT |
VREF |
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Monitor |
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SS |
Protection and Ref |
UGATE |
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OSC |
OSC |
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PHASE |
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L6910 |
Vo |
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RT |
LGATE |
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- |
PGND |
EAREF |
E/A |
+ |
PWM |
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- |
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GND |
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300k |
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VFB |
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COMP |
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July 2003 |
1/21 |
L6910A L6910
ABSOLUTE MAXIMUM RATINGS
Symbol |
Parameter |
Value |
Unit |
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Vcc |
Vcc to GND, PGND |
15 |
V |
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VBOOT- |
Boot Voltage |
15 |
V |
VPHASE |
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VHGATE- |
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15 |
V |
VPHASE |
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OCSET, LGATE, PHASE |
-0.3 to Vcc+0.3 |
V |
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SS, FB, PGOOD, VREF, EAREF, RT |
7 |
V |
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COMP |
6.5 |
V |
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Tj |
Junction Temperature Range |
-40 to 150 |
°C |
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Tstg |
Storage temperature range |
-40 to 150 |
°C |
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Ptot |
Maximum power dissipation at Tamb = 25°C |
1 |
W |
THERMAL DATA
Symbol |
Parameter |
SO-16 |
HTSSOP16 |
HTSSOP16 (*) |
Unit |
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Rth j-amb |
Thermal Resistance Junction to Ambient |
120 |
110 |
50 |
°C/W |
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(*) Device soldered on 1 S2P PC board
PINS CONNECTION (Top view)
VREF |
1 |
16 |
N.C. |
VREF |
1 |
16 |
VCC |
OSC |
2 |
15 |
VCC |
OSC |
2 |
15 |
LGATE |
OCSET |
3 |
14 |
LGATE |
OCSET |
3 |
14 |
PGND |
SS/INH |
4 |
13 |
PGND |
SS/INH |
4 |
13 |
BOOT |
COMP |
5 |
12 |
BOOT |
N.C. |
5 |
12 |
HGATE |
FB |
6 |
11 |
HGATE |
COMP |
6 |
11 |
PHASE |
GND |
7 |
10 |
PHASE |
FB |
7 |
10 |
PGOOD |
EAREF |
8 |
9 |
PGOOD |
GND |
8 |
9 |
EAREF |
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SO16 |
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HTSSOP-16 |
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2/21
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L6910A L6910 |
PINS FUNCTION |
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SO |
HTSSOP |
Name |
Description |
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1 |
1 |
VREF |
Internal 0.9V ±1.5% reference is available for external regulators or for the internal error |
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amplifier (connecting this pin to EAREF) if external reference is not available. |
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A minimum 1nF capacitor is required. |
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If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode. |
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2 |
2 |
OSC |
Oscillator switching frequency pin. Connecting an external resistor (RT) from this pin to |
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GND, the external frequency is increased according to the equation: |
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4.94 × 106 |
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fO SC,RT = 200KHz + ------------------------ |
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RT (KW) |
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Connecting a resistor (RT) from this pin to Vcc (12V), the switching frequency is reduced |
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according to the equation: |
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4.306 × 107 |
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fO SC,RT = 200KHz – ---------------------------- |
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RT(KW) |
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If the pin is not connected, the switching frequency is 200KHz. |
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The voltage at this pin is fixed at 1.23V. Forcing a 50mA current into this pin, the built in |
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oscillator stops to switch. |
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In Over Voltage condition this pin goes over 3V until that conditon is removed. |
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3 |
3 |
OCSET |
A resistor connected from this pin and the upper Mos Drain sets the current limit |
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protection. |
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The internal 200mA current generator sinks a constant current through the external |
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resistor. The Over-Current threshold is due to the following equation: |
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IOCSE T × RO CS ET |
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IP = --------------------------------------------- |
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RDS on |
4 |
4 |
SS/INH |
The soft start time is programmed connecting an external capacitor from this pin and |
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GND. The internal current generator forces through the capacitor 10mA. |
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This pin can be used to disable the device forcing a voltage lower than 0.4V |
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5 |
6 |
COMP |
This pin is connected to the error amplifier output and is used to compensate the voltage |
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control feedback loop. |
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6 |
7 |
FB |
This pin is connected to the error amplifier inverting input and is used to compensate the |
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voltage control feedback loop. |
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Connected to the output resistor divider, if used, or directly to Vout, it manages also over- |
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voltage conditions and the PGOOD signal |
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7 |
8 |
GND |
All the internal references are referred to this pin. Connect it to the PCB signal ground. |
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8 |
9 |
EAREF |
Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to |
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3V) for the PWM regulation or short it to VREF pin to use the internal reference. |
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If this pin goes under 650mV (typ), the device shuts down. |
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9 |
10 |
PGOOD |
This pin is an open collector output and it is pulled low if the output voltage is not within the |
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above specified thresholds. If not used it may be left floating. |
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10 |
11 |
PHASE |
This pin is connected to the source of the upper mosfet and provides the return path for the |
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high side driver. This pin monitors the drop across the upper mosfet for the current limit |
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together with OCSET. |
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11 |
12 |
HGATE |
High side gate driver output. |
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12 |
13 |
BOOT |
Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper |
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mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc |
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(cathode vs. boot). |
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13 |
14 |
PGND |
Power ground pin. This pin has to be connected closely to the low side mosfet source in |
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order to reduce the noise injection into the device |
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14 |
‘5 |
LGATE |
This pin is the lower mosfet gate driver output |
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15 |
16 |
VCC |
Device supply voltage. The operative supply voltage ranges is from 5V to 12V. |
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DO NOT CONNECT VIN TO A VOLTAGE GREATER THAN VCC. |
16 |
5 |
N.C. |
This pin is not internally bonded. It may be left floating or connected to GND. |
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3/21 |
L6910A L6910
ELECTRICAL CHARACTERISTICS (Vcc = 12V, TJ =25°C unless otherwise specified)
Symbol |
Parameter |
Test Condition |
Min |
Typ |
Max |
Unit |
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Vcc SUPPLY CURRENT |
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Icc |
Vcc Supply current |
OSC = open; SS to GND |
4 |
7 |
9 |
mA |
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POWER-ON |
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Turn-On Vcc threshold |
VOCSET = 4V |
4.0 |
4.3 |
4.6 |
V |
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Turn-Off Vcc threshold |
VOCSET = 4V |
3.8 |
4.1 |
4.4 |
V |
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Rising VOCSET threshold |
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1.24 |
1.4 |
V |
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Turn On EAREF threshold |
VOCSET = 4V |
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650 |
750 |
mV |
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SOFT START AND INHIBIT |
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Iss |
Soft start Current |
SS = 2V |
6 |
10 |
14 |
μA |
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S.S. current in INH condition |
SS = 0 to 0.4V |
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35 |
60 |
μA |
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OSCILLATOR |
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fOSC |
Initial Accuracy |
OSC = OPEN |
180 |
200 |
220 |
KHz |
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OSC = OPEN; Tj = 0° to 125° |
170 |
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230 |
kHz |
fOSC,RT |
Total Accuracy |
16 KΩ < RT to GND < 200 KΩ |
-15 |
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15 |
% |
Vosc |
Ramp amplitude |
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1.9 |
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V |
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REFERENCE |
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VOUT |
Output Voltage Accuracy |
VOUT = VFB; VEAREF = VREF |
0.886 |
0.900 |
0.913 |
V |
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VREF |
Reference Voltage |
CREF = 1nF; IREF = 0 to 100μA |
0.886 |
0.900 |
0.913 |
V |
VREF |
Reference Voltage |
CREF = 1nF; TJ = 0 to 125°C |
-2 |
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+2 |
% |
ERROR AMPLIFIER |
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IEAREF |
N.I. bias current |
VEAREF = 3V |
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10 |
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μA |
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EAREF Input Resistance |
Vs. GND |
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300 |
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kΩ |
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IFB |
I.I. bias current |
VFB = 0V to 3V |
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0.01 |
0.5 |
μA |
VCM |
Common Mode Voltage |
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0.8 |
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3 |
V |
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VCOMP |
Output Voltage |
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0.5 |
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4 |
V |
GV |
Open Loop Voltage Gain |
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70 |
85 |
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dB |
GBWP |
Gain-Bandwidth Product |
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10 |
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MHz |
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SR |
Slew-Rate |
COMP = 10pF |
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10 |
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V/μs |
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GATE DRIVERS |
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IHGATE |
High Side |
VBOOT - VPHASE = 12V |
1 |
1.3 |
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A |
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Source Current |
VHGATE - VPHASE = 6V |
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RHGATE |
High Side |
VBOOT - VPHASE = 12V |
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2 |
4 |
Ω |
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Sink Resistance |
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ILGATE |
Low Side Source Current |
Vcc = 12V; VLGATE = 6V |
0.9 |
1.1 |
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A |
RLGATE |
Low Side Sink Resistance |
Vcc = 12V |
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1.5 |
3 |
Ω |
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Output Driver Dead Time |
PHASE connected to GND |
90 |
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210 |
ns |
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PROTECTIONS |
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IOCSET |
OCSET Current Source |
VOCSET = 4V |
170 |
200 |
230 |
μA |
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Over Voltage Trip (VFB / VEAREF) |
VFB Rising |
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117 |
120 |
% |
IOSC |
OSC Sourcing Current |
VFB > OVP Trip |
15 |
30 |
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mA |
POWER GOOD |
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Upper Threshold (VFB / VEAREF) |
VFB Rising |
108 |
110 |
112 |
% |
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Lower Threshold (VFB / VEAREF) |
VFB Falling |
88 |
90 |
92 |
% |
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Hysteresis (VFB / VEAREF) |
Upper and Lower threshold |
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2 |
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% |
VPGOOD |
PGOOD Voltage Low |
IPGOOD = -4mA |
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0.4 |
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V |
IPGOOD |
Output Leakage Current |
VPGOOD = 6V |
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0.2 |
1 |
μA |
4/21 |
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L6910A L6910
Device Description
The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and protection for a high performance step-down DC-DC converter. It is designed to drive N Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be precisely regulated down to 900mV with a maximum tolerance of ±1.5% when the internal reference is used (simply connecting together EAREF and VREF pins). The device allows also using an external reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V/ms slew rate that permits to realize high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode. The de-
vice monitors the current by using the rDS(ON) of the upper MOSFET(s) that eliminates the need for a current sensing resistor. The device is available in SO16 narrow package.
Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 50mA (Fsw = 200KHz) and may be varied using an external resistor (RT) connected between OSC pin and GND or VCC. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin.
In particular connecting RT vs. GND the frequency is increased (current is sunk from the pin), according to the following relationship:
4.94 × 106 fOSC,RT = 200KHz + -------------------------
RT (KW)
Connecting RT to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according to the following relationships:
fOSC,RT = |
200KHz – |
4.306 × 10 |
7 |
VCC = 12V |
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R-----T---(---K----W-----)--- |
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fOSC,RT |
= 200KHz |
– |
15 |
× 106 |
VCC = 5V |
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R-----T--- |
(---K----W-----)- |
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Switching frequency variation vs. RT are repeated in Fig. 1.
Note that forcing a 50mA current into this pin, the device stops switching because no current is delivered to the oscillator.
Figure 1.
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10000 |
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1000 |
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[kOhm] |
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Resistance |
100 |
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RT to GND |
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10 |
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RT to VCC=12V |
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RT to VCC=5V |
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10 |
100 |
1000 |
Frequency [kHz]
Reference
A precise ±1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid instability in the internal linear regulator. It is able to deliver up to 100mA and may be used as reference for the device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hiccup mode until this condition is removed.
Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-in- verting input of the error amplifier. An external reference (or the internal 0.9V ±1.5%) may be used. The input for this pin can range from 0.9V to 3V. It has an internal pull-down (300kW resistor) that forces the device shutdown if no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is lower than 650mV (typ).
5/21
L6910A L6910
Soft Start
At start-up a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is of 35μA and speeds-up the charge of the capacitor up to 0.5V. After that it becames 10μA until the final charge value of approximatively 4V.
When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase.
No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.
If VCC and OCSET pins are not above their own turn-on thresholds and VEAREF is not above 650mV, the SoftStart will not take place, and the relative pin is internally shorted to GND. During normal operation, if any under-
voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
Figure 2. Soft Start (with Reference Present)
Vcc |
Vcc Turn-on threshold |
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Vin |
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Vin Turn-on threshold |
Vss |
1V |
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to GND |
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0.5V |
LGATE |
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Vout |
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Timing Diagram |
Acquisition: CH1 = PHASE; CH2 = Vout; |
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CH3 = PGOOD; CH4 = Vss |
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Driver Section
The driver capability on the high and low side drivers allows using different types of power MOS (also multiple MOS to reduce the RDSON), maintaining fast switching transition.
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the high side turn-off.
The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 3.3nF capacitive load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ VCC = 12V and 500mA @ VCC = 5V, and the sink peak current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V.
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ VbootVphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
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L6910A L6910
Figure 3. High Side driver peak current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)
CH1 = High Side Gate CH4 = Gate Current
Figure 4. Low Side driver peak current. VCC = 12V (right) VCC = 5V (left)
CH1 = Low Side Gate CH4 = Gate Current
Monitoring and Protections
The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the powergood output is forced low.
The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.) greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the over-voltage is detected.
Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the
RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship:
ROCS × IOCS
IP = --------------------------------
RdsON
Where the typical value of IOCS is 200mA. To calculate the ROCS value it must be considered the maximum RdsON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied:
7/21